| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFoldOperands.cpp | 197 const MachineOperand &UseOp = UseMI->getOperand(UseOpIdx); in foldOperand() local
200 if (UseOp.isReg() && ((UseOp.getSubReg() && OpToFold.isReg()) || in foldOperand()
201 UseOp.isImplicit())) { in foldOperand()
209 unsigned UseReg = UseOp.getReg(); in foldOperand()
222 if (FoldRC->getSize() == 8 && UseOp.getSubReg()) { in foldOperand()
226 if (UseOp.getSubReg() == AMDGPU::sub0) { in foldOperand()
229 assert(UseOp.getSubReg() == AMDGPU::sub1); in foldOperand()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIFoldOperands.cpp | 317 const MachineOperand &UseOp = UseMI->getOperand(UseOpIdx); in foldOperand() local
319 if (!isUseSafeToFold(TII, *UseMI, UseOp)) in foldOperand()
323 if (UseOp.isReg() && OpToFold.isReg()) { in foldOperand()
324 if (UseOp.isImplicit() || UseOp.getSubReg() != AMDGPU::NoSubRegister) in foldOperand()
336 if (UseOp.isTied() && OpToFold.getSubReg() != AMDGPU::NoSubRegister) in foldOperand()
386 UseOp.isImplicit() || in foldOperand()
407 if (UseOp.getSubReg() && AMDGPU::getRegBitWidth(FoldRC->getID()) == 64) { in foldOperand()
408 unsigned UseReg = UseOp.getReg(); in foldOperand()
418 if (UseOp.getSubReg() == AMDGPU::sub0) { in foldOperand()
421 assert(UseOp.getSubReg() == AMDGPU::sub1); in foldOperand()
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| D | AMDGPUAsmPrinter.cpp | 555 for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) { in hasAnyNonFlatUseOfReg() local
556 if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent())) in hasAnyNonFlatUseOfReg()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | MachineTraceMetrics.cpp | 631 unsigned UseOp; member
633 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp) in DataDep()
634 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} in DataDep()
637 DataDep(const MachineRegisterInfo *MRI, unsigned VirtReg, unsigned UseOp) in DataDep()
638 : UseOp(UseOp) { in DataDep()
806 .computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI, Dep.UseOp); in updateDepth()
961 Dep.UseOp); in pushDepHeight()
1193 &PHI, Dep.UseOp); in getPHIDepth()
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| D | ScheduleDAGInstrs.cpp | 248 int UseOp = I->OpIdx; in addPhysRegDataDeps() local
251 if (UseOp < 0) in addPhysRegDataDeps()
262 UseOp)); in addPhysRegDataDeps()
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| D | MachinePipeliner.cpp | 3380 MachineOperand &UseOp = *UI; in rewriteScheduledInstr() local
3381 MachineInstr *UseMI = UseOp.getParent(); in rewriteScheduledInstr()
3419 UseOp.setReg(ReplaceReg); in rewriteScheduledInstr()
4140 MachineOperand &UseOp = *UI; in finalizeSchedule() local
4141 MachineInstr *UseMI = UseOp.getParent(); in finalizeSchedule()
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| /external/llvm/lib/CodeGen/ |
| D | MachineTraceMetrics.cpp | 608 unsigned UseOp; member
610 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp) in DataDep()
611 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} in DataDep()
614 DataDep(const MachineRegisterInfo *MRI, unsigned VirtReg, unsigned UseOp) in DataDep()
615 : UseOp(UseOp) { in DataDep()
847 .computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI, Dep.UseOp); in computeInstrDepths()
936 Dep.UseOp); in pushDepHeight()
1168 &PHI, Dep.UseOp); in getPHIDepth()
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| D | ScheduleDAGInstrs.cpp | 301 int UseOp = I->OpIdx; in addPhysRegDataDeps() local
304 if (UseOp < 0) in addPhysRegDataDeps()
315 UseOp)); in addPhysRegDataDeps()
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| D | MachinePipeliner.cpp | 3257 MachineOperand &UseOp = *UI; in rewriteScheduledInstr() local
3258 MachineInstr *UseMI = UseOp.getParent(); in rewriteScheduledInstr()
3296 UseOp.setReg(ReplaceReg); in rewriteScheduledInstr()
3870 MachineOperand &UseOp = *UI; in finalizeSchedule() local
3871 MachineInstr *UseMI = UseOp.getParent(); in finalizeSchedule()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 4495 int UseOp = -1; in getPartialRegUpdateClearance() local
4507 UseOp = MI.findRegisterUseOperandIdx(Reg, false, TRI); in getPartialRegUpdateClearance()
4512 UseOp = 3; in getPartialRegUpdateClearance()
4520 if (UseOp != -1 && MI.getOperand(UseOp).readsReg()) in getPartialRegUpdateClearance()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 4890 int UseOp = -1; in getPartialRegUpdateClearance() local
4902 UseOp = MI.findRegisterUseOperandIdx(Reg, false, TRI); in getPartialRegUpdateClearance()
4907 UseOp = 3; in getPartialRegUpdateClearance()
4915 if (UseOp != -1 && MI.getOperand(UseOp).readsReg()) in getPartialRegUpdateClearance()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 3890 SDValue UseOp = User->getOperand(i); in ExtendUsesToFormExtLoad() local
3891 if (UseOp == N0) in ExtendUsesToFormExtLoad()
3893 if (!isa<ConstantSDNode>(UseOp)) in ExtendUsesToFormExtLoad()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 5859 SDValue UseOp = User->getOperand(i); in ExtendUsesToFormExtLoad() local
5860 if (UseOp == N0) in ExtendUsesToFormExtLoad()
5862 if (!isa<ConstantSDNode>(UseOp)) in ExtendUsesToFormExtLoad()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 7985 SDValue UseOp = User->getOperand(i); in ExtendUsesToFormExtLoad() local
7986 if (UseOp == N0) in ExtendUsesToFormExtLoad()
7988 if (!isa<ConstantSDNode>(UseOp)) in ExtendUsesToFormExtLoad()
|