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Searched refs:VLIW5 (Results 1 – 10 of 10) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
DR600Packetizer.cpp62 bool VLIW5; member in __anon18a263af0111::R600PacketizerList
155 VLIW5 = !ST.hasCaymanISA(); in R600PacketizerList()
234 assert (!isTransSlot || VLIW5); in isBundlableWithCurrentPMI()
240 !TII->isVectorOnly(MI) && VLIW5) { in isBundlableWithCurrentPMI()
DR700Instructions.td11 // - Available to R700 and newer VLIW4/VLIW5 GPUs
DR600MachineScheduler.h83 bool VLIW5; variable
DR600MachineScheduler.cpp33 VLIW5 = !ST.hasCaymanISA(); in initialize()
428 if (!TransSlotOccuped && VLIW5) { in pickAlu()
DEvergreenInstructions.td11 // - Available to Evergreen and newer VLIW4/VLIW5 GPUs
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600Packetizer.cpp60 bool VLIW5; member in __anon90d2bde70111::R600PacketizerList
153 VLIW5 = !ST.hasCaymanISA(); in R600PacketizerList()
232 assert (!isTransSlot || VLIW5); in isBundlableWithCurrentPMI()
238 !TII->isVectorOnly(MI) && VLIW5) { in isBundlableWithCurrentPMI()
DR700Instructions.td11 // - Available to R700 and newer VLIW4/VLIW5 GPUs
DR600MachineScheduler.h81 bool VLIW5; variable
DR600MachineScheduler.cpp34 VLIW5 = !ST.hasCaymanISA(); in initialize()
427 if (!TransSlotOccuped && VLIW5) { in pickAlu()
DEvergreenInstructions.td11 // - Available to Evergreen and newer VLIW4/VLIW5 GPUs