Searched refs:VS_32 (Results 1 – 7 of 7) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 381 def VS_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VGPR_32, SReg_32)>;
387 def VSrc_32 : RegisterOperand<VS_32> {
403 def VCSrc_32 : RegisterOperand<VS_32> {
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| D | SIInstructions.td | 1223 (ins VS_32:$src0),
1596 (ins VS_32:$src0, SCSrc_32:$src1),
2039 (ins rc:$src, VS_32:$idx, i32imm:$offset)>;
2043 (ins unknown:$src, VS_32:$idx, i32imm:$offset, VGPR_32:$val)> {
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| /external/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 63 DECODE_OPERAND(VS_32) in DECODE_OPERAND() argument
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 101 DECODE_OPERAND_REG(VS_32) in DECODE_OPERAND_REG() argument
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 548 def VS_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
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| D | SIInstructions.td | 461 (ins rc:$src, VS_32:$idx, i32imm:$offset)> {
467 (ins rc:$src, VS_32:$idx, i32imm:$offset, VGPR_32:$val)> {
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| D | SIInstrInfo.td | 661 class SDWASrc<ValueType vt> : RegisterOperand<VS_32> {
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