Searched refs:XCHG (Results 1 – 18 of 18) sorted by relevance
| /external/strace/xlat/ |
| D | atomic_ops.in | 3 { OR1K_ATOMIC_XCHG, "XCHG" },
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Instrumentation/ |
| D | HWAddressSanitizer.cpp | 346 } else if (AtomicCmpXchgInst *XCHG = dyn_cast<AtomicCmpXchgInst>(I)) { in isInterestingMemoryAccess() local
349 *TypeSize = DL.getTypeStoreSizeInBits(XCHG->getCompareOperand()->getType()); in isInterestingMemoryAccess()
351 PtrOperand = XCHG->getPointerOperand(); in isInterestingMemoryAccess()
379 if (AtomicCmpXchgInst *XCHG = dyn_cast<AtomicCmpXchgInst>(I)) in getPointerOperandIndex() local
380 return XCHG->getPointerOperandIndex(); in getPointerOperandIndex()
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| D | AddressSanitizer.cpp | 1239 } else if (AtomicCmpXchgInst *XCHG = dyn_cast<AtomicCmpXchgInst>(I)) { in isInterestingMemoryAccess() local
1242 *TypeSize = DL.getTypeStoreSizeInBits(XCHG->getCompareOperand()->getType()); in isInterestingMemoryAccess()
1244 PtrOperand = XCHG->getPointerOperand(); in isInterestingMemoryAccess()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ScheduleZnver1.td | 501 // XCHG.
508 def : InstRW<[ZnWriteXCHG], (instregex "XCHG(8|16|32|64)rr", "XCHG(16|32|64)ar")>;
515 def : InstRW<[ZnWriteXCHGrm, ReadAfterLd], (instregex "XCHG(8|16|32|64)rm")>;
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| D | X86ScheduleAtom.td | 569 "XCHG(8|16|32|64)(ar|rr)",
586 "XCHG(8|16|32|64)rm",
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| D | X86SchedHaswell.td | 1373 def: InstRW<[HWWriteResGroup68], (instregex "XCHG(8|16|32|64)rm")>;
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| D | X86SchedSkylakeClient.td | 1442 def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>;
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| D | X86SchedBroadwell.td | 1233 def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>;
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| D | X86SchedSkylakeServer.td | 1932 def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>;
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| D | X86InstrInfo.td | 1994 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap">, NotMemoryFoldable;
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| /external/llvm/lib/Target/X86/ |
| D | X86SchedHaswell.td | 447 // XCHG.
454 def : InstRW<[WriteXCHG], (instregex "XCHG(8|16|32|64)rr", "XCHG(16|32|64)ar")>;
461 def : InstRW<[WriteXCHGrm], (instregex "XCHG(8|16|32|64)rm")>;
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| D | X86InstrInfo.td | 1846 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
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| /external/llvm/lib/Transforms/Instrumentation/ |
| D | AddressSanitizer.cpp | 964 } else if (AtomicCmpXchgInst *XCHG = dyn_cast<AtomicCmpXchgInst>(I)) { in isInterestingMemoryAccess() local
967 *TypeSize = DL.getTypeStoreSizeInBits(XCHG->getCompareOperand()->getType()); in isInterestingMemoryAccess()
969 PtrOperand = XCHG->getPointerOperand(); in isInterestingMemoryAccess()
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| /external/llvm/docs/ |
| D | Atomics.rst | 435 generate an ``XCHG``, other stores generate a ``MOV``. SequentiallyConsistent
438 uses ``XCHG``, ``atomicrmw add`` and ``atomicrmw sub`` use ``XADD``, and all
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| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | Atomics.rst | 435 generate an ``XCHG``, other stores generate a ``MOV``. SequentiallyConsistent
438 uses ``XCHG``, ``atomicrmw add`` and ``atomicrmw sub`` use ``XADD``, and all
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| /external/llvm/test/Transforms/InstCombine/ |
| D | icmp.ll | 1768 ; CHECK-NEXT: [[XCHG:%.*]] = cmpxchg i32* %sc, i32 %old_val, i32 %new_val seq_cst seq_cst
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/ |
| D | icmp.ll | 2445 ; CHECK-NEXT: [[XCHG:%.*]] = cmpxchg i32* %sc, i32 %old_val, i32 %new_val seq_cst seq_cst
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| /external/syzkaller/pkg/ifuzz/gen/ |
| D | all-enc-instructions.txt | 6705 ICLASS : XCHG
6717 ICLASS : XCHG
6729 ICLASS : XCHG
6741 ICLASS : XCHG
6915 ICLASS : XCHG
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