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Searched refs:hasInterval (Results 1 – 25 of 36) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DLiveIntervalAnalysis.h110 if (hasInterval(Reg)) in getInterval()
120 bool hasInterval(unsigned Reg) const { in hasInterval() function
126 assert(!hasInterval(Reg) && "Interval already exists!"); in createEmptyInterval()
DLiveStackAnalysis.h74 bool hasInterval(int Slot) const { return S2IMap.count(Slot); } in hasInterval() function
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DRegisterCoalescer.cpp419 if (!LIS->hasInterval(CP.getDstReg())) in AdjustCopiesBackFrom()
496 if (LIS->hasInterval(*AS) && IntA.overlaps(LIS->getInterval(*AS))) { in AdjustCopiesBackFrom()
526 if (!LIS->hasInterval(*SR)) in AdjustCopiesBackFrom()
625 if (!LIS->hasInterval(CP.getDstReg())) in RemoveCopyByCommutingDef()
688 if (LIS->hasInterval(*AS) && in RemoveCopyByCommutingDef()
1000 if (!LIS->hasInterval(*SR)) in removeIntervalIfEmpty()
1027 if (LIS->hasInterval(DstReg)) { in RemoveCopyFlag()
1036 if (!LIS->hasInterval(*AS)) in RemoveCopyFlag()
1075 if (LIS->hasInterval(CP.getDstReg()) && in shouldJoinPhys()
1435 if (!LIS->hasInterval(*AS)) in JoinIntervals()
[all …]
DVirtRegMap.cpp241 if (Allocatable[Reg] && !Used[Reg] && !LIs->hasInterval(Reg)) { in FindUnusedRegisters()
244 if (Used[*AS] || LIs->hasInterval(*AS)) { in FindUnusedRegisters()
DLiveIntervalAnalysis.cpp695 if (!hasInterval(*AS)) in computeIntervals()
2058 if (allocatableRegs_[*AS] && hasInterval(*AS)) in hasAllocatableSuperReg()
2070 if (!hasAllocatableSuperReg(SuperReg) && hasInterval(SuperReg)) { in getRepresentativeReg()
2111 assert(*AS == SpillReg || !allocatableRegs_[*AS] || !hasInterval(*AS) || in spillPhysRegAroundRegDefsUses()
2116 if (hasInterval(SpillReg)) in spillPhysRegAroundRegDefsUses()
2119 if (hasInterval(*SR)) in spillPhysRegAroundRegDefsUses()
DMachineVerifier.cpp663 if (LiveInts->hasInterval(Reg)) { in visitMachineOperand()
714 if (LiveInts->hasInterval(Reg)) { in visitMachineOperand()
799 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) && in visitMachineOperand()
DLiveRangeEdit.cpp93 if (MO.isUndef() || !lis.hasInterval(MO.getReg())) in allUsesAvailableAt()
DLiveDebugVariables.cpp582 if (!LIS.hasInterval(DstReg)) in addDefsFromCopies()
638 if (Loc.isReg() && LIS.hasInterval(Loc.getReg())) { in computeIntervals()
DInlineSpiller.cpp681 if (!LIS.hasInterval(SVI.SpillReg)) { in hoistSpill()
966 if (!LIS.hasInterval(Reg)) { in reMaterializeAll()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DLiveIntervals.h116 if (hasInterval(Reg)) in getInterval()
126 bool hasInterval(unsigned Reg) const { in hasInterval() function
132 assert(!hasInterval(Reg) && "Interval already exists!"); in createEmptyInterval()
DLiveStacks.h78 bool hasInterval(int Slot) const { return S2IMap.count(Slot); } in hasInterval() function
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DLiveStackAnalysis.h73 bool hasInterval(int Slot) const { in hasInterval() function
DLiveIntervalAnalysis.h98 bool hasInterval(unsigned reg) const { in hasInterval() function
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DRegAllocBase.cpp142 assert(LIS->hasInterval(Reg)); in allocatePhysRegs()
DLiveDebugVariables.cpp534 if (!LIS->hasInterval(Reg)) { in handleDebugValue()
685 if (!LIS.hasInterval(DstReg)) in addDefsFromCopies()
749 if (LIS.hasInterval(LocMO.getReg())) { in computeIntervals()
DRenameIndependentSubregs.cpp395 if (!LIS->hasInterval(Reg)) in runOnMachineFunction()
DLiveRangeEdit.cpp384 if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) { in eliminateDeadDef()
DMachineVerifier.cpp1329 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) && in visitMachineOperand()
1482 if (LiveInts->hasInterval(Reg)) { in checkLiveness()
1584 if (LiveInts->hasInterval(Reg)) { in checkLiveness()
1854 if (!LiveInts->hasInterval(Reg)) { in verifyLiveIntervals()
DStackSlotColoring.cpp173 if (!LS->hasInterval(FI)) in ScanForSpillSlotRefs()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DGCNRegPressure.cpp45 if (!LIS.hasInterval(Reg)) in printLivesAt()
278 if (!LIS.hasInterval(Reg)) in getLiveRegs()
/external/llvm/lib/CodeGen/
DRenameIndependentSubregs.cpp378 if (!LIS->hasInterval(Reg)) in runOnMachineFunction()
DMachineVerifier.cpp1065 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) && in visitMachineOperand()
1218 if (LiveInts->hasInterval(Reg)) { in checkLiveness()
1320 if (LiveInts->hasInterval(Reg)) { in checkLiveness()
1564 if (!LiveInts->hasInterval(Reg)) { in verifyLiveIntervals()
DStackSlotColoring.cpp156 if (!LS->hasInterval(FI)) in ScanForSpillSlotRefs()
DLiveRangeEdit.cpp358 if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) { in eliminateDeadDef()
DLiveDebugVariables.cpp623 if (!LIS.hasInterval(DstReg)) in addDefsFromCopies()
688 if (LIS.hasInterval(Loc.getReg())) { in computeIntervals()

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