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Searched refs:sdr_ctrl (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/drivers/ddr/altera/
Dsdram_gen5.c29 static struct socfpga_sdr_ctrl *sdr_ctrl = variable
114 writel(ruleno, &sdr_ctrl->prot_rule_rdwr); in sdram_set_rule()
126 writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr); in sdram_set_rule()
130 &sdr_ctrl->prot_rule_id); in sdram_set_rule()
135 &sdr_ctrl->prot_rule_data); in sdram_set_rule()
138 writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr); in sdram_set_rule()
141 writel(0, &sdr_ctrl->prot_rule_rdwr); in sdram_set_rule()
152 writel(ruleno, &sdr_ctrl->prot_rule_rdwr); in sdram_get_rule()
153 writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr); in sdram_get_rule()
156 addr = readl(&sdr_ctrl->prot_rule_addr); in sdram_get_rule()
[all …]
Dsequencer.c30 static struct socfpga_sdr_ctrl *sdr_ctrl = variable
3496 ctrl_cfg = readl(&sdr_ctrl->ctrl_cfg); in run_mem_calibrate()
3498 &sdr_ctrl->ctrl_cfg); in run_mem_calibrate()
3519 writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg); in run_mem_calibrate()
3647 writel(reg, &sdr_ctrl->phy_ctrl0); in initialize_hps_phy()
3655 writel(reg, &sdr_ctrl->phy_ctrl1); in initialize_hps_phy()
3661 writel(reg, &sdr_ctrl->phy_ctrl2); in initialize_hps_phy()
/external/u-boot/arch/arm/mach-socfpga/
Dmisc_gen5.c230 static struct socfpga_sdr_ctrl *sdr_ctrl = variable
236 u32 val = readl(&sdr_ctrl->static_cfg) | applymask; in socfpga_sdram_apply_static_cfg()
259 : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc"); in socfpga_sdram_apply_static_cfg()
273 writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); in do_bridge()
279 writel(0, &sdr_ctrl->fpgaport_rst); in do_bridge()