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Searched refs:v1i1 (Results 1 – 23 of 23) sorted by relevance

/external/llvm/test/CodeGen/AArch64/
Daarch64-neon-v1i1-setcc.ll2 ; arm64 has a separate copy as aarch64-neon-v1i1-setcc.ll
4 ; This file test the DAG node like "v1i1 SETCC v1i64, v1i64". As the v1i1 type
10 ; "v1i1 SETCC" correctly, these test cases are not needed.
Darm64-vector-ext.ll18 ; Extend from v1i1 was crashing things (PR20791). Make sure we do something
Dtrunc-v1i64.ll65 ; PR20777: v1i1 is also problematic, but we can't widen it, so we extract_elt
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Daarch64-neon-v1i1-setcc.ll2 ; arm64 has a separate copy as aarch64-neon-v1i1-setcc.ll
4 ; This file test the DAG node like "v1i1 SETCC v1i64, v1i64". As the v1i1 type
10 ; "v1i1 SETCC" correctly, these test cases are not needed.
Darm64-vector-ext.ll18 ; Extend from v1i1 was crashing things (PR20791). Make sure we do something
Dtrunc-v1i64.ll65 ; PR20777: v1i1 is also problematic, but we can't widen it, so we extract_elt
/external/llvm/test/CodeGen/X86/
Dpr28444.ll7 ; i8 = extract_vector_elt v1i1, Constant:i64<0>
8 ; i1 = extract_vector_elt v1i1, Constant:i64<0>
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dpr28444.ll7 ; i8 = extract_vector_elt v1i1, Constant:i64<0>
8 ; i1 = extract_vector_elt v1i1, Constant:i64<0>
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DMachineValueType.h60 v1i1 = 14, // 1 x i1 enumerator
143 FIRST_INTEGER_VECTOR_VALUETYPE = v1i1,
181 FIRST_VECTOR_VALUETYPE = v1i1,
420 case v1i1: in getVectorElementType()
602 case v1i1: in getVectorNumElements()
644 case v1i1: in getSizeInBits()
832 if (NumElements == 1) return MVT::v1i1; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86CallingConv.td82 // Promote i1/i8/i16/v1i1 arguments to i32.
83 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
155 // Promote i1, v1i1, v8i1 arguments to i8.
156 CCIfType<[i1, v1i1, v8i1], CCPromoteToType<i8>>,
216 CCIfType<[v1i1], CCPromoteToType<i8>>,
386 CCIfType<[v1i1], CCPromoteToType<i8>>,
497 // Promote i1/i8/i16/v1i1 arguments to i32.
498 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
596 // Promote i1/v1i1 arguments to i8.
597 CCIfType<[i1, v1i1], CCPromoteToType<i8>>,
[all …]
DX86InstrVecCompiler.td322 def maskzeroupperv1i1 : maskzeroupper<v1i1, VK1>;
409 (v1i1 VK1:$mask), (iPTR 0))),
437 (v1i1 VK1:$mask), (iPTR 0))),
487 (v1i1 VK1:$mask), (iPTR 0))),
500 (v1i1 VK1:$mask), (iPTR 0))),
DX86RegisterInfo.td574 def VK1 : RegisterClass<"X86", [v1i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;}
582 def VK1WM : RegisterClass<"X86", [v1i1], 16, (sub VK1, K0)> {let Size = 16;}
DX86InstrFragmentsSIMD.td255 SDTypeProfile<1, 3, [SDTCisVT<1, v1i1>,
437 SDTypeProfile<1, 2, [SDTCisVT<0, v1i1>,
DX86InstrAVX512.td179 def v1i1_info : X86KVectorVTInfo<VK1, VK1WM, v1i1>;
2659 def : Pat<(v1i1 (X86cmpms (loadf64 addr:$src2), FR64X:$src1,
2663 def : Pat<(v1i1 (X86cmpms (loadf32 addr:$src2), FR32X:$src1,
2899 def : Pat<(v1i1 (load addr:$src)),
2921 defm : operation_gpr_mask_copy_lowering<VK1, v1i1>;
2930 (v1i1 (scalar_to_vector GR8:$src)), (iPTR 0)),
3284 def : Pat<(v1i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK1)>;
3288 def : Pat<(v1i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK1)>;
3300 defm : operation_subvector_mask_lowering<VK1, v1i1, VK2, v2i1>;
3301 defm : operation_subvector_mask_lowering<VK1, v1i1, VK4, v4i1>;
[all …]
DX86ISelLowering.cpp1183 addRegisterClass(MVT::v1i1, &X86::VK1RegClass); in X86TargetLowering()
1189 setOperationAction(ISD::SELECT, MVT::v1i1, Custom); in X86TargetLowering()
1190 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v1i1, Custom); in X86TargetLowering()
1191 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i1, Custom); in X86TargetLowering()
1202 setOperationAction(ISD::LOAD, MVT::v1i1, Custom); in X86TargetLowering()
1207 setOperationAction(ISD::STORE, MVT::v1i1, Custom); in X86TargetLowering()
1242 for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 }) in X86TargetLowering()
2222 if (ValVT == MVT::v1i1) in lowerMasksToReg()
2600 if (ValVT == MVT::v1i1) in lowerRegToMasks()
2601 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Dl, MVT::v1i1, ValReturned); in lowerRegToMasks()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DValueTypes.cpp140 case MVT::v1i1: return "v1i1"; in getEVTString()
221 case MVT::v1i1: return VectorType::get(Type::getInt1Ty(Context), 1); in getTypeForEVT()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenCallingConv.inc378 LocVT == MVT::v1i1) {
564 LocVT == MVT::v1i1) {
772 LocVT == MVT::v1i1) {
815 LocVT == MVT::v1i1) {
1076 LocVT == MVT::v1i1) {
1100 LocVT == MVT::v1i1) {
1393 LocVT == MVT::v1i1) {
1889 LocVT == MVT::v1i1) {
2134 LocVT == MVT::v1i1) {
2321 LocVT == MVT::v1i1) {
[all …]
DX86GenGlobalISel.inc2559 …v1i1] } (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, -1:{ *:[v1i1] }), VK1:{ *:[v1i1] }:$src2) => (…
2593 …v1i1] } VK1:{ *:[v1i1] }:$src2, (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, -1:{ *:[v1i1] })) => (…
2621 …v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KANDW…
3783 …v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KORWr…
4868 …v1i1] } (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, -1:{ *:[v1i1] }), VK1:{ *:[v1i1] }:$src2) => (…
4902 …v1i1] } (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2), -1:{ *:[v1i1] }) => (…
4936 …v1i1] } VK1:{ *:[v1i1] }:$src2, (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, -1:{ *:[v1i1] })) => (…
4964 …v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KXORW…
DX86GenRegisterInfo.inc4012 /* 24 */ MVT::v1i1, MVT::Other,
DX86GenFastISel.inc13374 if (RetVT.SimpleTy != MVT::v1i1)
13383 if (RetVT.SimpleTy != MVT::v1i1)
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DValueTypes.td36 def v1i1 : ValueType<1 , 14>; // 1 x i1 vector value
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenTarget.cpp79 case MVT::v1i1: return "MVT::v1i1"; in getEnumName()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp567 assert(N->getValueType(0) == MVT::v1i1 && "Expected v1i1 type"); in ScalarizeVecOp_VSETCC()