1 /* 2 * Copyright (C) 2016 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ART_COMPILER_OPTIMIZING_CODE_GENERATOR_ARM_VIXL_H_ 18 #define ART_COMPILER_OPTIMIZING_CODE_GENERATOR_ARM_VIXL_H_ 19 20 #include "base/enums.h" 21 #include "code_generator.h" 22 #include "common_arm.h" 23 #include "dex/string_reference.h" 24 #include "dex/type_reference.h" 25 #include "driver/compiler_options.h" 26 #include "nodes.h" 27 #include "parallel_move_resolver.h" 28 #include "utils/arm/assembler_arm_vixl.h" 29 30 // TODO(VIXL): make vixl clean wrt -Wshadow. 31 #pragma GCC diagnostic push 32 #pragma GCC diagnostic ignored "-Wshadow" 33 #include "aarch32/constants-aarch32.h" 34 #include "aarch32/instructions-aarch32.h" 35 #include "aarch32/macro-assembler-aarch32.h" 36 #pragma GCC diagnostic pop 37 38 namespace art { 39 40 namespace linker { 41 class Thumb2RelativePatcherTest; 42 } // namespace linker 43 44 namespace arm { 45 46 // This constant is used as an approximate margin when emission of veneer and literal pools 47 // must be blocked. 48 static constexpr int kMaxMacroInstructionSizeInBytes = 49 15 * vixl::aarch32::kMaxInstructionSizeInBytes; 50 51 static const vixl::aarch32::Register kParameterCoreRegistersVIXL[] = { 52 vixl::aarch32::r1, 53 vixl::aarch32::r2, 54 vixl::aarch32::r3 55 }; 56 static const size_t kParameterCoreRegistersLengthVIXL = arraysize(kParameterCoreRegistersVIXL); 57 static const vixl::aarch32::SRegister kParameterFpuRegistersVIXL[] = { 58 vixl::aarch32::s0, 59 vixl::aarch32::s1, 60 vixl::aarch32::s2, 61 vixl::aarch32::s3, 62 vixl::aarch32::s4, 63 vixl::aarch32::s5, 64 vixl::aarch32::s6, 65 vixl::aarch32::s7, 66 vixl::aarch32::s8, 67 vixl::aarch32::s9, 68 vixl::aarch32::s10, 69 vixl::aarch32::s11, 70 vixl::aarch32::s12, 71 vixl::aarch32::s13, 72 vixl::aarch32::s14, 73 vixl::aarch32::s15 74 }; 75 static const size_t kParameterFpuRegistersLengthVIXL = arraysize(kParameterFpuRegistersVIXL); 76 77 static const vixl::aarch32::Register kMethodRegister = vixl::aarch32::r0; 78 79 static const vixl::aarch32::Register kCoreAlwaysSpillRegister = vixl::aarch32::r5; 80 81 // Callee saves core registers r5, r6, r7, r8 (except when emitting Baker 82 // read barriers, where it is used as Marking Register), r10, r11, and lr. 83 static const vixl::aarch32::RegisterList kCoreCalleeSaves = vixl::aarch32::RegisterList::Union( 84 vixl::aarch32::RegisterList(vixl::aarch32::r5, 85 vixl::aarch32::r6, 86 vixl::aarch32::r7), 87 // Do not consider r8 as a callee-save register with Baker read barriers. 88 ((kEmitCompilerReadBarrier && kUseBakerReadBarrier) 89 ? vixl::aarch32::RegisterList() 90 : vixl::aarch32::RegisterList(vixl::aarch32::r8)), 91 vixl::aarch32::RegisterList(vixl::aarch32::r10, 92 vixl::aarch32::r11, 93 vixl::aarch32::lr)); 94 95 // Callee saves FP registers s16 to s31 inclusive. 96 static const vixl::aarch32::SRegisterList kFpuCalleeSaves = 97 vixl::aarch32::SRegisterList(vixl::aarch32::s16, 16); 98 99 static const vixl::aarch32::Register kRuntimeParameterCoreRegistersVIXL[] = { 100 vixl::aarch32::r0, 101 vixl::aarch32::r1, 102 vixl::aarch32::r2, 103 vixl::aarch32::r3 104 }; 105 static const size_t kRuntimeParameterCoreRegistersLengthVIXL = 106 arraysize(kRuntimeParameterCoreRegistersVIXL); 107 static const vixl::aarch32::SRegister kRuntimeParameterFpuRegistersVIXL[] = { 108 vixl::aarch32::s0, 109 vixl::aarch32::s1, 110 vixl::aarch32::s2, 111 vixl::aarch32::s3 112 }; 113 static const size_t kRuntimeParameterFpuRegistersLengthVIXL = 114 arraysize(kRuntimeParameterFpuRegistersVIXL); 115 116 class LoadClassSlowPathARMVIXL; 117 class CodeGeneratorARMVIXL; 118 119 using VIXLInt32Literal = vixl::aarch32::Literal<int32_t>; 120 using VIXLUInt32Literal = vixl::aarch32::Literal<uint32_t>; 121 122 class JumpTableARMVIXL : public DeletableArenaObject<kArenaAllocSwitchTable> { 123 public: JumpTableARMVIXL(HPackedSwitch * switch_instr)124 explicit JumpTableARMVIXL(HPackedSwitch* switch_instr) 125 : switch_instr_(switch_instr), 126 table_start_(), 127 bb_addresses_(switch_instr->GetAllocator()->Adapter(kArenaAllocCodeGenerator)) { 128 uint32_t num_entries = switch_instr_->GetNumEntries(); 129 for (uint32_t i = 0; i < num_entries; i++) { 130 VIXLInt32Literal *lit = new VIXLInt32Literal(0, vixl32::RawLiteral::kManuallyPlaced); 131 bb_addresses_.emplace_back(lit); 132 } 133 } 134 GetTableStartLabel()135 vixl::aarch32::Label* GetTableStartLabel() { return &table_start_; } 136 137 void EmitTable(CodeGeneratorARMVIXL* codegen); 138 void FixTable(CodeGeneratorARMVIXL* codegen); 139 140 private: 141 HPackedSwitch* const switch_instr_; 142 vixl::aarch32::Label table_start_; 143 ArenaVector<std::unique_ptr<VIXLInt32Literal>> bb_addresses_; 144 145 DISALLOW_COPY_AND_ASSIGN(JumpTableARMVIXL); 146 }; 147 148 class InvokeRuntimeCallingConventionARMVIXL 149 : public CallingConvention<vixl::aarch32::Register, vixl::aarch32::SRegister> { 150 public: InvokeRuntimeCallingConventionARMVIXL()151 InvokeRuntimeCallingConventionARMVIXL() 152 : CallingConvention(kRuntimeParameterCoreRegistersVIXL, 153 kRuntimeParameterCoreRegistersLengthVIXL, 154 kRuntimeParameterFpuRegistersVIXL, 155 kRuntimeParameterFpuRegistersLengthVIXL, 156 kArmPointerSize) {} 157 158 private: 159 DISALLOW_COPY_AND_ASSIGN(InvokeRuntimeCallingConventionARMVIXL); 160 }; 161 162 class InvokeDexCallingConventionARMVIXL 163 : public CallingConvention<vixl::aarch32::Register, vixl::aarch32::SRegister> { 164 public: InvokeDexCallingConventionARMVIXL()165 InvokeDexCallingConventionARMVIXL() 166 : CallingConvention(kParameterCoreRegistersVIXL, 167 kParameterCoreRegistersLengthVIXL, 168 kParameterFpuRegistersVIXL, 169 kParameterFpuRegistersLengthVIXL, 170 kArmPointerSize) {} 171 172 private: 173 DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConventionARMVIXL); 174 }; 175 176 class InvokeDexCallingConventionVisitorARMVIXL : public InvokeDexCallingConventionVisitor { 177 public: InvokeDexCallingConventionVisitorARMVIXL()178 InvokeDexCallingConventionVisitorARMVIXL() {} ~InvokeDexCallingConventionVisitorARMVIXL()179 virtual ~InvokeDexCallingConventionVisitorARMVIXL() {} 180 181 Location GetNextLocation(DataType::Type type) override; 182 Location GetReturnLocation(DataType::Type type) const override; 183 Location GetMethodLocation() const override; 184 185 private: 186 InvokeDexCallingConventionARMVIXL calling_convention; 187 uint32_t double_index_ = 0; 188 189 DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConventionVisitorARMVIXL); 190 }; 191 192 class FieldAccessCallingConventionARMVIXL : public FieldAccessCallingConvention { 193 public: FieldAccessCallingConventionARMVIXL()194 FieldAccessCallingConventionARMVIXL() {} 195 GetObjectLocation()196 Location GetObjectLocation() const override { 197 return helpers::LocationFrom(vixl::aarch32::r1); 198 } GetFieldIndexLocation()199 Location GetFieldIndexLocation() const override { 200 return helpers::LocationFrom(vixl::aarch32::r0); 201 } GetReturnLocation(DataType::Type type)202 Location GetReturnLocation(DataType::Type type) const override { 203 return DataType::Is64BitType(type) 204 ? helpers::LocationFrom(vixl::aarch32::r0, vixl::aarch32::r1) 205 : helpers::LocationFrom(vixl::aarch32::r0); 206 } GetSetValueLocation(DataType::Type type,bool is_instance)207 Location GetSetValueLocation(DataType::Type type, bool is_instance) const override { 208 return DataType::Is64BitType(type) 209 ? helpers::LocationFrom(vixl::aarch32::r2, vixl::aarch32::r3) 210 : (is_instance 211 ? helpers::LocationFrom(vixl::aarch32::r2) 212 : helpers::LocationFrom(vixl::aarch32::r1)); 213 } GetFpuLocation(DataType::Type type)214 Location GetFpuLocation(DataType::Type type) const override { 215 return DataType::Is64BitType(type) 216 ? helpers::LocationFrom(vixl::aarch32::s0, vixl::aarch32::s1) 217 : helpers::LocationFrom(vixl::aarch32::s0); 218 } 219 220 private: 221 DISALLOW_COPY_AND_ASSIGN(FieldAccessCallingConventionARMVIXL); 222 }; 223 224 class SlowPathCodeARMVIXL : public SlowPathCode { 225 public: SlowPathCodeARMVIXL(HInstruction * instruction)226 explicit SlowPathCodeARMVIXL(HInstruction* instruction) 227 : SlowPathCode(instruction), entry_label_(), exit_label_() {} 228 GetEntryLabel()229 vixl::aarch32::Label* GetEntryLabel() { return &entry_label_; } GetExitLabel()230 vixl::aarch32::Label* GetExitLabel() { return &exit_label_; } 231 232 void SaveLiveRegisters(CodeGenerator* codegen, LocationSummary* locations) override; 233 void RestoreLiveRegisters(CodeGenerator* codegen, LocationSummary* locations) override; 234 235 private: 236 vixl::aarch32::Label entry_label_; 237 vixl::aarch32::Label exit_label_; 238 239 DISALLOW_COPY_AND_ASSIGN(SlowPathCodeARMVIXL); 240 }; 241 242 class ParallelMoveResolverARMVIXL : public ParallelMoveResolverWithSwap { 243 public: ParallelMoveResolverARMVIXL(ArenaAllocator * allocator,CodeGeneratorARMVIXL * codegen)244 ParallelMoveResolverARMVIXL(ArenaAllocator* allocator, CodeGeneratorARMVIXL* codegen) 245 : ParallelMoveResolverWithSwap(allocator), codegen_(codegen) {} 246 247 void EmitMove(size_t index) override; 248 void EmitSwap(size_t index) override; 249 void SpillScratch(int reg) override; 250 void RestoreScratch(int reg) override; 251 252 ArmVIXLAssembler* GetAssembler() const; 253 254 private: 255 void Exchange(vixl32::Register reg, int mem); 256 void Exchange(int mem1, int mem2); 257 258 CodeGeneratorARMVIXL* const codegen_; 259 260 DISALLOW_COPY_AND_ASSIGN(ParallelMoveResolverARMVIXL); 261 }; 262 263 class LocationsBuilderARMVIXL : public HGraphVisitor { 264 public: LocationsBuilderARMVIXL(HGraph * graph,CodeGeneratorARMVIXL * codegen)265 LocationsBuilderARMVIXL(HGraph* graph, CodeGeneratorARMVIXL* codegen) 266 : HGraphVisitor(graph), codegen_(codegen) {} 267 268 #define DECLARE_VISIT_INSTRUCTION(name, super) \ 269 void Visit##name(H##name* instr) override; 270 271 FOR_EACH_CONCRETE_INSTRUCTION_COMMON(DECLARE_VISIT_INSTRUCTION) FOR_EACH_CONCRETE_INSTRUCTION_ARM(DECLARE_VISIT_INSTRUCTION)272 FOR_EACH_CONCRETE_INSTRUCTION_ARM(DECLARE_VISIT_INSTRUCTION) 273 FOR_EACH_CONCRETE_INSTRUCTION_SHARED(DECLARE_VISIT_INSTRUCTION) 274 275 #undef DECLARE_VISIT_INSTRUCTION 276 277 void VisitInstruction(HInstruction* instruction) override { 278 LOG(FATAL) << "Unreachable instruction " << instruction->DebugName() 279 << " (id " << instruction->GetId() << ")"; 280 } 281 282 private: 283 void HandleInvoke(HInvoke* invoke); 284 void HandleBitwiseOperation(HBinaryOperation* operation, Opcode opcode); 285 void HandleCondition(HCondition* condition); 286 void HandleIntegerRotate(LocationSummary* locations); 287 void HandleLongRotate(LocationSummary* locations); 288 void HandleShift(HBinaryOperation* operation); 289 void HandleFieldSet(HInstruction* instruction, const FieldInfo& field_info); 290 void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info); 291 292 Location ArithmeticZeroOrFpuRegister(HInstruction* input); 293 Location ArmEncodableConstantOrRegister(HInstruction* constant, Opcode opcode); 294 bool CanEncodeConstantAsImmediate(HConstant* input_cst, Opcode opcode); 295 296 CodeGeneratorARMVIXL* const codegen_; 297 InvokeDexCallingConventionVisitorARMVIXL parameter_visitor_; 298 299 DISALLOW_COPY_AND_ASSIGN(LocationsBuilderARMVIXL); 300 }; 301 302 class InstructionCodeGeneratorARMVIXL : public InstructionCodeGenerator { 303 public: 304 InstructionCodeGeneratorARMVIXL(HGraph* graph, CodeGeneratorARMVIXL* codegen); 305 306 #define DECLARE_VISIT_INSTRUCTION(name, super) \ 307 void Visit##name(H##name* instr) override; 308 309 FOR_EACH_CONCRETE_INSTRUCTION_COMMON(DECLARE_VISIT_INSTRUCTION) FOR_EACH_CONCRETE_INSTRUCTION_ARM(DECLARE_VISIT_INSTRUCTION)310 FOR_EACH_CONCRETE_INSTRUCTION_ARM(DECLARE_VISIT_INSTRUCTION) 311 FOR_EACH_CONCRETE_INSTRUCTION_SHARED(DECLARE_VISIT_INSTRUCTION) 312 313 #undef DECLARE_VISIT_INSTRUCTION 314 315 void VisitInstruction(HInstruction* instruction) override { 316 LOG(FATAL) << "Unreachable instruction " << instruction->DebugName() 317 << " (id " << instruction->GetId() << ")"; 318 } 319 GetAssembler()320 ArmVIXLAssembler* GetAssembler() const { return assembler_; } GetVIXLAssembler()321 ArmVIXLMacroAssembler* GetVIXLAssembler() { return GetAssembler()->GetVIXLAssembler(); } 322 323 private: 324 // Generate code for the given suspend check. If not null, `successor` 325 // is the block to branch to if the suspend check is not needed, and after 326 // the suspend call. 327 void GenerateSuspendCheck(HSuspendCheck* instruction, HBasicBlock* successor); 328 void GenerateClassInitializationCheck(LoadClassSlowPathARMVIXL* slow_path, 329 vixl32::Register class_reg); 330 void GenerateBitstringTypeCheckCompare(HTypeCheckInstruction* check, 331 vixl::aarch32::Register temp, 332 vixl::aarch32::FlagsUpdate flags_update); 333 void GenerateAndConst(vixl::aarch32::Register out, vixl::aarch32::Register first, uint32_t value); 334 void GenerateOrrConst(vixl::aarch32::Register out, vixl::aarch32::Register first, uint32_t value); 335 void GenerateEorConst(vixl::aarch32::Register out, vixl::aarch32::Register first, uint32_t value); 336 void GenerateAddLongConst(Location out, Location first, uint64_t value); 337 void HandleBitwiseOperation(HBinaryOperation* operation); 338 void HandleCondition(HCondition* condition); 339 void HandleIntegerRotate(HRor* ror); 340 void HandleLongRotate(HRor* ror); 341 void HandleShift(HBinaryOperation* operation); 342 343 void GenerateWideAtomicStore(vixl::aarch32::Register addr, 344 uint32_t offset, 345 vixl::aarch32::Register value_lo, 346 vixl::aarch32::Register value_hi, 347 vixl::aarch32::Register temp1, 348 vixl::aarch32::Register temp2, 349 HInstruction* instruction); 350 void GenerateWideAtomicLoad(vixl::aarch32::Register addr, 351 uint32_t offset, 352 vixl::aarch32::Register out_lo, 353 vixl::aarch32::Register out_hi); 354 355 void HandleFieldSet(HInstruction* instruction, 356 const FieldInfo& field_info, 357 bool value_can_be_null); 358 void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info); 359 360 void GenerateMinMaxInt(LocationSummary* locations, bool is_min); 361 void GenerateMinMaxLong(LocationSummary* locations, bool is_min); 362 void GenerateMinMaxFloat(HInstruction* minmax, bool is_min); 363 void GenerateMinMaxDouble(HInstruction* minmax, bool is_min); 364 void GenerateMinMax(HBinaryOperation* minmax, bool is_min); 365 366 // Generate a heap reference load using one register `out`: 367 // 368 // out <- *(out + offset) 369 // 370 // while honoring heap poisoning and/or read barriers (if any). 371 // 372 // Location `maybe_temp` is used when generating a read barrier and 373 // shall be a register in that case; it may be an invalid location 374 // otherwise. 375 void GenerateReferenceLoadOneRegister(HInstruction* instruction, 376 Location out, 377 uint32_t offset, 378 Location maybe_temp, 379 ReadBarrierOption read_barrier_option); 380 // Generate a heap reference load using two different registers 381 // `out` and `obj`: 382 // 383 // out <- *(obj + offset) 384 // 385 // while honoring heap poisoning and/or read barriers (if any). 386 // 387 // Location `maybe_temp` is used when generating a Baker's (fast 388 // path) read barrier and shall be a register in that case; it may 389 // be an invalid location otherwise. 390 void GenerateReferenceLoadTwoRegisters(HInstruction* instruction, 391 Location out, 392 Location obj, 393 uint32_t offset, 394 Location maybe_temp, 395 ReadBarrierOption read_barrier_option); 396 void GenerateTestAndBranch(HInstruction* instruction, 397 size_t condition_input_index, 398 vixl::aarch32::Label* true_target, 399 vixl::aarch32::Label* false_target, 400 bool far_target = true); 401 void GenerateCompareTestAndBranch(HCondition* condition, 402 vixl::aarch32::Label* true_target, 403 vixl::aarch32::Label* false_target, 404 bool is_far_target = true); 405 void DivRemOneOrMinusOne(HBinaryOperation* instruction); 406 void DivRemByPowerOfTwo(HBinaryOperation* instruction); 407 void GenerateDivRemWithAnyConstant(HBinaryOperation* instruction); 408 void GenerateDivRemConstantIntegral(HBinaryOperation* instruction); 409 void HandleGoto(HInstruction* got, HBasicBlock* successor); 410 411 vixl::aarch32::MemOperand VecAddress( 412 HVecMemoryOperation* instruction, 413 // This function may acquire a scratch register. 414 vixl::aarch32::UseScratchRegisterScope* temps_scope, 415 /*out*/ vixl32::Register* scratch); 416 vixl::aarch32::AlignedMemOperand VecAddressUnaligned( 417 HVecMemoryOperation* instruction, 418 // This function may acquire a scratch register. 419 vixl::aarch32::UseScratchRegisterScope* temps_scope, 420 /*out*/ vixl32::Register* scratch); 421 422 ArmVIXLAssembler* const assembler_; 423 CodeGeneratorARMVIXL* const codegen_; 424 425 DISALLOW_COPY_AND_ASSIGN(InstructionCodeGeneratorARMVIXL); 426 }; 427 428 class CodeGeneratorARMVIXL : public CodeGenerator { 429 public: 430 CodeGeneratorARMVIXL(HGraph* graph, 431 const CompilerOptions& compiler_options, 432 OptimizingCompilerStats* stats = nullptr); ~CodeGeneratorARMVIXL()433 virtual ~CodeGeneratorARMVIXL() {} 434 435 void GenerateFrameEntry() override; 436 void GenerateFrameExit() override; 437 void Bind(HBasicBlock* block) override; 438 void MoveConstant(Location destination, int32_t value) override; 439 void MoveLocation(Location dst, Location src, DataType::Type dst_type) override; 440 void AddLocationAsTemp(Location location, LocationSummary* locations) override; 441 442 size_t SaveCoreRegister(size_t stack_index, uint32_t reg_id) override; 443 size_t RestoreCoreRegister(size_t stack_index, uint32_t reg_id) override; 444 size_t SaveFloatingPointRegister(size_t stack_index, uint32_t reg_id) override; 445 size_t RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) override; 446 GetWordSize()447 size_t GetWordSize() const override { 448 return static_cast<size_t>(kArmPointerSize); 449 } 450 GetFloatingPointSpillSlotSize()451 size_t GetFloatingPointSpillSlotSize() const override { return vixl::aarch32::kRegSizeInBytes; } 452 GetLocationBuilder()453 HGraphVisitor* GetLocationBuilder() override { return &location_builder_; } 454 GetInstructionVisitor()455 HGraphVisitor* GetInstructionVisitor() override { return &instruction_visitor_; } 456 GetAssembler()457 ArmVIXLAssembler* GetAssembler() override { return &assembler_; } 458 GetAssembler()459 const ArmVIXLAssembler& GetAssembler() const override { return assembler_; } 460 GetVIXLAssembler()461 ArmVIXLMacroAssembler* GetVIXLAssembler() { return GetAssembler()->GetVIXLAssembler(); } 462 GetAddressOf(HBasicBlock * block)463 uintptr_t GetAddressOf(HBasicBlock* block) override { 464 vixl::aarch32::Label* block_entry_label = GetLabelOf(block); 465 DCHECK(block_entry_label->IsBound()); 466 return block_entry_label->GetLocation(); 467 } 468 469 void FixJumpTables(); 470 void SetupBlockedRegisters() const override; 471 472 void DumpCoreRegister(std::ostream& stream, int reg) const override; 473 void DumpFloatingPointRegister(std::ostream& stream, int reg) const override; 474 GetMoveResolver()475 ParallelMoveResolver* GetMoveResolver() override { return &move_resolver_; } GetInstructionSet()476 InstructionSet GetInstructionSet() const override { return InstructionSet::kThumb2; } 477 478 const ArmInstructionSetFeatures& GetInstructionSetFeatures() const; 479 480 // Helper method to move a 32-bit value between two locations. 481 void Move32(Location destination, Location source); 482 483 void LoadFromShiftedRegOffset(DataType::Type type, 484 Location out_loc, 485 vixl::aarch32::Register base, 486 vixl::aarch32::Register reg_index, 487 vixl::aarch32::Condition cond = vixl::aarch32::al); 488 void StoreToShiftedRegOffset(DataType::Type type, 489 Location out_loc, 490 vixl::aarch32::Register base, 491 vixl::aarch32::Register reg_index, 492 vixl::aarch32::Condition cond = vixl::aarch32::al); 493 494 // Generate code to invoke a runtime entry point. 495 void InvokeRuntime(QuickEntrypointEnum entrypoint, 496 HInstruction* instruction, 497 uint32_t dex_pc, 498 SlowPathCode* slow_path = nullptr) override; 499 500 // Generate code to invoke a runtime entry point, but do not record 501 // PC-related information in a stack map. 502 void InvokeRuntimeWithoutRecordingPcInfo(int32_t entry_point_offset, 503 HInstruction* instruction, 504 SlowPathCode* slow_path); 505 506 // Emit a write barrier. 507 void MarkGCCard(vixl::aarch32::Register temp, 508 vixl::aarch32::Register card, 509 vixl::aarch32::Register object, 510 vixl::aarch32::Register value, 511 bool can_be_null); 512 513 void GenerateMemoryBarrier(MemBarrierKind kind); 514 GetLabelOf(HBasicBlock * block)515 vixl::aarch32::Label* GetLabelOf(HBasicBlock* block) { 516 block = FirstNonEmptyBlock(block); 517 return &(block_labels_[block->GetBlockId()]); 518 } 519 520 vixl32::Label* GetFinalLabel(HInstruction* instruction, vixl32::Label* final_label); 521 Initialize()522 void Initialize() override { 523 block_labels_.resize(GetGraph()->GetBlocks().size()); 524 } 525 526 void Finalize(CodeAllocator* allocator) override; 527 NeedsTwoRegisters(DataType::Type type)528 bool NeedsTwoRegisters(DataType::Type type) const override { 529 return type == DataType::Type::kFloat64 || type == DataType::Type::kInt64; 530 } 531 532 void ComputeSpillMask() override; 533 GetFrameEntryLabel()534 vixl::aarch32::Label* GetFrameEntryLabel() { return &frame_entry_label_; } 535 536 // Check if the desired_string_load_kind is supported. If it is, return it, 537 // otherwise return a fall-back kind that should be used instead. 538 HLoadString::LoadKind GetSupportedLoadStringKind( 539 HLoadString::LoadKind desired_string_load_kind) override; 540 541 // Check if the desired_class_load_kind is supported. If it is, return it, 542 // otherwise return a fall-back kind that should be used instead. 543 HLoadClass::LoadKind GetSupportedLoadClassKind( 544 HLoadClass::LoadKind desired_class_load_kind) override; 545 546 // Check if the desired_dispatch_info is supported. If it is, return it, 547 // otherwise return a fall-back info that should be used instead. 548 HInvokeStaticOrDirect::DispatchInfo GetSupportedInvokeStaticOrDirectDispatch( 549 const HInvokeStaticOrDirect::DispatchInfo& desired_dispatch_info, 550 ArtMethod* method) override; 551 552 void GenerateStaticOrDirectCall( 553 HInvokeStaticOrDirect* invoke, Location temp, SlowPathCode* slow_path = nullptr) override; 554 void GenerateVirtualCall( 555 HInvokeVirtual* invoke, Location temp, SlowPathCode* slow_path = nullptr) override; 556 557 void MoveFromReturnRegister(Location trg, DataType::Type type) override; 558 559 // The PcRelativePatchInfo is used for PC-relative addressing of methods/strings/types, 560 // whether through .data.bimg.rel.ro, .bss, or directly in the boot image. 561 // 562 // The PC-relative address is loaded with three instructions, 563 // MOVW+MOVT to load the offset to base_reg and then ADD base_reg, PC. The offset 564 // is calculated from the ADD's effective PC, i.e. PC+4 on Thumb2. Though we 565 // currently emit these 3 instructions together, instruction scheduling could 566 // split this sequence apart, so we keep separate labels for each of them. 567 struct PcRelativePatchInfo { PcRelativePatchInfoPcRelativePatchInfo568 PcRelativePatchInfo(const DexFile* dex_file, uint32_t off_or_idx) 569 : target_dex_file(dex_file), offset_or_index(off_or_idx) { } 570 PcRelativePatchInfo(PcRelativePatchInfo&& other) = default; 571 572 // Target dex file or null for .data.bmig.rel.ro patches. 573 const DexFile* target_dex_file; 574 // Either the boot image offset (to write to .data.bmig.rel.ro) or string/type/method index. 575 uint32_t offset_or_index; 576 vixl::aarch32::Label movw_label; 577 vixl::aarch32::Label movt_label; 578 vixl::aarch32::Label add_pc_label; 579 }; 580 581 PcRelativePatchInfo* NewBootImageIntrinsicPatch(uint32_t intrinsic_data); 582 PcRelativePatchInfo* NewBootImageRelRoPatch(uint32_t boot_image_offset); 583 PcRelativePatchInfo* NewBootImageMethodPatch(MethodReference target_method); 584 PcRelativePatchInfo* NewMethodBssEntryPatch(MethodReference target_method); 585 PcRelativePatchInfo* NewBootImageTypePatch(const DexFile& dex_file, dex::TypeIndex type_index); 586 PcRelativePatchInfo* NewTypeBssEntryPatch(const DexFile& dex_file, dex::TypeIndex type_index); 587 PcRelativePatchInfo* NewBootImageStringPatch(const DexFile& dex_file, 588 dex::StringIndex string_index); 589 PcRelativePatchInfo* NewStringBssEntryPatch(const DexFile& dex_file, 590 dex::StringIndex string_index); 591 592 // Emit the BNE instruction for baker read barrier and record 593 // the associated patch for AOT or slow path for JIT. 594 void EmitBakerReadBarrierBne(uint32_t custom_data); 595 596 VIXLUInt32Literal* DeduplicateBootImageAddressLiteral(uint32_t address); 597 VIXLUInt32Literal* DeduplicateJitStringLiteral(const DexFile& dex_file, 598 dex::StringIndex string_index, 599 Handle<mirror::String> handle); 600 VIXLUInt32Literal* DeduplicateJitClassLiteral(const DexFile& dex_file, 601 dex::TypeIndex type_index, 602 Handle<mirror::Class> handle); 603 604 void LoadBootImageAddress(vixl::aarch32::Register reg, uint32_t boot_image_reference); 605 void AllocateInstanceForIntrinsic(HInvokeStaticOrDirect* invoke, uint32_t boot_image_offset); 606 607 void EmitLinkerPatches(ArenaVector<linker::LinkerPatch>* linker_patches) override; 608 bool NeedsThunkCode(const linker::LinkerPatch& patch) const override; 609 void EmitThunkCode(const linker::LinkerPatch& patch, 610 /*out*/ ArenaVector<uint8_t>* code, 611 /*out*/ std::string* debug_name) override; 612 613 void EmitJitRootPatches(uint8_t* code, const uint8_t* roots_data) override; 614 615 // Generate a GC root reference load: 616 // 617 // root <- *(obj + offset) 618 // 619 // while honoring read barriers based on read_barrier_option. 620 void GenerateGcRootFieldLoad(HInstruction* instruction, 621 Location root, 622 vixl::aarch32::Register obj, 623 uint32_t offset, 624 ReadBarrierOption read_barrier_option); 625 // Generate ADD for UnsafeCASObject to reconstruct the old value from 626 // `old_value - expected` and mark it with Baker read barrier. 627 void GenerateUnsafeCasOldValueAddWithBakerReadBarrier(vixl::aarch32::Register old_value, 628 vixl::aarch32::Register adjusted_old_value, 629 vixl::aarch32::Register expected); 630 // Fast path implementation of ReadBarrier::Barrier for a heap 631 // reference field load when Baker's read barriers are used. 632 // Overload suitable for Unsafe.getObject/-Volatile() intrinsic. 633 void GenerateFieldLoadWithBakerReadBarrier(HInstruction* instruction, 634 Location ref, 635 vixl::aarch32::Register obj, 636 const vixl::aarch32::MemOperand& src, 637 bool needs_null_check); 638 // Fast path implementation of ReadBarrier::Barrier for a heap 639 // reference field load when Baker's read barriers are used. 640 void GenerateFieldLoadWithBakerReadBarrier(HInstruction* instruction, 641 Location ref, 642 vixl::aarch32::Register obj, 643 uint32_t offset, 644 Location temp, 645 bool needs_null_check); 646 // Fast path implementation of ReadBarrier::Barrier for a heap 647 // reference array load when Baker's read barriers are used. 648 void GenerateArrayLoadWithBakerReadBarrier(Location ref, 649 vixl::aarch32::Register obj, 650 uint32_t data_offset, 651 Location index, 652 Location temp, 653 bool needs_null_check); 654 655 // Emit code checking the status of the Marking Register, and 656 // aborting the program if MR does not match the value stored in the 657 // art::Thread object. Code is only emitted in debug mode and if 658 // CompilerOptions::EmitRunTimeChecksInDebugMode returns true. 659 // 660 // Argument `code` is used to identify the different occurrences of 661 // MaybeGenerateMarkingRegisterCheck in the code generator, and is 662 // used together with kMarkingRegisterCheckBreakCodeBaseCode to 663 // create the value passed to the BKPT instruction. Note that unlike 664 // in the ARM64 code generator, where `__LINE__` is passed as `code` 665 // argument to 666 // CodeGeneratorARM64::MaybeGenerateMarkingRegisterCheck, we cannot 667 // realistically do that here, as Encoding T1 for the BKPT 668 // instruction only accepts 8-bit immediate values. 669 // 670 // If `temp_loc` is a valid location, it is expected to be a 671 // register and will be used as a temporary to generate code; 672 // otherwise, a temporary will be fetched from the core register 673 // scratch pool. 674 virtual void MaybeGenerateMarkingRegisterCheck(int code, 675 Location temp_loc = Location::NoLocation()); 676 677 // Generate a read barrier for a heap reference within `instruction` 678 // using a slow path. 679 // 680 // A read barrier for an object reference read from the heap is 681 // implemented as a call to the artReadBarrierSlow runtime entry 682 // point, which is passed the values in locations `ref`, `obj`, and 683 // `offset`: 684 // 685 // mirror::Object* artReadBarrierSlow(mirror::Object* ref, 686 // mirror::Object* obj, 687 // uint32_t offset); 688 // 689 // The `out` location contains the value returned by 690 // artReadBarrierSlow. 691 // 692 // When `index` is provided (i.e. for array accesses), the offset 693 // value passed to artReadBarrierSlow is adjusted to take `index` 694 // into account. 695 void GenerateReadBarrierSlow(HInstruction* instruction, 696 Location out, 697 Location ref, 698 Location obj, 699 uint32_t offset, 700 Location index = Location::NoLocation()); 701 702 // If read barriers are enabled, generate a read barrier for a heap 703 // reference using a slow path. If heap poisoning is enabled, also 704 // unpoison the reference in `out`. 705 void MaybeGenerateReadBarrierSlow(HInstruction* instruction, 706 Location out, 707 Location ref, 708 Location obj, 709 uint32_t offset, 710 Location index = Location::NoLocation()); 711 712 // Generate a read barrier for a GC root within `instruction` using 713 // a slow path. 714 // 715 // A read barrier for an object reference GC root is implemented as 716 // a call to the artReadBarrierForRootSlow runtime entry point, 717 // which is passed the value in location `root`: 718 // 719 // mirror::Object* artReadBarrierForRootSlow(GcRoot<mirror::Object>* root); 720 // 721 // The `out` location contains the value returned by 722 // artReadBarrierForRootSlow. 723 void GenerateReadBarrierForRootSlow(HInstruction* instruction, Location out, Location root); 724 725 void GenerateNop() override; 726 727 void GenerateImplicitNullCheck(HNullCheck* instruction) override; 728 void GenerateExplicitNullCheck(HNullCheck* instruction) override; 729 CreateJumpTable(HPackedSwitch * switch_instr)730 JumpTableARMVIXL* CreateJumpTable(HPackedSwitch* switch_instr) { 731 jump_tables_.emplace_back(new (GetGraph()->GetAllocator()) JumpTableARMVIXL(switch_instr)); 732 return jump_tables_.back().get(); 733 } 734 void EmitJumpTables(); 735 736 void EmitMovwMovtPlaceholder(CodeGeneratorARMVIXL::PcRelativePatchInfo* labels, 737 vixl::aarch32::Register out); 738 739 // `temp` is an extra temporary register that is used for some conditions; 740 // callers may not specify it, in which case the method will use a scratch 741 // register instead. 742 void GenerateConditionWithZero(IfCondition condition, 743 vixl::aarch32::Register out, 744 vixl::aarch32::Register in, 745 vixl::aarch32::Register temp = vixl32::Register()); 746 747 private: 748 // Encoding of thunk type and data for link-time generated thunks for Baker read barriers. 749 750 enum class BakerReadBarrierKind : uint8_t { 751 kField, // Field get or array get with constant offset (i.e. constant index). 752 kArray, // Array get with index in register. 753 kGcRoot, // GC root load. 754 kUnsafeCas, // UnsafeCASObject intrinsic. 755 kLast = kUnsafeCas 756 }; 757 758 enum class BakerReadBarrierWidth : uint8_t { 759 kWide, // 32-bit LDR (and 32-bit NEG if heap poisoning is enabled). 760 kNarrow, // 16-bit LDR (and 16-bit NEG if heap poisoning is enabled). 761 kLast = kNarrow 762 }; 763 764 static constexpr uint32_t kBakerReadBarrierInvalidEncodedReg = /* pc is invalid */ 15u; 765 766 static constexpr size_t kBitsForBakerReadBarrierKind = 767 MinimumBitsToStore(static_cast<size_t>(BakerReadBarrierKind::kLast)); 768 static constexpr size_t kBakerReadBarrierBitsForRegister = 769 MinimumBitsToStore(kBakerReadBarrierInvalidEncodedReg); 770 using BakerReadBarrierKindField = 771 BitField<BakerReadBarrierKind, 0, kBitsForBakerReadBarrierKind>; 772 using BakerReadBarrierFirstRegField = 773 BitField<uint32_t, kBitsForBakerReadBarrierKind, kBakerReadBarrierBitsForRegister>; 774 using BakerReadBarrierSecondRegField = 775 BitField<uint32_t, 776 kBitsForBakerReadBarrierKind + kBakerReadBarrierBitsForRegister, 777 kBakerReadBarrierBitsForRegister>; 778 static constexpr size_t kBitsForBakerReadBarrierWidth = 779 MinimumBitsToStore(static_cast<size_t>(BakerReadBarrierWidth::kLast)); 780 using BakerReadBarrierWidthField = 781 BitField<BakerReadBarrierWidth, 782 kBitsForBakerReadBarrierKind + 2 * kBakerReadBarrierBitsForRegister, 783 kBitsForBakerReadBarrierWidth>; 784 CheckValidReg(uint32_t reg)785 static void CheckValidReg(uint32_t reg) { 786 DCHECK(reg < vixl::aarch32::ip.GetCode() && reg != mr.GetCode()) << reg; 787 } 788 EncodeBakerReadBarrierFieldData(uint32_t base_reg,uint32_t holder_reg,bool narrow)789 static uint32_t EncodeBakerReadBarrierFieldData(uint32_t base_reg, 790 uint32_t holder_reg, 791 bool narrow) { 792 CheckValidReg(base_reg); 793 CheckValidReg(holder_reg); 794 DCHECK(!narrow || base_reg < 8u) << base_reg; 795 BakerReadBarrierWidth width = 796 narrow ? BakerReadBarrierWidth::kNarrow : BakerReadBarrierWidth::kWide; 797 return BakerReadBarrierKindField::Encode(BakerReadBarrierKind::kField) | 798 BakerReadBarrierFirstRegField::Encode(base_reg) | 799 BakerReadBarrierSecondRegField::Encode(holder_reg) | 800 BakerReadBarrierWidthField::Encode(width); 801 } 802 EncodeBakerReadBarrierArrayData(uint32_t base_reg)803 static uint32_t EncodeBakerReadBarrierArrayData(uint32_t base_reg) { 804 CheckValidReg(base_reg); 805 return BakerReadBarrierKindField::Encode(BakerReadBarrierKind::kArray) | 806 BakerReadBarrierFirstRegField::Encode(base_reg) | 807 BakerReadBarrierSecondRegField::Encode(kBakerReadBarrierInvalidEncodedReg) | 808 BakerReadBarrierWidthField::Encode(BakerReadBarrierWidth::kWide); 809 } 810 EncodeBakerReadBarrierGcRootData(uint32_t root_reg,bool narrow)811 static uint32_t EncodeBakerReadBarrierGcRootData(uint32_t root_reg, bool narrow) { 812 CheckValidReg(root_reg); 813 DCHECK(!narrow || root_reg < 8u) << root_reg; 814 BakerReadBarrierWidth width = 815 narrow ? BakerReadBarrierWidth::kNarrow : BakerReadBarrierWidth::kWide; 816 return BakerReadBarrierKindField::Encode(BakerReadBarrierKind::kGcRoot) | 817 BakerReadBarrierFirstRegField::Encode(root_reg) | 818 BakerReadBarrierSecondRegField::Encode(kBakerReadBarrierInvalidEncodedReg) | 819 BakerReadBarrierWidthField::Encode(width); 820 } 821 EncodeBakerReadBarrierUnsafeCasData(uint32_t root_reg)822 static uint32_t EncodeBakerReadBarrierUnsafeCasData(uint32_t root_reg) { 823 CheckValidReg(root_reg); 824 return BakerReadBarrierKindField::Encode(BakerReadBarrierKind::kUnsafeCas) | 825 BakerReadBarrierFirstRegField::Encode(root_reg) | 826 BakerReadBarrierSecondRegField::Encode(kBakerReadBarrierInvalidEncodedReg) | 827 BakerReadBarrierWidthField::Encode(BakerReadBarrierWidth::kWide); 828 } 829 830 void CompileBakerReadBarrierThunk(ArmVIXLAssembler& assembler, 831 uint32_t encoded_data, 832 /*out*/ std::string* debug_name); 833 834 vixl::aarch32::Register GetInvokeStaticOrDirectExtraParameter(HInvokeStaticOrDirect* invoke, 835 vixl::aarch32::Register temp); 836 837 using Uint32ToLiteralMap = ArenaSafeMap<uint32_t, VIXLUInt32Literal*>; 838 using StringToLiteralMap = ArenaSafeMap<StringReference, 839 VIXLUInt32Literal*, 840 StringReferenceValueComparator>; 841 using TypeToLiteralMap = ArenaSafeMap<TypeReference, 842 VIXLUInt32Literal*, 843 TypeReferenceValueComparator>; 844 845 struct BakerReadBarrierPatchInfo { BakerReadBarrierPatchInfoBakerReadBarrierPatchInfo846 explicit BakerReadBarrierPatchInfo(uint32_t data) : label(), custom_data(data) { } 847 848 vixl::aarch32::Label label; 849 uint32_t custom_data; 850 }; 851 852 VIXLUInt32Literal* DeduplicateUint32Literal(uint32_t value, Uint32ToLiteralMap* map); 853 PcRelativePatchInfo* NewPcRelativePatch(const DexFile* dex_file, 854 uint32_t offset_or_index, 855 ArenaDeque<PcRelativePatchInfo>* patches); 856 template <linker::LinkerPatch (*Factory)(size_t, const DexFile*, uint32_t, uint32_t)> 857 static void EmitPcRelativeLinkerPatches(const ArenaDeque<PcRelativePatchInfo>& infos, 858 ArenaVector<linker::LinkerPatch>* linker_patches); 859 860 // Labels for each block that will be compiled. 861 // We use a deque so that the `vixl::aarch32::Label` objects do not move in memory. 862 ArenaDeque<vixl::aarch32::Label> block_labels_; // Indexed by block id. 863 vixl::aarch32::Label frame_entry_label_; 864 865 ArenaVector<std::unique_ptr<JumpTableARMVIXL>> jump_tables_; 866 LocationsBuilderARMVIXL location_builder_; 867 InstructionCodeGeneratorARMVIXL instruction_visitor_; 868 ParallelMoveResolverARMVIXL move_resolver_; 869 870 ArmVIXLAssembler assembler_; 871 872 // Deduplication map for 32-bit literals, used for non-patchable boot image addresses. 873 Uint32ToLiteralMap uint32_literals_; 874 // PC-relative method patch info for kBootImageLinkTimePcRelative/kBootImageRelRo. 875 // Also used for type/string patches for kBootImageRelRo (same linker patch as for methods). 876 ArenaDeque<PcRelativePatchInfo> boot_image_method_patches_; 877 // PC-relative method patch info for kBssEntry. 878 ArenaDeque<PcRelativePatchInfo> method_bss_entry_patches_; 879 // PC-relative type patch info for kBootImageLinkTimePcRelative. 880 ArenaDeque<PcRelativePatchInfo> boot_image_type_patches_; 881 // PC-relative type patch info for kBssEntry. 882 ArenaDeque<PcRelativePatchInfo> type_bss_entry_patches_; 883 // PC-relative String patch info for kBootImageLinkTimePcRelative. 884 ArenaDeque<PcRelativePatchInfo> boot_image_string_patches_; 885 // PC-relative String patch info for kBssEntry. 886 ArenaDeque<PcRelativePatchInfo> string_bss_entry_patches_; 887 // PC-relative patch info for IntrinsicObjects. 888 ArenaDeque<PcRelativePatchInfo> boot_image_intrinsic_patches_; 889 // Baker read barrier patch info. 890 ArenaDeque<BakerReadBarrierPatchInfo> baker_read_barrier_patches_; 891 892 // Patches for string literals in JIT compiled code. 893 StringToLiteralMap jit_string_patches_; 894 // Patches for class literals in JIT compiled code. 895 TypeToLiteralMap jit_class_patches_; 896 897 // Baker read barrier slow paths, mapping custom data (uint32_t) to label. 898 // Wrap the label to work around vixl::aarch32::Label being non-copyable 899 // and non-moveable and as such unusable in ArenaSafeMap<>. 900 struct LabelWrapper { LabelWrapperLabelWrapper901 LabelWrapper(const LabelWrapper& src) 902 : label() { 903 DCHECK(!src.label.IsReferenced() && !src.label.IsBound()); 904 } 905 LabelWrapper() = default; 906 vixl::aarch32::Label label; 907 }; 908 ArenaSafeMap<uint32_t, LabelWrapper> jit_baker_read_barrier_slow_paths_; 909 910 friend class linker::Thumb2RelativePatcherTest; 911 DISALLOW_COPY_AND_ASSIGN(CodeGeneratorARMVIXL); 912 }; 913 914 } // namespace arm 915 } // namespace art 916 917 #endif // ART_COMPILER_OPTIMIZING_CODE_GENERATOR_ARM_VIXL_H_ 918