1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <stdio.h>
25 #include <inttypes.h>
26
27 #include "CUnit/Basic.h"
28
29 #include "util_math.h"
30
31 #include "amdgpu_test.h"
32 #include "amdgpu_drm.h"
33 #include "amdgpu_internal.h"
34
35 #include "vce_ib.h"
36 #include "frame.h"
37
38 #define IB_SIZE 4096
39 #define MAX_RESOURCES 16
40
41 struct amdgpu_vce_bo {
42 amdgpu_bo_handle handle;
43 amdgpu_va_handle va_handle;
44 uint64_t addr;
45 uint64_t size;
46 uint8_t *ptr;
47 };
48
49 struct amdgpu_vce_encode {
50 unsigned width;
51 unsigned height;
52 struct amdgpu_vce_bo vbuf;
53 struct amdgpu_vce_bo bs[2];
54 struct amdgpu_vce_bo fb[2];
55 struct amdgpu_vce_bo cpb;
56 unsigned ib_len;
57 bool two_instance;
58 };
59
60 static amdgpu_device_handle device_handle;
61 static uint32_t major_version;
62 static uint32_t minor_version;
63 static uint32_t family_id;
64 static uint32_t vce_harvest_config;
65
66 static amdgpu_context_handle context_handle;
67 static amdgpu_bo_handle ib_handle;
68 static amdgpu_va_handle ib_va_handle;
69 static uint64_t ib_mc_address;
70 static uint32_t *ib_cpu;
71
72 static struct amdgpu_vce_encode enc;
73 static amdgpu_bo_handle resources[MAX_RESOURCES];
74 static unsigned num_resources;
75
76 static void amdgpu_cs_vce_create(void);
77 static void amdgpu_cs_vce_encode(void);
78 static void amdgpu_cs_vce_destroy(void);
79
80 CU_TestInfo vce_tests[] = {
81 { "VCE create", amdgpu_cs_vce_create },
82 { "VCE encode", amdgpu_cs_vce_encode },
83 { "VCE destroy", amdgpu_cs_vce_destroy },
84 CU_TEST_INFO_NULL,
85 };
86
87
suite_vce_tests_enable(void)88 CU_BOOL suite_vce_tests_enable(void)
89 {
90 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
91 &minor_version, &device_handle))
92 return CU_FALSE;
93
94 family_id = device_handle->info.family_id;
95
96 if (amdgpu_device_deinitialize(device_handle))
97 return CU_FALSE;
98
99
100 if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) {
101 printf("\n\nThe ASIC NOT support VCE, suite disabled\n");
102 return CU_FALSE;
103 }
104
105 return CU_TRUE;
106 }
107
suite_vce_tests_init(void)108 int suite_vce_tests_init(void)
109 {
110 int r;
111
112 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
113 &minor_version, &device_handle);
114 if (r) {
115 if ((r == -EACCES) && (errno == EACCES))
116 printf("\n\nError:%s. "
117 "Hint:Try to run this test program as root.",
118 strerror(errno));
119
120 return CUE_SINIT_FAILED;
121 }
122
123 family_id = device_handle->info.family_id;
124 vce_harvest_config = device_handle->info.vce_harvest_config;
125
126 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
127 if (r)
128 return CUE_SINIT_FAILED;
129
130 r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
131 AMDGPU_GEM_DOMAIN_GTT, 0,
132 &ib_handle, (void**)&ib_cpu,
133 &ib_mc_address, &ib_va_handle);
134 if (r)
135 return CUE_SINIT_FAILED;
136
137 memset(&enc, 0, sizeof(struct amdgpu_vce_encode));
138
139 return CUE_SUCCESS;
140 }
141
suite_vce_tests_clean(void)142 int suite_vce_tests_clean(void)
143 {
144 int r;
145
146 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
147 ib_mc_address, IB_SIZE);
148 if (r)
149 return CUE_SCLEAN_FAILED;
150
151 r = amdgpu_cs_ctx_free(context_handle);
152 if (r)
153 return CUE_SCLEAN_FAILED;
154
155 r = amdgpu_device_deinitialize(device_handle);
156 if (r)
157 return CUE_SCLEAN_FAILED;
158
159 return CUE_SUCCESS;
160 }
161
submit(unsigned ndw,unsigned ip)162 static int submit(unsigned ndw, unsigned ip)
163 {
164 struct amdgpu_cs_request ibs_request = {0};
165 struct amdgpu_cs_ib_info ib_info = {0};
166 struct amdgpu_cs_fence fence_status = {0};
167 uint32_t expired;
168 int r;
169
170 ib_info.ib_mc_address = ib_mc_address;
171 ib_info.size = ndw;
172
173 ibs_request.ip_type = ip;
174
175 r = amdgpu_bo_list_create(device_handle, num_resources, resources,
176 NULL, &ibs_request.resources);
177 if (r)
178 return r;
179
180 ibs_request.number_of_ibs = 1;
181 ibs_request.ibs = &ib_info;
182 ibs_request.fence_info.handle = NULL;
183
184 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
185 if (r)
186 return r;
187
188 r = amdgpu_bo_list_destroy(ibs_request.resources);
189 if (r)
190 return r;
191
192 fence_status.context = context_handle;
193 fence_status.ip_type = ip;
194 fence_status.fence = ibs_request.seq_no;
195
196 r = amdgpu_cs_query_fence_status(&fence_status,
197 AMDGPU_TIMEOUT_INFINITE,
198 0, &expired);
199 if (r)
200 return r;
201
202 return 0;
203 }
204
alloc_resource(struct amdgpu_vce_bo * vce_bo,unsigned size,unsigned domain)205 static void alloc_resource(struct amdgpu_vce_bo *vce_bo, unsigned size, unsigned domain)
206 {
207 struct amdgpu_bo_alloc_request req = {0};
208 amdgpu_bo_handle buf_handle;
209 amdgpu_va_handle va_handle;
210 uint64_t va = 0;
211 int r;
212
213 req.alloc_size = ALIGN(size, 4096);
214 req.preferred_heap = domain;
215 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
216 CU_ASSERT_EQUAL(r, 0);
217 r = amdgpu_va_range_alloc(device_handle,
218 amdgpu_gpu_va_range_general,
219 req.alloc_size, 1, 0, &va,
220 &va_handle, 0);
221 CU_ASSERT_EQUAL(r, 0);
222 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
223 AMDGPU_VA_OP_MAP);
224 CU_ASSERT_EQUAL(r, 0);
225 vce_bo->addr = va;
226 vce_bo->handle = buf_handle;
227 vce_bo->size = req.alloc_size;
228 vce_bo->va_handle = va_handle;
229 r = amdgpu_bo_cpu_map(vce_bo->handle, (void **)&vce_bo->ptr);
230 CU_ASSERT_EQUAL(r, 0);
231 memset(vce_bo->ptr, 0, size);
232 r = amdgpu_bo_cpu_unmap(vce_bo->handle);
233 CU_ASSERT_EQUAL(r, 0);
234 }
235
free_resource(struct amdgpu_vce_bo * vce_bo)236 static void free_resource(struct amdgpu_vce_bo *vce_bo)
237 {
238 int r;
239
240 r = amdgpu_bo_va_op(vce_bo->handle, 0, vce_bo->size,
241 vce_bo->addr, 0, AMDGPU_VA_OP_UNMAP);
242 CU_ASSERT_EQUAL(r, 0);
243
244 r = amdgpu_va_range_free(vce_bo->va_handle);
245 CU_ASSERT_EQUAL(r, 0);
246
247 r = amdgpu_bo_free(vce_bo->handle);
248 CU_ASSERT_EQUAL(r, 0);
249 memset(vce_bo, 0, sizeof(*vce_bo));
250 }
251
amdgpu_cs_vce_create(void)252 static void amdgpu_cs_vce_create(void)
253 {
254 unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
255 int len, r;
256
257 enc.width = vce_create[6];
258 enc.height = vce_create[7];
259
260 num_resources = 0;
261 alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
262 resources[num_resources++] = enc.fb[0].handle;
263 resources[num_resources++] = ib_handle;
264
265 len = 0;
266 memcpy(ib_cpu, vce_session, sizeof(vce_session));
267 len += sizeof(vce_session) / 4;
268 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
269 len += sizeof(vce_taskinfo) / 4;
270 memcpy((ib_cpu + len), vce_create, sizeof(vce_create));
271 ib_cpu[len + 8] = ALIGN(enc.width, align);
272 ib_cpu[len + 9] = ALIGN(enc.width, align);
273 len += sizeof(vce_create) / 4;
274 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
275 ib_cpu[len + 2] = enc.fb[0].addr >> 32;
276 ib_cpu[len + 3] = enc.fb[0].addr;
277 len += sizeof(vce_feedback) / 4;
278
279 r = submit(len, AMDGPU_HW_IP_VCE);
280 CU_ASSERT_EQUAL(r, 0);
281
282 free_resource(&enc.fb[0]);
283 }
284
amdgpu_cs_vce_config(void)285 static void amdgpu_cs_vce_config(void)
286 {
287 int len = 0, r;
288
289 memcpy((ib_cpu + len), vce_session, sizeof(vce_session));
290 len += sizeof(vce_session) / 4;
291 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
292 ib_cpu[len + 3] = 2;
293 ib_cpu[len + 6] = 0xffffffff;
294 len += sizeof(vce_taskinfo) / 4;
295 memcpy((ib_cpu + len), vce_rate_ctrl, sizeof(vce_rate_ctrl));
296 len += sizeof(vce_rate_ctrl) / 4;
297 memcpy((ib_cpu + len), vce_config_ext, sizeof(vce_config_ext));
298 len += sizeof(vce_config_ext) / 4;
299 memcpy((ib_cpu + len), vce_motion_est, sizeof(vce_motion_est));
300 len += sizeof(vce_motion_est) / 4;
301 memcpy((ib_cpu + len), vce_rdo, sizeof(vce_rdo));
302 len += sizeof(vce_rdo) / 4;
303 memcpy((ib_cpu + len), vce_pic_ctrl, sizeof(vce_pic_ctrl));
304 len += sizeof(vce_pic_ctrl) / 4;
305
306 r = submit(len, AMDGPU_HW_IP_VCE);
307 CU_ASSERT_EQUAL(r, 0);
308 }
309
amdgpu_cs_vce_encode_idr(struct amdgpu_vce_encode * enc)310 static void amdgpu_cs_vce_encode_idr(struct amdgpu_vce_encode *enc)
311 {
312
313 uint64_t luma_offset, chroma_offset;
314 unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
315 unsigned luma_size = ALIGN(enc->width, align) * ALIGN(enc->height, 16);
316 int len = 0, i, r;
317
318 luma_offset = enc->vbuf.addr;
319 chroma_offset = luma_offset + luma_size;
320
321 memcpy((ib_cpu + len), vce_session, sizeof(vce_session));
322 len += sizeof(vce_session) / 4;
323 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
324 len += sizeof(vce_taskinfo) / 4;
325 memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer));
326 ib_cpu[len + 2] = enc->bs[0].addr >> 32;
327 ib_cpu[len + 3] = enc->bs[0].addr;
328 len += sizeof(vce_bs_buffer) / 4;
329 memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer));
330 ib_cpu[len + 2] = enc->cpb.addr >> 32;
331 ib_cpu[len + 3] = enc->cpb.addr;
332 len += sizeof(vce_context_buffer) / 4;
333 memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer));
334 for (i = 0; i < 8; ++i)
335 ib_cpu[len + 2 + i] = luma_size * 1.5 * (i + 2);
336 for (i = 0; i < 8; ++i)
337 ib_cpu[len + 10 + i] = luma_size * 1.5;
338 len += sizeof(vce_aux_buffer) / 4;
339 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
340 ib_cpu[len + 2] = enc->fb[0].addr >> 32;
341 ib_cpu[len + 3] = enc->fb[0].addr;
342 len += sizeof(vce_feedback) / 4;
343 memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode));
344 ib_cpu[len + 9] = luma_offset >> 32;
345 ib_cpu[len + 10] = luma_offset;
346 ib_cpu[len + 11] = chroma_offset >> 32;
347 ib_cpu[len + 12] = chroma_offset;
348 ib_cpu[len + 14] = ALIGN(enc->width, align);
349 ib_cpu[len + 15] = ALIGN(enc->width, align);
350 ib_cpu[len + 73] = luma_size * 1.5;
351 ib_cpu[len + 74] = luma_size * 2.5;
352 len += sizeof(vce_encode) / 4;
353 enc->ib_len = len;
354 if (!enc->two_instance) {
355 r = submit(len, AMDGPU_HW_IP_VCE);
356 CU_ASSERT_EQUAL(r, 0);
357 }
358 }
359
amdgpu_cs_vce_encode_p(struct amdgpu_vce_encode * enc)360 static void amdgpu_cs_vce_encode_p(struct amdgpu_vce_encode *enc)
361 {
362 uint64_t luma_offset, chroma_offset;
363 int len, i, r;
364 unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
365 unsigned luma_size = ALIGN(enc->width, align) * ALIGN(enc->height, 16);
366
367 len = (enc->two_instance) ? enc->ib_len : 0;
368 luma_offset = enc->vbuf.addr;
369 chroma_offset = luma_offset + luma_size;
370
371 if (!enc->two_instance) {
372 memcpy((ib_cpu + len), vce_session, sizeof(vce_session));
373 len += sizeof(vce_session) / 4;
374 }
375 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
376 len += sizeof(vce_taskinfo) / 4;
377 memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer));
378 ib_cpu[len + 2] = enc->bs[1].addr >> 32;
379 ib_cpu[len + 3] = enc->bs[1].addr;
380 len += sizeof(vce_bs_buffer) / 4;
381 memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer));
382 ib_cpu[len + 2] = enc->cpb.addr >> 32;
383 ib_cpu[len + 3] = enc->cpb.addr;
384 len += sizeof(vce_context_buffer) / 4;
385 memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer));
386 for (i = 0; i < 8; ++i)
387 ib_cpu[len + 2 + i] = luma_size * 1.5 * (i + 2);
388 for (i = 0; i < 8; ++i)
389 ib_cpu[len + 10 + i] = luma_size * 1.5;
390 len += sizeof(vce_aux_buffer) / 4;
391 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
392 ib_cpu[len + 2] = enc->fb[1].addr >> 32;
393 ib_cpu[len + 3] = enc->fb[1].addr;
394 len += sizeof(vce_feedback) / 4;
395 memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode));
396 ib_cpu[len + 2] = 0;
397 ib_cpu[len + 9] = luma_offset >> 32;
398 ib_cpu[len + 10] = luma_offset;
399 ib_cpu[len + 11] = chroma_offset >> 32;
400 ib_cpu[len + 12] = chroma_offset;
401 ib_cpu[len + 14] = ALIGN(enc->width, align);
402 ib_cpu[len + 15] = ALIGN(enc->width, align);
403 ib_cpu[len + 18] = 0;
404 ib_cpu[len + 19] = 0;
405 ib_cpu[len + 56] = 3;
406 ib_cpu[len + 57] = 0;
407 ib_cpu[len + 58] = 0;
408 ib_cpu[len + 59] = luma_size * 1.5;
409 ib_cpu[len + 60] = luma_size * 2.5;
410 ib_cpu[len + 73] = 0;
411 ib_cpu[len + 74] = luma_size;
412 ib_cpu[len + 81] = 1;
413 ib_cpu[len + 82] = 1;
414 len += sizeof(vce_encode) / 4;
415
416 r = submit(len, AMDGPU_HW_IP_VCE);
417 CU_ASSERT_EQUAL(r, 0);
418 }
419
check_result(struct amdgpu_vce_encode * enc)420 static void check_result(struct amdgpu_vce_encode *enc)
421 {
422 uint64_t sum;
423 uint32_t s[2] = {180325, 15946};
424 uint32_t *ptr, size;
425 int i, j, r;
426
427 for (i = 0; i < 2; ++i) {
428 r = amdgpu_bo_cpu_map(enc->fb[i].handle, (void **)&enc->fb[i].ptr);
429 CU_ASSERT_EQUAL(r, 0);
430 ptr = (uint32_t *)enc->fb[i].ptr;
431 size = ptr[4] - ptr[9];
432 r = amdgpu_bo_cpu_unmap(enc->fb[i].handle);
433 CU_ASSERT_EQUAL(r, 0);
434 r = amdgpu_bo_cpu_map(enc->bs[i].handle, (void **)&enc->bs[i].ptr);
435 CU_ASSERT_EQUAL(r, 0);
436 for (j = 0, sum = 0; j < size; ++j)
437 sum += enc->bs[i].ptr[j];
438 CU_ASSERT_EQUAL(sum, s[i]);
439 r = amdgpu_bo_cpu_unmap(enc->bs[i].handle);
440 CU_ASSERT_EQUAL(r, 0);
441 }
442 }
443
amdgpu_cs_vce_encode(void)444 static void amdgpu_cs_vce_encode(void)
445 {
446 uint32_t vbuf_size, bs_size = 0x154000, cpb_size;
447 unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
448 int i, r;
449
450 vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5;
451 cpb_size = vbuf_size * 10;
452 num_resources = 0;
453 alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
454 resources[num_resources++] = enc.fb[0].handle;
455 alloc_resource(&enc.fb[1], 4096, AMDGPU_GEM_DOMAIN_GTT);
456 resources[num_resources++] = enc.fb[1].handle;
457 alloc_resource(&enc.bs[0], bs_size, AMDGPU_GEM_DOMAIN_GTT);
458 resources[num_resources++] = enc.bs[0].handle;
459 alloc_resource(&enc.bs[1], bs_size, AMDGPU_GEM_DOMAIN_GTT);
460 resources[num_resources++] = enc.bs[1].handle;
461 alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM);
462 resources[num_resources++] = enc.vbuf.handle;
463 alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM);
464 resources[num_resources++] = enc.cpb.handle;
465 resources[num_resources++] = ib_handle;
466
467 r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr);
468 CU_ASSERT_EQUAL(r, 0);
469
470 memset(enc.vbuf.ptr, 0, vbuf_size);
471 for (i = 0; i < enc.height; ++i) {
472 memcpy(enc.vbuf.ptr, (frame + i * enc.width), enc.width);
473 enc.vbuf.ptr += ALIGN(enc.width, align);
474 }
475 for (i = 0; i < enc.height / 2; ++i) {
476 memcpy(enc.vbuf.ptr, ((frame + enc.height * enc.width) + i * enc.width), enc.width);
477 enc.vbuf.ptr += ALIGN(enc.width, align);
478 }
479
480 r = amdgpu_bo_cpu_unmap(enc.vbuf.handle);
481 CU_ASSERT_EQUAL(r, 0);
482
483 amdgpu_cs_vce_config();
484
485 if (family_id >= AMDGPU_FAMILY_VI) {
486 vce_taskinfo[3] = 3;
487 amdgpu_cs_vce_encode_idr(&enc);
488 amdgpu_cs_vce_encode_p(&enc);
489 check_result(&enc);
490
491 /* two pipes */
492 vce_encode[16] = 0;
493 amdgpu_cs_vce_encode_idr(&enc);
494 amdgpu_cs_vce_encode_p(&enc);
495 check_result(&enc);
496
497 /* two instances */
498 if (vce_harvest_config == 0) {
499 enc.two_instance = true;
500 vce_taskinfo[2] = 0x83;
501 vce_taskinfo[4] = 1;
502 amdgpu_cs_vce_encode_idr(&enc);
503 vce_taskinfo[2] = 0xffffffff;
504 vce_taskinfo[4] = 2;
505 amdgpu_cs_vce_encode_p(&enc);
506 check_result(&enc);
507 }
508 } else {
509 vce_taskinfo[3] = 3;
510 vce_encode[16] = 0;
511 amdgpu_cs_vce_encode_idr(&enc);
512 amdgpu_cs_vce_encode_p(&enc);
513 check_result(&enc);
514 }
515
516 free_resource(&enc.fb[0]);
517 free_resource(&enc.fb[1]);
518 free_resource(&enc.bs[0]);
519 free_resource(&enc.bs[1]);
520 free_resource(&enc.vbuf);
521 free_resource(&enc.cpb);
522 }
523
amdgpu_cs_vce_destroy(void)524 static void amdgpu_cs_vce_destroy(void)
525 {
526 int len, r;
527
528 num_resources = 0;
529 alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
530 resources[num_resources++] = enc.fb[0].handle;
531 resources[num_resources++] = ib_handle;
532
533 len = 0;
534 memcpy(ib_cpu, vce_session, sizeof(vce_session));
535 len += sizeof(vce_session) / 4;
536 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
537 ib_cpu[len + 3] = 1;
538 len += sizeof(vce_taskinfo) / 4;
539 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
540 ib_cpu[len + 2] = enc.fb[0].addr >> 32;
541 ib_cpu[len + 3] = enc.fb[0].addr;
542 len += sizeof(vce_feedback) / 4;
543 memcpy((ib_cpu + len), vce_destroy, sizeof(vce_destroy));
544 len += sizeof(vce_destroy) / 4;
545
546 r = submit(len, AMDGPU_HW_IP_VCE);
547 CU_ASSERT_EQUAL(r, 0);
548
549 free_resource(&enc.fb[0]);
550 }
551