1//==- AArch64SchedA53.td - Cortex-A53 Scheduling Definitions -*- tablegen -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the ARM Cortex A53 processors.
11//
12//===----------------------------------------------------------------------===//
13
14// ===---------------------------------------------------------------------===//
15// The following definitions describe the simpler per-operand machine model.
16// This works with MachineScheduler. See MCSchedModel.h for details.
17
18// Cortex-A53 machine model for scheduling and other instruction cost heuristics.
19def CortexA53Model : SchedMachineModel {
20  let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order.
21  let IssueWidth = 2;        // 2 micro-ops are dispatched per cycle.
22  let LoadLatency = 3;       // Optimistic load latency assuming bypass.
23                             // This is overriden by OperandCycles if the
24                             // Itineraries are queried instead.
25  let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
26                             // Specification - Instruction Timings"
27                             // v 1.0 Spreadsheet
28  let CompleteModel = 1;
29}
30
31
32//===----------------------------------------------------------------------===//
33// Define each kind of processor resource and number available.
34
35// Modeling each pipeline as a ProcResource using the BufferSize = 0 since
36// Cortex-A53 is in-order.
37
38def A53UnitALU    : ProcResource<2> { let BufferSize = 0; } // Int ALU
39def A53UnitMAC    : ProcResource<1> { let BufferSize = 0; } // Int MAC
40def A53UnitDiv    : ProcResource<1> { let BufferSize = 0; } // Int Division
41def A53UnitLdSt   : ProcResource<1> { let BufferSize = 0; } // Load/Store
42def A53UnitB      : ProcResource<1> { let BufferSize = 0; } // Branch
43def A53UnitFPALU  : ProcResource<1> { let BufferSize = 0; } // FP ALU
44def A53UnitFPMDS  : ProcResource<1> { let BufferSize = 0; } // FP Mult/Div/Sqrt
45
46
47//===----------------------------------------------------------------------===//
48// Subtarget-specific SchedWrite types which both map the ProcResources and
49// set the latency.
50
51let SchedModel = CortexA53Model in {
52
53// ALU - Despite having a full latency of 4, most of the ALU instructions can
54//       forward a cycle earlier and then two cycles earlier in the case of a
55//       shift-only instruction. These latencies will be incorrect when the
56//       result cannot be forwarded, but modeling isn't rocket surgery.
57def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; }
58def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
59def : WriteRes<WriteISReg, [A53UnitALU]> { let Latency = 3; }
60def : WriteRes<WriteIEReg, [A53UnitALU]> { let Latency = 3; }
61def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; }
62def : WriteRes<WriteExtr, [A53UnitALU]> { let Latency = 3; }
63
64// MAC
65def : WriteRes<WriteIM32, [A53UnitMAC]> { let Latency = 4; }
66def : WriteRes<WriteIM64, [A53UnitMAC]> { let Latency = 4; }
67
68// Div
69def : WriteRes<WriteID32, [A53UnitDiv]> { let Latency = 4; }
70def : WriteRes<WriteID64, [A53UnitDiv]> { let Latency = 4; }
71
72// Load
73def : WriteRes<WriteLD, [A53UnitLdSt]> { let Latency = 4; }
74def : WriteRes<WriteLDIdx, [A53UnitLdSt]> { let Latency = 4; }
75def : WriteRes<WriteLDHi, [A53UnitLdSt]> { let Latency = 4; }
76
77// Vector Load - Vector loads take 1-5 cycles to issue. For the WriteVecLd
78//               below, choosing the median of 3 which makes the latency 6.
79//               May model this more carefully in the future. The remaining
80//               A53WriteVLD# types represent the 1-5 cycle issues explicitly.
81def : WriteRes<WriteVLD, [A53UnitLdSt]> { let Latency = 6;
82                                          let ResourceCycles = [3]; }
83def A53WriteVLD1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; }
84def A53WriteVLD2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5;
85                                                  let ResourceCycles = [2]; }
86def A53WriteVLD3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6;
87                                                  let ResourceCycles = [3]; }
88def A53WriteVLD4 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 7;
89                                                  let ResourceCycles = [4]; }
90def A53WriteVLD5 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 8;
91                                                  let ResourceCycles = [5]; }
92
93// Pre/Post Indexing - Performed as part of address generation which is already
94//                     accounted for in the WriteST* latencies below
95def : WriteRes<WriteAdr, []> { let Latency = 0; }
96
97// Store
98def : WriteRes<WriteST, [A53UnitLdSt]> { let Latency = 4; }
99def : WriteRes<WriteSTP, [A53UnitLdSt]> { let Latency = 4; }
100def : WriteRes<WriteSTIdx, [A53UnitLdSt]> { let Latency = 4; }
101def : WriteRes<WriteSTX, [A53UnitLdSt]> { let Latency = 4; }
102
103// Vector Store - Similar to vector loads, can take 1-3 cycles to issue.
104def : WriteRes<WriteVST, [A53UnitLdSt]> { let Latency = 5;
105                                          let ResourceCycles = [2];}
106def A53WriteVST1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; }
107def A53WriteVST2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5;
108                                                  let ResourceCycles = [2]; }
109def A53WriteVST3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6;
110                                                  let ResourceCycles = [3]; }
111
112def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
113
114// Branch
115def : WriteRes<WriteBr, [A53UnitB]>;
116def : WriteRes<WriteBrReg, [A53UnitB]>;
117def : WriteRes<WriteSys, [A53UnitB]>;
118def : WriteRes<WriteBarrier, [A53UnitB]>;
119def : WriteRes<WriteHint, [A53UnitB]>;
120
121// FP ALU
122def : WriteRes<WriteF, [A53UnitFPALU]> { let Latency = 6; }
123def : WriteRes<WriteFCmp, [A53UnitFPALU]> { let Latency = 6; }
124def : WriteRes<WriteFCvt, [A53UnitFPALU]> { let Latency = 6; }
125def : WriteRes<WriteFCopy, [A53UnitFPALU]> { let Latency = 6; }
126def : WriteRes<WriteFImm, [A53UnitFPALU]> { let Latency = 6; }
127def : WriteRes<WriteV, [A53UnitFPALU]> { let Latency = 6; }
128
129// FP Mul, Div, Sqrt
130def : WriteRes<WriteFMul, [A53UnitFPMDS]> { let Latency = 6; }
131def : WriteRes<WriteFDiv, [A53UnitFPMDS]> { let Latency = 33;
132                                            let ResourceCycles = [29]; }
133def A53WriteFMAC : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 10; }
134def A53WriteFDivSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 18;
135                                                     let ResourceCycles = [14]; }
136def A53WriteFDivDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 33;
137                                                     let ResourceCycles = [29]; }
138def A53WriteFSqrtSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 17;
139                                                      let ResourceCycles = [13]; }
140def A53WriteFSqrtDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 32;
141                                                      let ResourceCycles = [28]; }
142
143//===----------------------------------------------------------------------===//
144// Subtarget-specific SchedRead types.
145
146// No forwarding for these reads.
147def : ReadAdvance<ReadExtrHi, 0>;
148def : ReadAdvance<ReadAdrBase, 0>;
149def : ReadAdvance<ReadVLD, 0>;
150
151// ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
152//       operands are needed one cycle later if and only if they are to be
153//       shifted. Otherwise, they too are needed two cycles later. This same
154//       ReadAdvance applies to Extended registers as well, even though there is
155//       a separate SchedPredicate for them.
156def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
157                             WriteISReg, WriteIEReg,WriteIS,
158                             WriteID32,WriteID64,
159                             WriteIM32,WriteIM64]>;
160def A53ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI,
161                                          WriteISReg, WriteIEReg,WriteIS,
162                                          WriteID32,WriteID64,
163                                          WriteIM32,WriteIM64]>;
164def A53ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI,
165                                             WriteISReg, WriteIEReg,WriteIS,
166                                             WriteID32,WriteID64,
167                                             WriteIM32,WriteIM64]>;
168def A53ReadISReg : SchedReadVariant<[
169	SchedVar<RegShiftedPred, [A53ReadShifted]>,
170	SchedVar<NoSchedPred, [A53ReadNotShifted]>]>;
171def : SchedAlias<ReadISReg, A53ReadISReg>;
172
173def A53ReadIEReg : SchedReadVariant<[
174	SchedVar<RegExtendedPred, [A53ReadShifted]>,
175	SchedVar<NoSchedPred, [A53ReadNotShifted]>]>;
176def : SchedAlias<ReadIEReg, A53ReadIEReg>;
177
178// MAC - Operands are generally needed one cycle later in the MAC pipe.
179//       Accumulator operands are needed two cycles later.
180def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
181                              WriteISReg, WriteIEReg,WriteIS,
182                              WriteID32,WriteID64,
183                              WriteIM32,WriteIM64]>;
184def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
185                               WriteISReg, WriteIEReg,WriteIS,
186                               WriteID32,WriteID64,
187                               WriteIM32,WriteIM64]>;
188
189// Div
190def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
191                              WriteISReg, WriteIEReg,WriteIS,
192                              WriteID32,WriteID64,
193                              WriteIM32,WriteIM64]>;
194
195//===----------------------------------------------------------------------===//
196// Subtarget-specific InstRWs.
197
198//---
199// Miscellaneous
200//---
201def : InstRW<[WriteI], (instrs COPY)>;
202
203//---
204// Vector Loads
205//---
206def : InstRW<[A53WriteVLD1], (instregex "LD1i(8|16|32|64)$")>;
207def : InstRW<[A53WriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
208def : InstRW<[A53WriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
209def : InstRW<[A53WriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
210def : InstRW<[A53WriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
211def : InstRW<[A53WriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
212def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>;
213def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
214def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
215def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
216def : InstRW<[A53WriteVLD3, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
217def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
218
219def : InstRW<[A53WriteVLD1], (instregex "LD2i(8|16|32|64)$")>;
220def : InstRW<[A53WriteVLD1], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
221def : InstRW<[A53WriteVLD2], (instregex "LD2Twov(8b|4h|2s)$")>;
222def : InstRW<[A53WriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
223def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD2i(8|16|32|64)(_POST)?$")>;
224def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
225def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD2Twov(8b|4h|2s)(_POST)?$")>;
226def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)(_POST)?$")>;
227
228def : InstRW<[A53WriteVLD2], (instregex "LD3i(8|16|32|64)$")>;
229def : InstRW<[A53WriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
230def : InstRW<[A53WriteVLD4], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
231def : InstRW<[A53WriteVLD3], (instregex "LD3Threev(2d)$")>;
232def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>;
233def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
234def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
235def : InstRW<[A53WriteVLD3, WriteAdr], (instregex "LD3Threev(2d)_POST$")>;
236
237def : InstRW<[A53WriteVLD2], (instregex "LD4i(8|16|32|64)$")>;
238def : InstRW<[A53WriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
239def : InstRW<[A53WriteVLD5], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
240def : InstRW<[A53WriteVLD4], (instregex "LD4Fourv(2d)$")>;
241def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>;
242def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
243def : InstRW<[A53WriteVLD5, WriteAdr], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
244def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>;
245
246//---
247// Vector Stores
248//---
249def : InstRW<[A53WriteVST1], (instregex "ST1i(8|16|32|64)$")>;
250def : InstRW<[A53WriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
251def : InstRW<[A53WriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
252def : InstRW<[A53WriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
253def : InstRW<[A53WriteVST2], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
254def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>;
255def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
256def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
257def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
258def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
259
260def : InstRW<[A53WriteVST1], (instregex "ST2i(8|16|32|64)$")>;
261def : InstRW<[A53WriteVST1], (instregex "ST2Twov(8b|4h|2s)$")>;
262def : InstRW<[A53WriteVST2], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
263def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>;
264def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
265def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
266
267def : InstRW<[A53WriteVST2], (instregex "ST3i(8|16|32|64)$")>;
268def : InstRW<[A53WriteVST3], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
269def : InstRW<[A53WriteVST2], (instregex "ST3Threev(2d)$")>;
270def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>;
271def : InstRW<[A53WriteVST3, WriteAdr], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
272def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST3Threev(2d)_POST$")>;
273
274def : InstRW<[A53WriteVST2], (instregex "ST4i(8|16|32|64)$")>;
275def : InstRW<[A53WriteVST3], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
276def : InstRW<[A53WriteVST2], (instregex "ST4Fourv(2d)$")>;
277def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST4i(8|16|32|64)_POST$")>;
278def : InstRW<[A53WriteVST3, WriteAdr], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
279def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>;
280
281//---
282// Floating Point MAC, DIV, SQRT
283//---
284def : InstRW<[A53WriteFMAC], (instregex "^FN?M(ADD|SUB).*")>;
285def : InstRW<[A53WriteFMAC], (instregex "^FML(A|S).*")>;
286def : InstRW<[A53WriteFDivSP], (instrs FDIVSrr)>;
287def : InstRW<[A53WriteFDivDP], (instrs FDIVDrr)>;
288def : InstRW<[A53WriteFDivSP], (instregex "^FDIVv.*32$")>;
289def : InstRW<[A53WriteFDivDP], (instregex "^FDIVv.*64$")>;
290def : InstRW<[A53WriteFSqrtSP], (instregex "^.*SQRT.*32$")>;
291def : InstRW<[A53WriteFSqrtDP], (instregex "^.*SQRT.*64$")>;
292
293}
294