1//===-- SIIntrinsics.td - SI Intrinsic defs ----------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// SI Intrinsic Definitions
11//
12//===----------------------------------------------------------------------===//
13
14
15let TargetPrefix = "SI", isTarget = 1 in {
16  def int_SI_packf16 : Intrinsic <[llvm_i32_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
17  def int_SI_export : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty], []>;
18  def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
19  def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_anyint_ty, llvm_i16_ty, llvm_i32_ty], [IntrNoMem]> ;
20
21  // Fully-flexible TBUFFER_STORE_FORMAT_* except for the ADDR64 bit, which is not exposed
22  def int_SI_tbuffer_store : Intrinsic <
23    [],
24    [llvm_anyint_ty, // rsrc(SGPR)
25     llvm_anyint_ty, // vdata(VGPR), overloaded for types i32, v2i32, v4i32
26     llvm_i32_ty,    // num_channels(imm), selects opcode suffix: 1=X, 2=XY, 3=XYZ, 4=XYZW
27     llvm_i32_ty,    // vaddr(VGPR)
28     llvm_i32_ty,    // soffset(SGPR)
29     llvm_i32_ty,    // inst_offset(imm)
30     llvm_i32_ty,    // dfmt(imm)
31     llvm_i32_ty,    // nfmt(imm)
32     llvm_i32_ty,    // offen(imm)
33     llvm_i32_ty,    // idxen(imm)
34     llvm_i32_ty,    // glc(imm)
35     llvm_i32_ty,    // slc(imm)
36     llvm_i32_ty],   // tfe(imm)
37    []>;
38
39  // Fully-flexible BUFFER_LOAD_DWORD_* except for the ADDR64 bit, which is not exposed
40  def int_SI_buffer_load_dword : Intrinsic <
41    [llvm_anyint_ty], // vdata(VGPR), overloaded for types i32, v2i32, v4i32
42    [llvm_anyint_ty,  // rsrc(SGPR)
43     llvm_anyint_ty,  // vaddr(VGPR)
44     llvm_i32_ty,     // soffset(SGPR)
45     llvm_i32_ty,     // inst_offset(imm)
46     llvm_i32_ty,     // offen(imm)
47     llvm_i32_ty,     // idxen(imm)
48     llvm_i32_ty,     // glc(imm)
49     llvm_i32_ty,     // slc(imm)
50     llvm_i32_ty],    // tfe(imm)
51    [IntrReadMem, IntrArgMemOnly]>;
52
53  def int_SI_sendmsg : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], []>;
54
55  // Fully-flexible SAMPLE instruction.
56  class SampleRaw : Intrinsic <
57    [llvm_v4f32_ty],    // vdata(VGPR)
58    [llvm_anyint_ty,    // vaddr(VGPR)
59     llvm_v8i32_ty,     // rsrc(SGPR)
60     llvm_v4i32_ty,     // sampler(SGPR)
61     llvm_i32_ty,       // dmask(imm)
62     llvm_i32_ty,       // unorm(imm)
63     llvm_i32_ty,       // r128(imm)
64     llvm_i32_ty,       // da(imm)
65     llvm_i32_ty,       // glc(imm)
66     llvm_i32_ty,       // slc(imm)
67     llvm_i32_ty,       // tfe(imm)
68     llvm_i32_ty],      // lwe(imm)
69    [IntrNoMem]>;
70
71  // Image instruction without a sampler.
72  class Image : Intrinsic <
73    [llvm_v4f32_ty],    // vdata(VGPR)
74    [llvm_anyint_ty,    // vaddr(VGPR)
75     llvm_v8i32_ty,     // rsrc(SGPR)
76     llvm_i32_ty,       // dmask(imm)
77     llvm_i32_ty,       // unorm(imm)
78     llvm_i32_ty,       // r128(imm)
79     llvm_i32_ty,       // da(imm)
80     llvm_i32_ty,       // glc(imm)
81     llvm_i32_ty,       // slc(imm)
82     llvm_i32_ty,       // tfe(imm)
83     llvm_i32_ty],      // lwe(imm)
84    [IntrNoMem]>;
85
86  // Basic sample
87  def int_SI_image_sample : SampleRaw;
88  def int_SI_image_sample_cl : SampleRaw;
89  def int_SI_image_sample_d : SampleRaw;
90  def int_SI_image_sample_d_cl : SampleRaw;
91  def int_SI_image_sample_l : SampleRaw;
92  def int_SI_image_sample_b : SampleRaw;
93  def int_SI_image_sample_b_cl : SampleRaw;
94  def int_SI_image_sample_lz : SampleRaw;
95  def int_SI_image_sample_cd : SampleRaw;
96  def int_SI_image_sample_cd_cl : SampleRaw;
97
98  // Sample with comparison
99  def int_SI_image_sample_c : SampleRaw;
100  def int_SI_image_sample_c_cl : SampleRaw;
101  def int_SI_image_sample_c_d : SampleRaw;
102  def int_SI_image_sample_c_d_cl : SampleRaw;
103  def int_SI_image_sample_c_l : SampleRaw;
104  def int_SI_image_sample_c_b : SampleRaw;
105  def int_SI_image_sample_c_b_cl : SampleRaw;
106  def int_SI_image_sample_c_lz : SampleRaw;
107  def int_SI_image_sample_c_cd : SampleRaw;
108  def int_SI_image_sample_c_cd_cl : SampleRaw;
109
110  // Sample with offsets
111  def int_SI_image_sample_o : SampleRaw;
112  def int_SI_image_sample_cl_o : SampleRaw;
113  def int_SI_image_sample_d_o : SampleRaw;
114  def int_SI_image_sample_d_cl_o : SampleRaw;
115  def int_SI_image_sample_l_o : SampleRaw;
116  def int_SI_image_sample_b_o : SampleRaw;
117  def int_SI_image_sample_b_cl_o : SampleRaw;
118  def int_SI_image_sample_lz_o : SampleRaw;
119  def int_SI_image_sample_cd_o : SampleRaw;
120  def int_SI_image_sample_cd_cl_o : SampleRaw;
121
122  // Sample with comparison and offsets
123  def int_SI_image_sample_c_o : SampleRaw;
124  def int_SI_image_sample_c_cl_o : SampleRaw;
125  def int_SI_image_sample_c_d_o : SampleRaw;
126  def int_SI_image_sample_c_d_cl_o : SampleRaw;
127  def int_SI_image_sample_c_l_o : SampleRaw;
128  def int_SI_image_sample_c_b_o : SampleRaw;
129  def int_SI_image_sample_c_b_cl_o : SampleRaw;
130  def int_SI_image_sample_c_lz_o : SampleRaw;
131  def int_SI_image_sample_c_cd_o : SampleRaw;
132  def int_SI_image_sample_c_cd_cl_o : SampleRaw;
133
134  // Basic gather4
135  def int_SI_gather4 : SampleRaw;
136  def int_SI_gather4_cl : SampleRaw;
137  def int_SI_gather4_l : SampleRaw;
138  def int_SI_gather4_b : SampleRaw;
139  def int_SI_gather4_b_cl : SampleRaw;
140  def int_SI_gather4_lz : SampleRaw;
141
142  // Gather4 with comparison
143  def int_SI_gather4_c : SampleRaw;
144  def int_SI_gather4_c_cl : SampleRaw;
145  def int_SI_gather4_c_l : SampleRaw;
146  def int_SI_gather4_c_b : SampleRaw;
147  def int_SI_gather4_c_b_cl : SampleRaw;
148  def int_SI_gather4_c_lz : SampleRaw;
149
150  // Gather4 with offsets
151  def int_SI_gather4_o : SampleRaw;
152  def int_SI_gather4_cl_o : SampleRaw;
153  def int_SI_gather4_l_o : SampleRaw;
154  def int_SI_gather4_b_o : SampleRaw;
155  def int_SI_gather4_b_cl_o : SampleRaw;
156  def int_SI_gather4_lz_o : SampleRaw;
157
158  // Gather4 with comparison and offsets
159  def int_SI_gather4_c_o : SampleRaw;
160  def int_SI_gather4_c_cl_o : SampleRaw;
161  def int_SI_gather4_c_l_o : SampleRaw;
162  def int_SI_gather4_c_b_o : SampleRaw;
163  def int_SI_gather4_c_b_cl_o : SampleRaw;
164  def int_SI_gather4_c_lz_o : SampleRaw;
165
166  def int_SI_getlod : SampleRaw;
167
168  // Image instrinsics.
169  def int_SI_image_load : Image;
170  def int_SI_image_load_mip : Image;
171  def int_SI_getresinfo : Image;
172
173  /* Interpolation Intrinsics */
174
175  def int_SI_fs_constant : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
176  def int_SI_fs_interp : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_v2i32_ty], [IntrNoMem]>;
177} // End TargetPrefix = "SI", isTarget = 1
178
179let TargetPrefix = "amdgcn", isTarget = 1 in {
180  /* Control flow Intrinsics */
181
182  def int_amdgcn_if : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_empty_ty], []>;
183  def int_amdgcn_else : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_empty_ty], []>;
184  def int_amdgcn_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty], []>;
185  def int_amdgcn_if_break : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_i64_ty], []>;
186  def int_amdgcn_else_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], []>;
187  def int_amdgcn_loop : Intrinsic<[], [llvm_i64_ty, llvm_empty_ty], []>;
188  def int_amdgcn_end_cf : Intrinsic<[], [llvm_i64_ty], []>;
189}
190