1//=- Mips64r6InstrInfo.td - Mips64r6 Instruction Information -*- tablegen -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes Mips64r6 instructions.
11//
12//===----------------------------------------------------------------------===//
13
14// Notes about removals/changes from MIPS32r6:
15// Reencoded: dclo, dclz
16
17//===----------------------------------------------------------------------===//
18//
19// Instruction Encodings
20//
21//===----------------------------------------------------------------------===//
22
23class DALIGN_ENC  : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>;
24class DAUI_ENC    : DAUI_FM;
25class DAHI_ENC    : REGIMM_FM<OPCODE5_DAHI>;
26class DATI_ENC    : REGIMM_FM<OPCODE5_DATI>;
27class DBITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_DBITSWAP>;
28class DCLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLO>;
29class DCLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLZ>;
30class DDIV_ENC    : SPECIAL_3R_FM<0b00010, 0b011110>;
31class DDIVU_ENC   : SPECIAL_3R_FM<0b00010, 0b011111>;
32class DLSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_DLSA>;
33class DMOD_ENC    : SPECIAL_3R_FM<0b00011, 0b011110>;
34class DMODU_ENC   : SPECIAL_3R_FM<0b00011, 0b011111>;
35class DMUH_ENC    : SPECIAL_3R_FM<0b00011, 0b011100>;
36class DMUHU_ENC   : SPECIAL_3R_FM<0b00011, 0b011101>;
37class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011100>;
38class DMULU_ENC   : SPECIAL_3R_FM<0b00010, 0b011101>;
39class LDPC_ENC    : PCREL18_FM<OPCODE3_LDPC>;
40class LLD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LLD>;
41class SCD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SCD>;
42
43//===----------------------------------------------------------------------===//
44//
45// Instruction Descriptions
46//
47//===----------------------------------------------------------------------===//
48
49class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, InstrItinClass itin> {
50  dag OutOperandList = (outs GPROpnd:$rs);
51  dag InOperandList = (ins GPROpnd:$rt, simm16_relaxed:$imm);
52  string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
53  string Constraints = "$rs = $rt";
54  InstrItinClass Itinerary = itin;
55}
56
57class DALIGN_DESC  : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3, II_DALIGN>;
58class DAHI_DESC    : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd, II_DAHI>;
59class DATI_DESC    : AHI_ATI_DESC_BASE<"dati", GPR64Opnd, II_DATI>;
60class DAUI_DESC    : AUI_DESC_BASE<"daui", GPR64Opnd, II_DAUI>;
61class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd, II_DBITSWAP>;
62class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd, II_DCLO>;
63class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd, II_DCLZ>;
64class DDIV_DESC    : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, II_DDIV, sdiv>;
65class DDIVU_DESC   : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, II_DDIVU, udiv>;
66class DLSA_R6_DESC : LSA_R6_DESC_BASE<"dlsa", GPR64Opnd, uimm2_plus1, II_DLSA>;
67class DMOD_DESC    : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, II_DMOD, srem>;
68class DMODU_DESC   : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, II_DMODU, urem>;
69class DMUH_DESC    : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH, mulhs>;
70class DMUHU_DESC   : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU, mulhu>;
71class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
72class DMULU_DESC   : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMUL>;
73class LDPC_DESC    : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3, II_LDPC>;
74class LLD_R6_DESC   : LL_R6_DESC_BASE<"lld", GPR64Opnd, mem_simm16, II_LLD>;
75class SCD_R6_DESC   : SC_R6_DESC_BASE<"scd", GPR64Opnd, II_SCD>;
76class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
77class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
78
79class JIALC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
80                                             GPR64Opnd> {
81  bit isCall = 1;
82  list<Register> Defs = [RA];
83}
84
85class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR64Opnd> {
86  bit isBarrier = 1;
87  bit isTerminator = 1;
88  list<Register> Defs = [AT];
89}
90
91class LL64_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9, II_LL>;
92class SC64_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>;
93//===----------------------------------------------------------------------===//
94//
95// Instruction Definitions
96//
97//===----------------------------------------------------------------------===//
98
99let AdditionalPredicates = [NotInMicroMips] in {
100  def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
101  def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
102  def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
103  def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
104}
105def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
106let AdditionalPredicates = [NotInMicroMips] in {
107  def DCLO_R6 : R6MMR6Rel, DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
108  def DCLZ_R6 : R6MMR6Rel, DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
109  def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
110  def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
111  def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
112  def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
113}
114def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
115let AdditionalPredicates = [NotInMicroMips] in {
116  def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
117  def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
118  def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
119  def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
120  def LLD_R6 : R6MMR6Rel, LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6;
121}
122def LDPC: R6MMR6Rel, LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
123def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
124let DecoderNamespace = "Mips32r6_64r6_GP64" in {
125  def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
126  def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
127}
128let AdditionalPredicates = [NotInMicroMips],
129    DecoderNamespace = "Mips32r6_64r6_PTR64" in {
130  def LL64_R6 : LL_R6_ENC, LL64_R6_DESC, PTR_64, ISA_MIPS64R6;
131  def SC64_R6 : SC_R6_ENC, SC64_R6_DESC, PTR_64, ISA_MIPS64R6;
132}
133let isCodeGenOnly = 1 in {
134def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6;
135def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6;
136}
137//===----------------------------------------------------------------------===//
138//
139// Instruction Aliases
140//
141//===----------------------------------------------------------------------===//
142
143def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6;
144
145def : MipsInstAlias<"jrc $rs", (JIC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6;
146
147def : MipsInstAlias<"jalrc $rs", (JIALC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6;
148//===----------------------------------------------------------------------===//
149//
150// Patterns and Pseudo Instructions
151//
152//===----------------------------------------------------------------------===//
153
154// i64 selects
155def : MipsPat<(select i64:$cond, i64:$t, i64:$f),
156              (OR64 (SELNEZ64 i64:$t, i64:$cond),
157                    (SELEQZ64 i64:$f, i64:$cond))>,
158              ISA_MIPS64R6;
159def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, i64:$f),
160              (OR64 (SELEQZ64 i64:$t, i64:$cond),
161                    (SELNEZ64 i64:$f, i64:$cond))>,
162              ISA_MIPS64R6;
163def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f),
164              (OR64 (SELNEZ64 i64:$t, i64:$cond),
165                    (SELEQZ64 i64:$f, i64:$cond))>,
166              ISA_MIPS64R6;
167def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
168              (OR64 (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
169                    (SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
170              ISA_MIPS64R6;
171def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
172              (OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
173                    (SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
174              ISA_MIPS64R6;
175def : MipsPat<
176  (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
177  (OR64 (SELEQZ64 i64:$t,
178                  (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
179                                 sub_32)),
180        (SELNEZ64 i64:$f,
181                  (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
182                                 sub_32)))>,
183  ISA_MIPS64R6;
184def : MipsPat<
185  (select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
186  (OR64 (SELEQZ64 i64:$t,
187                  (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
188                                 sub_32)),
189        (SELNEZ64 i64:$f,
190                  (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
191                                 sub_32)))>,
192  ISA_MIPS64R6;
193
194def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, immz),
195              (SELNEZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
196def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, immz),
197              (SELEQZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
198def : MipsPat<(select (i32 (setne i64:$cond, immz)), immz, i64:$f),
199              (SELEQZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
200def : MipsPat<(select (i32 (seteq i64:$cond, immz)), immz, i64:$f),
201              (SELNEZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
202
203// i64 selects from an i32 comparison
204// One complicating factor here is that bits 32-63 of an i32 are undefined.
205// FIXME: Ideally, setcc would always produce an i64 on MIPS64 targets.
206//        This would allow us to remove the sign-extensions here.
207def : MipsPat<(select i32:$cond, i64:$t, i64:$f),
208              (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
209                    (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
210              ISA_MIPS64R6;
211def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, i64:$f),
212              (OR64 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)),
213                    (SELNEZ64 i64:$f, (SLL64_32 i32:$cond)))>,
214              ISA_MIPS64R6;
215def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, i64:$f),
216              (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
217                    (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
218              ISA_MIPS64R6;
219def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
220              (OR64 (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
221                                                      immZExt16:$imm))),
222                    (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
223                                                      immZExt16:$imm))))>,
224              ISA_MIPS64R6;
225def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
226              (OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
227                                                      immZExt16:$imm))),
228                    (SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
229                                                      immZExt16:$imm))))>,
230              ISA_MIPS64R6;
231
232def : MipsPat<(select i32:$cond, i64:$t, immz),
233              (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
234              ISA_MIPS64R6;
235def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, immz),
236              (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
237              ISA_MIPS64R6;
238def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, immz),
239              (SELEQZ64 i64:$t, (SLL64_32 i32:$cond))>,
240              ISA_MIPS64R6;
241def : MipsPat<(select i32:$cond, immz, i64:$f),
242              (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
243              ISA_MIPS64R6;
244def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i64:$f),
245              (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
246              ISA_MIPS64R6;
247def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i64:$f),
248              (SELNEZ64 i64:$f, (SLL64_32 i32:$cond))>,
249              ISA_MIPS64R6;
250