1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Mips target spec.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "MipsTargetMachine.h"
15 #include "Mips.h"
16 #include "Mips16FrameLowering.h"
17 #include "Mips16ISelDAGToDAG.h"
18 #include "Mips16ISelLowering.h"
19 #include "Mips16InstrInfo.h"
20 #include "MipsFrameLowering.h"
21 #include "MipsInstrInfo.h"
22 #include "MipsSEFrameLowering.h"
23 #include "MipsSEISelDAGToDAG.h"
24 #include "MipsSEISelLowering.h"
25 #include "MipsSEInstrInfo.h"
26 #include "MipsTargetObjectFile.h"
27 #include "llvm/Analysis/TargetTransformInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/CodeGen/TargetPassConfig.h"
30 #include "llvm/IR/LegacyPassManager.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/TargetRegistry.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Transforms/Scalar.h"
35
36 using namespace llvm;
37
38 #define DEBUG_TYPE "mips"
39
LLVMInitializeMipsTarget()40 extern "C" void LLVMInitializeMipsTarget() {
41 // Register the target.
42 RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
43 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
44 RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
45 RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
46 }
47
computeDataLayout(const Triple & TT,StringRef CPU,const TargetOptions & Options,bool isLittle)48 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
49 const TargetOptions &Options,
50 bool isLittle) {
51 std::string Ret = "";
52 MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions);
53
54 // There are both little and big endian mips.
55 if (isLittle)
56 Ret += "e";
57 else
58 Ret += "E";
59
60 Ret += "-m:m";
61
62 // Pointers are 32 bit on some ABIs.
63 if (!ABI.IsN64())
64 Ret += "-p:32:32";
65
66 // 8 and 16 bit integers only need to have natural alignment, but try to
67 // align them to 32 bits. 64 bit integers have natural alignment.
68 Ret += "-i8:8:32-i16:16:32-i64:64";
69
70 // 32 bit registers are always available and the stack is at least 64 bit
71 // aligned. On N64 64 bit registers are also available and the stack is
72 // 128 bit aligned.
73 if (ABI.IsN64() || ABI.IsN32())
74 Ret += "-n32:64-S128";
75 else
76 Ret += "-n32-S64";
77
78 return Ret;
79 }
80
getEffectiveRelocModel(CodeModel::Model CM,Optional<Reloc::Model> RM)81 static Reloc::Model getEffectiveRelocModel(CodeModel::Model CM,
82 Optional<Reloc::Model> RM) {
83 if (!RM.hasValue() || CM == CodeModel::JITDefault)
84 return Reloc::Static;
85 return *RM;
86 }
87
88 // On function prologue, the stack is created by decrementing
89 // its pointer. Once decremented, all references are done with positive
90 // offset from the stack/frame pointer, using StackGrowsUp enables
91 // an easier handling.
92 // Using CodeModel::Large enables different CALL behavior.
MipsTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,CodeModel::Model CM,CodeGenOpt::Level OL,bool isLittle)93 MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT,
94 StringRef CPU, StringRef FS,
95 const TargetOptions &Options,
96 Optional<Reloc::Model> RM,
97 CodeModel::Model CM, CodeGenOpt::Level OL,
98 bool isLittle)
99 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
100 CPU, FS, Options, getEffectiveRelocModel(CM, RM), CM,
101 OL),
102 isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()),
103 ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
104 Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this),
105 NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
106 isLittle, *this),
107 Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
108 isLittle, *this) {
109 Subtarget = &DefaultSubtarget;
110 initAsmInfo();
111 }
112
~MipsTargetMachine()113 MipsTargetMachine::~MipsTargetMachine() {}
114
anchor()115 void MipsebTargetMachine::anchor() { }
116
MipsebTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,CodeModel::Model CM,CodeGenOpt::Level OL)117 MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT,
118 StringRef CPU, StringRef FS,
119 const TargetOptions &Options,
120 Optional<Reloc::Model> RM,
121 CodeModel::Model CM,
122 CodeGenOpt::Level OL)
123 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
124
anchor()125 void MipselTargetMachine::anchor() { }
126
MipselTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,CodeModel::Model CM,CodeGenOpt::Level OL)127 MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT,
128 StringRef CPU, StringRef FS,
129 const TargetOptions &Options,
130 Optional<Reloc::Model> RM,
131 CodeModel::Model CM,
132 CodeGenOpt::Level OL)
133 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
134
135 const MipsSubtarget *
getSubtargetImpl(const Function & F) const136 MipsTargetMachine::getSubtargetImpl(const Function &F) const {
137 Attribute CPUAttr = F.getFnAttribute("target-cpu");
138 Attribute FSAttr = F.getFnAttribute("target-features");
139
140 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
141 ? CPUAttr.getValueAsString().str()
142 : TargetCPU;
143 std::string FS = !FSAttr.hasAttribute(Attribute::None)
144 ? FSAttr.getValueAsString().str()
145 : TargetFS;
146 bool hasMips16Attr =
147 !F.getFnAttribute("mips16").hasAttribute(Attribute::None);
148 bool hasNoMips16Attr =
149 !F.getFnAttribute("nomips16").hasAttribute(Attribute::None);
150
151 // FIXME: This is related to the code below to reset the target options,
152 // we need to know whether or not the soft float flag is set on the
153 // function, so we can enable it as a subtarget feature.
154 bool softFloat =
155 F.hasFnAttribute("use-soft-float") &&
156 F.getFnAttribute("use-soft-float").getValueAsString() == "true";
157
158 if (hasMips16Attr)
159 FS += FS.empty() ? "+mips16" : ",+mips16";
160 else if (hasNoMips16Attr)
161 FS += FS.empty() ? "-mips16" : ",-mips16";
162 if (softFloat)
163 FS += FS.empty() ? "+soft-float" : ",+soft-float";
164
165 auto &I = SubtargetMap[CPU + FS];
166 if (!I) {
167 // This needs to be done before we create a new subtarget since any
168 // creation will depend on the TM and the code generation flags on the
169 // function that reside in TargetOptions.
170 resetTargetOptions(F);
171 I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle,
172 *this);
173 }
174 return I.get();
175 }
176
resetSubtarget(MachineFunction * MF)177 void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
178 DEBUG(dbgs() << "resetSubtarget\n");
179
180 Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(*MF->getFunction()));
181 MF->setSubtarget(Subtarget);
182 return;
183 }
184
185 namespace {
186 /// Mips Code Generator Pass Configuration Options.
187 class MipsPassConfig : public TargetPassConfig {
188 public:
MipsPassConfig(MipsTargetMachine * TM,PassManagerBase & PM)189 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
190 : TargetPassConfig(TM, PM) {
191 // The current implementation of long branch pass requires a scratch
192 // register ($at) to be available before branch instructions. Tail merging
193 // can break this requirement, so disable it when long branch pass is
194 // enabled.
195 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
196 }
197
getMipsTargetMachine() const198 MipsTargetMachine &getMipsTargetMachine() const {
199 return getTM<MipsTargetMachine>();
200 }
201
getMipsSubtarget() const202 const MipsSubtarget &getMipsSubtarget() const {
203 return *getMipsTargetMachine().getSubtargetImpl();
204 }
205
206 void addIRPasses() override;
207 bool addInstSelector() override;
208 void addMachineSSAOptimization() override;
209 void addPreEmitPass() override;
210
211 void addPreRegAlloc() override;
212
213 };
214 } // namespace
215
createPassConfig(PassManagerBase & PM)216 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
217 return new MipsPassConfig(this, PM);
218 }
219
addIRPasses()220 void MipsPassConfig::addIRPasses() {
221 TargetPassConfig::addIRPasses();
222 addPass(createAtomicExpandPass(&getMipsTargetMachine()));
223 if (getMipsSubtarget().os16())
224 addPass(createMipsOs16Pass(getMipsTargetMachine()));
225 if (getMipsSubtarget().inMips16HardFloat())
226 addPass(createMips16HardFloatPass(getMipsTargetMachine()));
227 }
228 // Install an instruction selector pass using
229 // the ISelDag to gen Mips code.
addInstSelector()230 bool MipsPassConfig::addInstSelector() {
231 addPass(createMipsModuleISelDagPass(getMipsTargetMachine()));
232 addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel()));
233 addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel()));
234 return false;
235 }
236
addMachineSSAOptimization()237 void MipsPassConfig::addMachineSSAOptimization() {
238 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
239 TargetPassConfig::addMachineSSAOptimization();
240 }
241
addPreRegAlloc()242 void MipsPassConfig::addPreRegAlloc() {
243 if (getOptLevel() == CodeGenOpt::None)
244 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
245 }
246
getTargetIRAnalysis()247 TargetIRAnalysis MipsTargetMachine::getTargetIRAnalysis() {
248 return TargetIRAnalysis([this](const Function &F) {
249 if (Subtarget->allowMixed16_32()) {
250 DEBUG(errs() << "No Target Transform Info Pass Added\n");
251 // FIXME: This is no longer necessary as the TTI returned is per-function.
252 return TargetTransformInfo(F.getParent()->getDataLayout());
253 }
254
255 DEBUG(errs() << "Target Transform Info Pass Added\n");
256 return TargetTransformInfo(BasicTTIImpl(this, F));
257 });
258 }
259
260 // Implemented by targets that want to run passes immediately before
261 // machine code is emitted. return true if -print-machineinstrs should
262 // print out the code after the passes.
addPreEmitPass()263 void MipsPassConfig::addPreEmitPass() {
264 MipsTargetMachine &TM = getMipsTargetMachine();
265
266 // The delay slot filler pass can potientially create forbidden slot (FS)
267 // hazards for MIPSR6 which the hazard schedule pass (HSP) will fix. Any
268 // (new) pass that creates compact branches after the HSP must handle FS
269 // hazards itself or be pipelined before the HSP.
270 addPass(createMipsDelaySlotFillerPass(TM));
271 addPass(createMipsHazardSchedule());
272 addPass(createMipsLongBranchPass(TM));
273 addPass(createMipsConstantIslandPass());
274 }
275