1//==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Basic SystemZ instruction definition
12//===----------------------------------------------------------------------===//
13
14class InstSystemZ<int size, dag outs, dag ins, string asmstr,
15                  list<dag> pattern> : Instruction {
16  let Namespace = "SystemZ";
17
18  dag OutOperandList = outs;
19  dag InOperandList = ins;
20  let Size = size;
21  let Pattern = pattern;
22  let AsmString = asmstr;
23
24  // Some instructions come in pairs, one having a 12-bit displacement
25  // and the other having a 20-bit displacement.  Both instructions in
26  // the pair have the same DispKey and their DispSizes are "12" and "20"
27  // respectively.
28  string DispKey = "";
29  string DispSize = "none";
30
31  // Many register-based <INSN>R instructions have a memory-based <INSN>
32  // counterpart.  OpKey uniquely identifies <INSN>, while OpType is
33  // "reg" for <INSN>R and "mem" for <INSN>.
34  string OpKey = "";
35  string OpType = "none";
36
37  // Many distinct-operands instructions have older 2-operand equivalents.
38  // NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs,
39  // with NumOpsValue being "2" or "3" as appropriate.
40  string NumOpsKey = "";
41  string NumOpsValue = "none";
42
43  // True if this instruction is a simple D(X,B) load of a register
44  // (with no sign or zero extension).
45  bit SimpleBDXLoad = 0;
46
47  // True if this instruction is a simple D(X,B) store of a register
48  // (with no truncation).
49  bit SimpleBDXStore = 0;
50
51  // True if this instruction has a 20-bit displacement field.
52  bit Has20BitOffset = 0;
53
54  // True if addresses in this instruction have an index register.
55  bit HasIndex = 0;
56
57  // True if this is a 128-bit pseudo instruction that combines two 64-bit
58  // operations.
59  bit Is128Bit = 0;
60
61  // The access size of all memory operands in bytes, or 0 if not known.
62  bits<5> AccessBytes = 0;
63
64  // If the instruction sets CC to a useful value, this gives the mask
65  // of all possible CC results.  The mask has the same form as
66  // SystemZ::CCMASK_*.
67  bits<4> CCValues = 0;
68
69  // The subset of CCValues that have the same meaning as they would after
70  // a comparison of the first operand against zero.
71  bits<4> CompareZeroCCMask = 0;
72
73  // True if the instruction is conditional and if the CC mask operand
74  // comes first (as for BRC, etc.).
75  bit CCMaskFirst = 0;
76
77  // Similar, but true if the CC mask operand comes last (as for LOC, etc.).
78  bit CCMaskLast = 0;
79
80  // True if the instruction is the "logical" rather than "arithmetic" form,
81  // in cases where a distinction exists.
82  bit IsLogical = 0;
83
84  let TSFlags{0}     = SimpleBDXLoad;
85  let TSFlags{1}     = SimpleBDXStore;
86  let TSFlags{2}     = Has20BitOffset;
87  let TSFlags{3}     = HasIndex;
88  let TSFlags{4}     = Is128Bit;
89  let TSFlags{9-5}   = AccessBytes;
90  let TSFlags{13-10} = CCValues;
91  let TSFlags{17-14} = CompareZeroCCMask;
92  let TSFlags{18}    = CCMaskFirst;
93  let TSFlags{19}    = CCMaskLast;
94  let TSFlags{20}    = IsLogical;
95}
96
97//===----------------------------------------------------------------------===//
98// Mappings between instructions
99//===----------------------------------------------------------------------===//
100
101// Return the version of an instruction that has an unsigned 12-bit
102// displacement.
103def getDisp12Opcode : InstrMapping {
104  let FilterClass = "InstSystemZ";
105  let RowFields = ["DispKey"];
106  let ColFields = ["DispSize"];
107  let KeyCol = ["20"];
108  let ValueCols = [["12"]];
109}
110
111// Return the version of an instruction that has a signed 20-bit displacement.
112def getDisp20Opcode : InstrMapping {
113  let FilterClass = "InstSystemZ";
114  let RowFields = ["DispKey"];
115  let ColFields = ["DispSize"];
116  let KeyCol = ["12"];
117  let ValueCols = [["20"]];
118}
119
120// Return the memory form of a register instruction.
121def getMemOpcode : InstrMapping {
122  let FilterClass = "InstSystemZ";
123  let RowFields = ["OpKey"];
124  let ColFields = ["OpType"];
125  let KeyCol = ["reg"];
126  let ValueCols = [["mem"]];
127}
128
129// Return the 3-operand form of a 2-operand instruction.
130def getThreeOperandOpcode : InstrMapping {
131  let FilterClass = "InstSystemZ";
132  let RowFields = ["NumOpsKey"];
133  let ColFields = ["NumOpsValue"];
134  let KeyCol = ["2"];
135  let ValueCols = [["3"]];
136}
137
138//===----------------------------------------------------------------------===//
139// Instruction formats
140//===----------------------------------------------------------------------===//
141//
142// Formats are specified using operand field declarations of the form:
143//
144//   bits<4> Rn   : register input or output for operand n
145//   bits<5> Vn   : vector register input or output for operand n
146//   bits<m> In   : immediate value of width m for operand n
147//   bits<4> BDn  : address operand n, which has a base and a displacement
148//   bits<m> XBDn : address operand n, which has an index, a base and a
149//                  displacement
150//   bits<m> VBDn : address operand n, which has a vector index, a base and a
151//                  displacement
152//   bits<4> Xn   : index register for address operand n
153//   bits<4> Mn   : mode value for operand n
154//
155// The operand numbers ("n" in the list above) follow the architecture manual.
156// Assembly operands sometimes have a different order; in particular, R3 often
157// is often written between operands 1 and 2.
158//
159//===----------------------------------------------------------------------===//
160
161class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
162  : InstSystemZ<2, outs, ins, asmstr, pattern> {
163  field bits<16> Inst;
164  field bits<16> SoftFail = 0;
165
166  bits<8> I1;
167
168  let Inst{15-8} = op;
169  let Inst{7-0}  = I1;
170}
171
172class InstRI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
173  : InstSystemZ<4, outs, ins, asmstr, pattern> {
174  field bits<32> Inst;
175  field bits<32> SoftFail = 0;
176
177  bits<4> R1;
178  bits<16> I2;
179
180  let Inst{31-24} = op{11-4};
181  let Inst{23-20} = R1;
182  let Inst{19-16} = op{3-0};
183  let Inst{15-0}  = I2;
184}
185
186class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
187  : InstSystemZ<6, outs, ins, asmstr, pattern> {
188  field bits<48> Inst;
189  field bits<48> SoftFail = 0;
190
191  bits<4> R1;
192  bits<16> I2;
193  bits<4> M3;
194
195  let Inst{47-40} = op{15-8};
196  let Inst{39-36} = R1;
197  let Inst{35-32} = 0;
198  let Inst{31-16} = I2;
199  let Inst{15-12} = M3;
200  let Inst{11-8}  = 0;
201  let Inst{7-0}   = op{7-0};
202}
203
204class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
205  : InstSystemZ<6, outs, ins, asmstr, pattern> {
206  field bits<48> Inst;
207  field bits<48> SoftFail = 0;
208
209  bits<4> R1;
210  bits<4> R2;
211  bits<4> M3;
212  bits<16> RI4;
213
214  let Inst{47-40} = op{15-8};
215  let Inst{39-36} = R1;
216  let Inst{35-32} = R2;
217  let Inst{31-16} = RI4;
218  let Inst{15-12} = M3;
219  let Inst{11-8}  = 0;
220  let Inst{7-0}   = op{7-0};
221}
222
223class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
224  : InstSystemZ<6, outs, ins, asmstr, pattern> {
225  field bits<48> Inst;
226  field bits<48> SoftFail = 0;
227
228  bits<4> R1;
229  bits<8> I2;
230  bits<4> M3;
231  bits<16> RI4;
232
233  let Inst{47-40} = op{15-8};
234  let Inst{39-36} = R1;
235  let Inst{35-32} = M3;
236  let Inst{31-16} = RI4;
237  let Inst{15-8}  = I2;
238  let Inst{7-0}   = op{7-0};
239}
240
241class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
242  : InstSystemZ<6, outs, ins, asmstr, pattern> {
243  field bits<48> Inst;
244  field bits<48> SoftFail = 0;
245
246  bits<4> R1;
247  bits<4> R3;
248  bits<16> I2;
249
250  let Inst{47-40} = op{15-8};
251  let Inst{39-36} = R1;
252  let Inst{35-32} = R3;
253  let Inst{31-16} = I2;
254  let Inst{15-8}  = 0;
255  let Inst{7-0}   = op{7-0};
256}
257
258class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
259  : InstSystemZ<6, outs, ins, asmstr, pattern> {
260  field bits<48> Inst;
261  field bits<48> SoftFail = 0;
262
263  bits<4> R1;
264  bits<4> R2;
265  bits<8> I3;
266  bits<8> I4;
267  bits<8> I5;
268
269  let Inst{47-40} = op{15-8};
270  let Inst{39-36} = R1;
271  let Inst{35-32} = R2;
272  let Inst{31-24} = I3;
273  let Inst{23-16} = I4;
274  let Inst{15-8}  = I5;
275  let Inst{7-0}   = op{7-0};
276}
277
278class InstRIL<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
279  : InstSystemZ<6, outs, ins, asmstr, pattern> {
280  field bits<48> Inst;
281  field bits<48> SoftFail = 0;
282
283  bits<4> R1;
284  bits<32> I2;
285
286  let Inst{47-40} = op{11-4};
287  let Inst{39-36} = R1;
288  let Inst{35-32} = op{3-0};
289  let Inst{31-0}  = I2;
290}
291
292class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
293  : InstSystemZ<6, outs, ins, asmstr, pattern> {
294  field bits<48> Inst;
295  field bits<48> SoftFail = 0;
296
297  bits<4> R1;
298  bits<8> I2;
299  bits<4> M3;
300  bits<16> BD4;
301
302  let Inst{47-40} = op{15-8};
303  let Inst{39-36} = R1;
304  let Inst{35-32} = M3;
305  let Inst{31-16} = BD4;
306  let Inst{15-8}  = I2;
307  let Inst{7-0}   = op{7-0};
308}
309
310class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
311  : InstSystemZ<2, outs, ins, asmstr, pattern> {
312  field bits<16> Inst;
313  field bits<16> SoftFail = 0;
314
315  bits<4> R1;
316  bits<4> R2;
317
318  let Inst{15-8} = op;
319  let Inst{7-4}  = R1;
320  let Inst{3-0}  = R2;
321}
322
323class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
324  : InstSystemZ<4, outs, ins, asmstr, pattern> {
325  field bits<32> Inst;
326  field bits<32> SoftFail = 0;
327
328  bits<4> R1;
329  bits<4> R3;
330  bits<4> R2;
331
332  let Inst{31-16} = op;
333  let Inst{15-12} = R1;
334  let Inst{11-8}  = 0;
335  let Inst{7-4}   = R3;
336  let Inst{3-0}   = R2;
337}
338
339class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
340  : InstSystemZ<4, outs, ins, asmstr, pattern> {
341  field bits<32> Inst;
342  field bits<32> SoftFail = 0;
343
344  bits<4> R1;
345  bits<4> R2;
346
347  let Inst{31-16} = op;
348  let Inst{15-8}  = 0;
349  let Inst{7-4}   = R1;
350  let Inst{3-0}   = R2;
351}
352
353class InstRRF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
354  : InstSystemZ<4, outs, ins, asmstr, pattern> {
355  field bits<32> Inst;
356  field bits<32> SoftFail = 0;
357
358  bits<4> R1;
359  bits<4> R2;
360  bits<4> R3;
361  bits<4> R4;
362
363  let Inst{31-16} = op;
364  let Inst{15-12} = R3;
365  let Inst{11-8}  = R4;
366  let Inst{7-4}   = R1;
367  let Inst{3-0}   = R2;
368}
369
370class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
371  : InstSystemZ<4, outs, ins, asmstr, pattern> {
372  field bits<32> Inst;
373  field bits<32> SoftFail = 0;
374
375  bits<4> R1;
376  bits<4> R2;
377  bits<4> M3;
378
379  let Inst{31-16} = op;
380  let Inst{15-12} = M3;
381  let Inst{11-8}  = 0;
382  let Inst{7-4}   = R1;
383  let Inst{3-0}   = R2;
384}
385
386class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
387  : InstSystemZ<6, outs, ins, asmstr, pattern> {
388  field bits<48> Inst;
389  field bits<48> SoftFail = 0;
390
391  bits<4> R1;
392  bits<4> R2;
393  bits<4> M3;
394  bits<16> BD4;
395
396  let Inst{47-40} = op{15-8};
397  let Inst{39-36} = R1;
398  let Inst{35-32} = R2;
399  let Inst{31-16} = BD4;
400  let Inst{15-12} = M3;
401  let Inst{11-8}  = 0;
402  let Inst{7-0}   = op{7-0};
403}
404
405class InstRX<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
406  : InstSystemZ<4, outs, ins, asmstr, pattern> {
407  field bits<32> Inst;
408  field bits<32> SoftFail = 0;
409
410  bits<4> R1;
411  bits<20> XBD2;
412
413  let Inst{31-24} = op;
414  let Inst{23-20} = R1;
415  let Inst{19-0}  = XBD2;
416
417  let HasIndex = 1;
418}
419
420class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
421  : InstSystemZ<6, outs, ins, asmstr, pattern> {
422  field bits<48> Inst;
423  field bits<48> SoftFail = 0;
424
425  bits<4> R1;
426  bits<20> XBD2;
427  bits<4> M3;
428
429  let Inst{47-40} = op{15-8};
430  let Inst{39-36} = R1;
431  let Inst{35-16} = XBD2;
432  let Inst{15-12} = M3;
433  let Inst{11-8}  = 0;
434  let Inst{7-0}   = op{7-0};
435
436  let HasIndex = 1;
437}
438
439class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
440  : InstSystemZ<6, outs, ins, asmstr, pattern> {
441  field bits<48> Inst;
442  field bits<48> SoftFail = 0;
443
444  bits<4> R1;
445  bits<4> R3;
446  bits<20> XBD2;
447
448  let Inst{47-40} = op{15-8};
449  let Inst{39-36} = R3;
450  let Inst{35-16} = XBD2;
451  let Inst{15-12} = R1;
452  let Inst{11-8}  = 0;
453  let Inst{7-0}   = op{7-0};
454
455  let HasIndex = 1;
456}
457
458class InstRXY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
459  : InstSystemZ<6, outs, ins, asmstr, pattern> {
460  field bits<48> Inst;
461  field bits<48> SoftFail = 0;
462
463  bits<4> R1;
464  bits<28> XBD2;
465
466  let Inst{47-40} = op{15-8};
467  let Inst{39-36} = R1;
468  let Inst{35-8}  = XBD2;
469  let Inst{7-0}   = op{7-0};
470
471  let Has20BitOffset = 1;
472  let HasIndex = 1;
473}
474
475class InstRS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
476  : InstSystemZ<4, outs, ins, asmstr, pattern> {
477  field bits<32> Inst;
478  field bits<32> SoftFail = 0;
479
480  bits<4> R1;
481  bits<4> R3;
482  bits<16> BD2;
483
484  let Inst{31-24} = op;
485  let Inst{23-20} = R1;
486  let Inst{19-16} = R3;
487  let Inst{15-0}  = BD2;
488}
489
490class InstRSY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
491  : InstSystemZ<6, outs, ins, asmstr, pattern> {
492  field bits<48> Inst;
493  field bits<48> SoftFail = 0;
494
495  bits<4> R1;
496  bits<4> R3;
497  bits<24> BD2;
498
499  let Inst{47-40} = op{15-8};
500  let Inst{39-36} = R1;
501  let Inst{35-32} = R3;
502  let Inst{31-8}  = BD2;
503  let Inst{7-0}   = op{7-0};
504
505  let Has20BitOffset = 1;
506}
507
508class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
509  : InstSystemZ<4, outs, ins, asmstr, pattern> {
510  field bits<32> Inst;
511  field bits<32> SoftFail = 0;
512
513  bits<16> BD1;
514  bits<8> I2;
515
516  let Inst{31-24} = op;
517  let Inst{23-16} = I2;
518  let Inst{15-0}  = BD1;
519}
520
521class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
522  : InstSystemZ<6, outs, ins, asmstr, pattern> {
523  field bits<48> Inst;
524  field bits<48> SoftFail = 0;
525
526  bits<16> BD1;
527  bits<16> I2;
528
529  let Inst{47-32} = op;
530  let Inst{31-16} = BD1;
531  let Inst{15-0}  = I2;
532}
533
534class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
535  : InstSystemZ<6, outs, ins, asmstr, pattern> {
536  field bits<48> Inst;
537  field bits<48> SoftFail = 0;
538
539  bits<24> BD1;
540  bits<8> I2;
541
542  let Inst{47-40} = op{15-8};
543  let Inst{39-32} = I2;
544  let Inst{31-8}  = BD1;
545  let Inst{7-0}   = op{7-0};
546
547  let Has20BitOffset = 1;
548}
549
550class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
551  : InstSystemZ<6, outs, ins, asmstr, pattern> {
552  field bits<48> Inst;
553  field bits<48> SoftFail = 0;
554
555  bits<24> BDL1;
556  bits<16> BD2;
557
558  let Inst{47-40} = op;
559  let Inst{39-16} = BDL1;
560  let Inst{15-0}  = BD2;
561}
562
563class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
564  : InstSystemZ<4, outs, ins, asmstr, pattern> {
565  field bits<32> Inst;
566  field bits<32> SoftFail = 0;
567
568  bits<16> BD2;
569
570  let Inst{31-16} = op;
571  let Inst{15-0}  = BD2;
572}
573
574class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
575  : InstSystemZ<6, outs, ins, asmstr, pattern> {
576  field bits<48> Inst;
577  field bits<48> SoftFail = 0;
578
579  bits<5> V1;
580  bits<16> I2;
581  bits<4> M3;
582
583  let Inst{47-40} = op{15-8};
584  let Inst{39-36} = V1{3-0};
585  let Inst{35-32} = 0;
586  let Inst{31-16} = I2;
587  let Inst{15-12} = M3;
588  let Inst{11}    = V1{4};
589  let Inst{10-8}  = 0;
590  let Inst{7-0}   = op{7-0};
591}
592
593class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
594  : InstSystemZ<6, outs, ins, asmstr, pattern> {
595  field bits<48> Inst;
596  field bits<48> SoftFail = 0;
597
598  bits<5> V1;
599  bits<8> I2;
600  bits<8> I3;
601  bits<4> M4;
602
603  let Inst{47-40} = op{15-8};
604  let Inst{39-36} = V1{3-0};
605  let Inst{35-32} = 0;
606  let Inst{31-24} = I2;
607  let Inst{23-16} = I3;
608  let Inst{15-12} = M4;
609  let Inst{11}    = V1{4};
610  let Inst{10-8}  = 0;
611  let Inst{7-0}   = op{7-0};
612}
613
614class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
615  : InstSystemZ<6, outs, ins, asmstr, pattern> {
616  field bits<48> Inst;
617  field bits<48> SoftFail = 0;
618
619  bits<5> V1;
620  bits<5> V3;
621  bits<16> I2;
622  bits<4> M4;
623
624  let Inst{47-40} = op{15-8};
625  let Inst{39-36} = V1{3-0};
626  let Inst{35-32} = V3{3-0};
627  let Inst{31-16} = I2;
628  let Inst{15-12} = M4;
629  let Inst{11}    = V1{4};
630  let Inst{10}    = V3{4};
631  let Inst{9-8}   = 0;
632  let Inst{7-0}   = op{7-0};
633}
634
635class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
636  : InstSystemZ<6, outs, ins, asmstr, pattern> {
637  field bits<48> Inst;
638  field bits<48> SoftFail = 0;
639
640  bits<5> V1;
641  bits<5> V2;
642  bits<5> V3;
643  bits<8> I4;
644  bits<4> M5;
645
646  let Inst{47-40} = op{15-8};
647  let Inst{39-36} = V1{3-0};
648  let Inst{35-32} = V2{3-0};
649  let Inst{31-28} = V3{3-0};
650  let Inst{27-24} = 0;
651  let Inst{23-16} = I4;
652  let Inst{15-12} = M5;
653  let Inst{11}    = V1{4};
654  let Inst{10}    = V2{4};
655  let Inst{9}     = V3{4};
656  let Inst{8}     = 0;
657  let Inst{7-0}   = op{7-0};
658}
659
660class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
661  : InstSystemZ<6, outs, ins, asmstr, pattern> {
662  field bits<48> Inst;
663  field bits<48> SoftFail = 0;
664
665  bits<5> V1;
666  bits<5> V2;
667  bits<12> I3;
668  bits<4> M4;
669  bits<4> M5;
670
671  let Inst{47-40} = op{15-8};
672  let Inst{39-36} = V1{3-0};
673  let Inst{35-32} = V2{3-0};
674  let Inst{31-20} = I3;
675  let Inst{19-16} = M5;
676  let Inst{15-12} = M4;
677  let Inst{11}    = V1{4};
678  let Inst{10}    = V2{4};
679  let Inst{9-8}   = 0;
680  let Inst{7-0}   = op{7-0};
681}
682
683// Depending on the instruction mnemonic, certain bits may be or-ed into
684// the M4 value provided as explicit operand.  These are passed as m4or.
685class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
686               bits<4> m4or = 0>
687  : InstSystemZ<6, outs, ins, asmstr, pattern> {
688  field bits<48> Inst;
689  field bits<48> SoftFail = 0;
690
691  bits<5> V1;
692  bits<5> V2;
693  bits<4> M3;
694  bits<4> M4;
695  bits<4> M5;
696
697  let Inst{47-40} = op{15-8};
698  let Inst{39-36} = V1{3-0};
699  let Inst{35-32} = V2{3-0};
700  let Inst{31-24} = 0;
701  let Inst{23-20} = M5;
702  let Inst{19}    = !if (!eq (m4or{3}, 1), 1, M4{3});
703  let Inst{18}    = !if (!eq (m4or{2}, 1), 1, M4{2});
704  let Inst{17}    = !if (!eq (m4or{1}, 1), 1, M4{1});
705  let Inst{16}    = !if (!eq (m4or{0}, 1), 1, M4{0});
706  let Inst{15-12} = M3;
707  let Inst{11}    = V1{4};
708  let Inst{10}    = V2{4};
709  let Inst{9-8}   = 0;
710  let Inst{7-0}   = op{7-0};
711}
712
713// Depending on the instruction mnemonic, certain bits may be or-ed into
714// the M5 value provided as explicit operand.  These are passed as m5or.
715class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
716               bits<4> m5or = 0>
717  : InstSystemZ<6, outs, ins, asmstr, pattern> {
718  field bits<48> Inst;
719  field bits<48> SoftFail = 0;
720
721  bits<5> V1;
722  bits<5> V2;
723  bits<5> V3;
724  bits<4> M4;
725  bits<4> M5;
726
727  let Inst{47-40} = op{15-8};
728  let Inst{39-36} = V1{3-0};
729  let Inst{35-32} = V2{3-0};
730  let Inst{31-28} = V3{3-0};
731  let Inst{27-24} = 0;
732  let Inst{23}    = !if (!eq (m5or{3}, 1), 1, M5{3});
733  let Inst{22}    = !if (!eq (m5or{2}, 1), 1, M5{2});
734  let Inst{21}    = !if (!eq (m5or{1}, 1), 1, M5{1});
735  let Inst{20}    = !if (!eq (m5or{0}, 1), 1, M5{0});
736  let Inst{19-16} = 0;
737  let Inst{15-12} = M4;
738  let Inst{11}    = V1{4};
739  let Inst{10}    = V2{4};
740  let Inst{9}     = V3{4};
741  let Inst{8}     = 0;
742  let Inst{7-0}   = op{7-0};
743}
744
745class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
746  : InstSystemZ<6, outs, ins, asmstr, pattern> {
747  field bits<48> Inst;
748  field bits<48> SoftFail = 0;
749
750  bits<5> V1;
751  bits<5> V2;
752  bits<5> V3;
753  bits<4> M4;
754  bits<4> M5;
755  bits<4> M6;
756
757  let Inst{47-40} = op{15-8};
758  let Inst{39-36} = V1{3-0};
759  let Inst{35-32} = V2{3-0};
760  let Inst{31-28} = V3{3-0};
761  let Inst{27-24} = 0;
762  let Inst{23-20} = M6;
763  let Inst{19-16} = M5;
764  let Inst{15-12} = M4;
765  let Inst{11}    = V1{4};
766  let Inst{10}    = V2{4};
767  let Inst{9}     = V3{4};
768  let Inst{8}     = 0;
769  let Inst{7-0}   = op{7-0};
770}
771
772// Depending on the instruction mnemonic, certain bits may be or-ed into
773// the M6 value provided as explicit operand.  These are passed as m6or.
774class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
775               bits<4> m6or = 0>
776  : InstSystemZ<6, outs, ins, asmstr, pattern> {
777  field bits<48> Inst;
778  field bits<48> SoftFail = 0;
779
780  bits<5> V1;
781  bits<5> V2;
782  bits<5> V3;
783  bits<5> V4;
784  bits<4> M5;
785  bits<4> M6;
786
787  let Inst{47-40} = op{15-8};
788  let Inst{39-36} = V1{3-0};
789  let Inst{35-32} = V2{3-0};
790  let Inst{31-28} = V3{3-0};
791  let Inst{27-24} = M5;
792  let Inst{23}    = !if (!eq (m6or{3}, 1), 1, M6{3});
793  let Inst{22}    = !if (!eq (m6or{2}, 1), 1, M6{2});
794  let Inst{21}    = !if (!eq (m6or{1}, 1), 1, M6{1});
795  let Inst{20}    = !if (!eq (m6or{0}, 1), 1, M6{0});
796  let Inst{19-16} = 0;
797  let Inst{15-12} = V4{3-0};
798  let Inst{11}    = V1{4};
799  let Inst{10}    = V2{4};
800  let Inst{9}     = V3{4};
801  let Inst{8}     = V4{4};
802  let Inst{7-0}   = op{7-0};
803}
804
805class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
806  : InstSystemZ<6, outs, ins, asmstr, pattern> {
807  field bits<48> Inst;
808  field bits<48> SoftFail = 0;
809
810  bits<5> V1;
811  bits<5> V2;
812  bits<5> V3;
813  bits<5> V4;
814  bits<4> M5;
815  bits<4> M6;
816
817  let Inst{47-40} = op{15-8};
818  let Inst{39-36} = V1{3-0};
819  let Inst{35-32} = V2{3-0};
820  let Inst{31-28} = V3{3-0};
821  let Inst{27-24} = M6;
822  let Inst{23-20} = 0;
823  let Inst{19-16} = M5;
824  let Inst{15-12} = V4{3-0};
825  let Inst{11}    = V1{4};
826  let Inst{10}    = V2{4};
827  let Inst{9}     = V3{4};
828  let Inst{8}     = V4{4};
829  let Inst{7-0}   = op{7-0};
830}
831
832class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
833  : InstSystemZ<6, outs, ins, asmstr, pattern> {
834  field bits<48> Inst;
835  field bits<48> SoftFail = 0;
836
837  bits<5> V1;
838  bits<4> R2;
839  bits<4> R3;
840
841  let Inst{47-40} = op{15-8};
842  let Inst{39-36} = V1{3-0};
843  let Inst{35-32} = R2;
844  let Inst{31-28} = R3;
845  let Inst{27-12} = 0;
846  let Inst{11}    = V1{4};
847  let Inst{10-8}  = 0;
848  let Inst{7-0}   = op{7-0};
849}
850
851class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
852  : InstSystemZ<6, outs, ins, asmstr, pattern> {
853  field bits<48> Inst;
854  field bits<48> SoftFail = 0;
855
856  bits<5> V1;
857  bits<16> BD2;
858  bits<5> V3;
859  bits<4> M4;
860
861  let Inst{47-40} = op{15-8};
862  let Inst{39-36} = V1{3-0};
863  let Inst{35-32} = V3{3-0};
864  let Inst{31-16} = BD2;
865  let Inst{15-12} = M4;
866  let Inst{11}    = V1{4};
867  let Inst{10}    = V3{4};
868  let Inst{9-8}   = 0;
869  let Inst{7-0}   = op{7-0};
870}
871
872class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
873  : InstSystemZ<6, outs, ins, asmstr, pattern> {
874  field bits<48> Inst;
875  field bits<48> SoftFail = 0;
876
877  bits<5> V1;
878  bits<16> BD2;
879  bits<4> R3;
880  bits<4> M4;
881
882  let Inst{47-40} = op{15-8};
883  let Inst{39-36} = V1{3-0};
884  let Inst{35-32} = R3;
885  let Inst{31-16} = BD2;
886  let Inst{15-12} = M4;
887  let Inst{11}    = V1{4};
888  let Inst{10-8}  = 0;
889  let Inst{7-0}   = op{7-0};
890}
891
892class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
893  : InstSystemZ<6, outs, ins, asmstr, pattern> {
894  field bits<48> Inst;
895  field bits<48> SoftFail = 0;
896
897  bits<4> R1;
898  bits<16> BD2;
899  bits<5> V3;
900  bits<4> M4;
901
902  let Inst{47-40} = op{15-8};
903  let Inst{39-36} = R1;
904  let Inst{35-32} = V3{3-0};
905  let Inst{31-16} = BD2;
906  let Inst{15-12} = M4;
907  let Inst{11}    = 0;
908  let Inst{10}    = V3{4};
909  let Inst{9-8}   = 0;
910  let Inst{7-0}   = op{7-0};
911}
912
913class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
914  : InstSystemZ<6, outs, ins, asmstr, pattern> {
915  field bits<48> Inst;
916  field bits<48> SoftFail = 0;
917
918  bits<5> V1;
919  bits<21> VBD2;
920  bits<4> M3;
921
922  let Inst{47-40} = op{15-8};
923  let Inst{39-36} = V1{3-0};
924  let Inst{35-16} = VBD2{19-0};
925  let Inst{15-12} = M3;
926  let Inst{11}    = V1{4};
927  let Inst{10}    = VBD2{20};
928  let Inst{9-8}   = 0;
929  let Inst{7-0}   = op{7-0};
930}
931
932class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
933  : InstSystemZ<6, outs, ins, asmstr, pattern> {
934  field bits<48> Inst;
935  field bits<48> SoftFail = 0;
936
937  bits<5> V1;
938  bits<20> XBD2;
939  bits<4> M3;
940
941  let Inst{47-40} = op{15-8};
942  let Inst{39-36} = V1{3-0};
943  let Inst{35-16} = XBD2;
944  let Inst{15-12} = M3;
945  let Inst{11}    = V1{4};
946  let Inst{10-8}  = 0;
947  let Inst{7-0}   = op{7-0};
948}
949
950//===----------------------------------------------------------------------===//
951// Instruction definitions with semantics
952//===----------------------------------------------------------------------===//
953//
954// These classes have the form [Cond]<Category><Format>, where <Format> is one
955// of the formats defined above and where <Category> describes the inputs
956// and outputs.  "Cond" is used if the instruction is conditional,
957// in which case the 4-bit condition-code mask is added as a final operand.
958// <Category> can be one of:
959//
960//   Inherent:
961//     One register output operand and no input operands.
962//
963//   BranchUnary:
964//     One register output operand, one register input operand and
965//     one branch displacement.  The instructions stores a modified
966//     form of the source register in the destination register and
967//     branches on the result.
968//
969//   LoadMultiple:
970//     One address input operand and two explicit output operands.
971//     The instruction loads a range of registers from the address,
972//     with the explicit operands giving the first and last register
973//     to load.  Other loaded registers are added as implicit definitions.
974//
975//   StoreMultiple:
976//     Two explicit input register operands and an address operand.
977//     The instruction stores a range of registers to the address,
978//     with the explicit operands giving the first and last register
979//     to store.  Other stored registers are added as implicit uses.
980//
981//   StoreLength:
982//     One value operand, one length operand and one address operand.
983//     The instruction stores the value operand to the address but
984//     doesn't write more than the number of bytes specified by the
985//     length operand.
986//
987//   Unary:
988//     One register output operand and one input operand.
989//
990//   Store:
991//     One address operand and one other input operand.  The instruction
992//     stores to the address.
993//
994//   Binary:
995//     One register output operand and two input operands.
996//
997//   StoreBinary:
998//     One address operand and two other input operands.  The instruction
999//     stores to the address.
1000//
1001//   Compare:
1002//     Two input operands and an implicit CC output operand.
1003//
1004//   Test:
1005//     Two input operands and an implicit CC output operand.  The second
1006//     input operand is an "address" operand used as a test class mask.
1007//
1008//   Ternary:
1009//     One register output operand and three input operands.
1010//
1011//   Quaternary:
1012//     One register output operand and four input operands.
1013//
1014//   LoadAndOp:
1015//     One output operand and two input operands, one of which is an address.
1016//     The instruction both reads from and writes to the address.
1017//
1018//   CmpSwap:
1019//     One output operand and three input operands, one of which is an address.
1020//     The instruction both reads from and writes to the address.
1021//
1022//   RotateSelect:
1023//     One output operand and five input operands.  The first two operands
1024//     are registers and the other three are immediates.
1025//
1026//   Prefetch:
1027//     One 4-bit immediate operand and one address operand.  The immediate
1028//     operand is 1 for a load prefetch and 2 for a store prefetch.
1029//
1030// The format determines which input operands are tied to output operands,
1031// and also determines the shape of any address operand.
1032//
1033// Multiclasses of the form <Category><Format>Pair define two instructions,
1034// one with <Category><Format> and one with <Category><Format>Y.  The name
1035// of the first instruction has no suffix, the name of the second has
1036// an extra "y".
1037//
1038//===----------------------------------------------------------------------===//
1039
1040class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1041                  dag src>
1042  : InstRRE<opcode, (outs cls:$R1), (ins),
1043            mnemonic#"\t$R1",
1044            [(set cls:$R1, src)]> {
1045  let R2 = 0;
1046}
1047
1048class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
1049  : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
1050  let I2 = value;
1051  let M3 = 0;
1052}
1053
1054class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
1055  : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$I2),
1056           mnemonic##"\t$R1, $I2", []> {
1057  let isBranch = 1;
1058  let isTerminator = 1;
1059  let Constraints = "$R1 = $R1src";
1060  let DisableEncoding = "$R1src";
1061}
1062
1063class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
1064                     AddressingMode mode = bdaddr12only>
1065  : InstRS<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
1066           mnemonic#"\t$R1, $R3, $BD2", []> {
1067  let mayLoad = 1;
1068}
1069
1070class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
1071                      AddressingMode mode = bdaddr20only>
1072  : InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
1073            mnemonic#"\t$R1, $R3, $BD2", []> {
1074  let mayLoad = 1;
1075}
1076
1077multiclass LoadMultipleRSPair<string mnemonic, bits<8> rsOpcode,
1078                              bits<16> rsyOpcode, RegisterOperand cls> {
1079  let DispKey = mnemonic ## #cls in {
1080    let DispSize = "12" in
1081      def "" : LoadMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
1082    let DispSize = "20" in
1083      def Y  : LoadMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
1084  }
1085}
1086
1087class LoadMultipleVRSa<string mnemonic, bits<16> opcode>
1088  : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2),
1089             mnemonic#"\t$V1, $V3, $BD2", []> {
1090  let M4 = 0;
1091  let mayLoad = 1;
1092}
1093
1094class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1095                 RegisterOperand cls>
1096  : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
1097            mnemonic#"\t$R1, $I2",
1098            [(operator cls:$R1, pcrel32:$I2)]> {
1099  let mayStore = 1;
1100  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
1101  // However, BDXs have two extra operands and are therefore 6 units more
1102  // complex.
1103  let AddedComplexity = 7;
1104}
1105
1106class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1107              RegisterOperand cls, bits<5> bytes,
1108              AddressingMode mode = bdxaddr12only>
1109  : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1110           mnemonic#"\t$R1, $XBD2",
1111           [(operator cls:$R1, mode:$XBD2)]> {
1112  let OpKey = mnemonic ## cls;
1113  let OpType = "mem";
1114  let mayStore = 1;
1115  let AccessBytes = bytes;
1116}
1117
1118class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1119               RegisterOperand cls, bits<5> bytes,
1120               AddressingMode mode = bdxaddr20only>
1121  : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1122            mnemonic#"\t$R1, $XBD2",
1123            [(operator cls:$R1, mode:$XBD2)]> {
1124  let OpKey = mnemonic ## cls;
1125  let OpType = "mem";
1126  let mayStore = 1;
1127  let AccessBytes = bytes;
1128}
1129
1130multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1131                       SDPatternOperator operator, RegisterOperand cls,
1132                       bits<5> bytes> {
1133  let DispKey = mnemonic ## #cls in {
1134    let DispSize = "12" in
1135      def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
1136    let DispSize = "20" in
1137      def Y  : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
1138                        bdxaddr20pair>;
1139  }
1140}
1141
1142class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1143               TypedReg tr, bits<5> bytes, bits<4> type = 0>
1144  : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2),
1145            mnemonic#"\t$V1, $XBD2",
1146            [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
1147  let M3 = type;
1148  let mayStore = 1;
1149  let AccessBytes = bytes;
1150}
1151
1152class StoreLengthVRSb<string mnemonic, bits<16> opcode,
1153                      SDPatternOperator operator, bits<5> bytes>
1154  : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
1155             mnemonic#"\t$V1, $R3, $BD2",
1156             [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
1157  let M4 = 0;
1158  let mayStore = 1;
1159  let AccessBytes = bytes;
1160}
1161
1162class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
1163                      AddressingMode mode = bdaddr12only>
1164  : InstRS<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
1165           mnemonic#"\t$R1, $R3, $BD2", []> {
1166  let mayStore = 1;
1167}
1168
1169class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
1170                       AddressingMode mode = bdaddr20only>
1171  : InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
1172            mnemonic#"\t$R1, $R3, $BD2", []> {
1173  let mayStore = 1;
1174}
1175
1176multiclass StoreMultipleRSPair<string mnemonic, bits<8> rsOpcode,
1177                               bits<16> rsyOpcode, RegisterOperand cls> {
1178  let DispKey = mnemonic ## #cls in {
1179    let DispSize = "12" in
1180      def "" : StoreMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
1181    let DispSize = "20" in
1182      def Y  : StoreMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
1183  }
1184}
1185
1186class StoreMultipleVRSa<string mnemonic, bits<16> opcode>
1187  : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, bdaddr12only:$BD2),
1188             mnemonic#"\t$V1, $V3, $BD2", []> {
1189  let M4 = 0;
1190  let mayStore = 1;
1191}
1192
1193// StoreSI* instructions are used to store an integer to memory, but the
1194// addresses are more restricted than for normal stores.  If we are in the
1195// situation of having to force either the address into a register or the
1196// constant into a register, it's usually better to do the latter.
1197// We therefore match the address in the same way as a normal store and
1198// only use the StoreSI* instruction if the matched address is suitable.
1199class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1200              Immediate imm>
1201  : InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
1202           mnemonic#"\t$BD1, $I2",
1203           [(operator imm:$I2, mviaddr12pair:$BD1)]> {
1204  let mayStore = 1;
1205}
1206
1207class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1208               Immediate imm>
1209  : InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2),
1210            mnemonic#"\t$BD1, $I2",
1211            [(operator imm:$I2, mviaddr20pair:$BD1)]> {
1212  let mayStore = 1;
1213}
1214
1215class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1216               Immediate imm>
1217  : InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
1218            mnemonic#"\t$BD1, $I2",
1219            [(operator imm:$I2, mviaddr12pair:$BD1)]> {
1220  let mayStore = 1;
1221}
1222
1223multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
1224                       SDPatternOperator operator, Immediate imm> {
1225  let DispKey = mnemonic in {
1226    let DispSize = "12" in
1227      def "" : StoreSI<mnemonic, siOpcode, operator, imm>;
1228    let DispSize = "20" in
1229      def Y  : StoreSIY<mnemonic#"y", siyOpcode, operator, imm>;
1230  }
1231}
1232
1233class CondStoreRSY<string mnemonic, bits<16> opcode,
1234                   RegisterOperand cls, bits<5> bytes,
1235                   AddressingMode mode = bdaddr20only>
1236  : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$R3),
1237            mnemonic#"$R3\t$R1, $BD2", []>,
1238    Requires<[FeatureLoadStoreOnCond]> {
1239  let mayStore = 1;
1240  let AccessBytes = bytes;
1241  let CCMaskLast = 1;
1242}
1243
1244// Like CondStoreRSY, but used for the raw assembly form.  The condition-code
1245// mask is the third operand rather than being part of the mnemonic.
1246class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
1247                      RegisterOperand cls, bits<5> bytes,
1248                      AddressingMode mode = bdaddr20only>
1249  : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, imm32zx4:$R3),
1250            mnemonic#"\t$R1, $BD2, $R3", []>,
1251    Requires<[FeatureLoadStoreOnCond]> {
1252  let mayStore = 1;
1253  let AccessBytes = bytes;
1254}
1255
1256// Like CondStoreRSY, but with a fixed CC mask.
1257class FixedCondStoreRSY<string mnemonic, bits<16> opcode,
1258                        RegisterOperand cls, bits<4> ccmask, bits<5> bytes,
1259                        AddressingMode mode = bdaddr20only>
1260  : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2),
1261            mnemonic#"\t$R1, $BD2", []>,
1262    Requires<[FeatureLoadStoreOnCond]> {
1263  let mayStore = 1;
1264  let AccessBytes = bytes;
1265  let R3 = ccmask;
1266}
1267
1268class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1269              RegisterOperand cls1, RegisterOperand cls2>
1270  : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
1271           mnemonic#"r\t$R1, $R2",
1272           [(set cls1:$R1, (operator cls2:$R2))]> {
1273  let OpKey = mnemonic ## cls1;
1274  let OpType = "reg";
1275}
1276
1277class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1278               RegisterOperand cls1, RegisterOperand cls2>
1279  : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
1280            mnemonic#"r\t$R1, $R2",
1281            [(set cls1:$R1, (operator cls2:$R2))]> {
1282  let OpKey = mnemonic ## cls1;
1283  let OpType = "reg";
1284}
1285
1286class UnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1287               RegisterOperand cls2>
1288  : InstRRF<opcode, (outs cls1:$R1), (ins imm32zx4:$R3, cls2:$R2),
1289            mnemonic#"r\t$R1, $R3, $R2", []> {
1290  let OpKey = mnemonic ## cls1;
1291  let OpType = "reg";
1292  let R4 = 0;
1293}
1294
1295class UnaryRRF4<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1296                RegisterOperand cls2>
1297  : InstRRF<opcode, (outs cls1:$R1), (ins imm32zx4:$R3, cls2:$R2, imm32zx4:$R4),
1298            mnemonic#"\t$R1, $R3, $R2, $R4", []>;
1299
1300// These instructions are generated by if conversion.  The old value of R1
1301// is added as an implicit use.
1302class CondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1303                   RegisterOperand cls2>
1304  : InstRRF<opcode, (outs cls1:$R1), (ins cls2:$R2, cond4:$valid, cond4:$R3),
1305            mnemonic#"r$R3\t$R1, $R2", []>,
1306    Requires<[FeatureLoadStoreOnCond]> {
1307  let CCMaskLast = 1;
1308  let R4 = 0;
1309}
1310
1311class CondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1312                   Immediate imm>
1313  : InstRIEd<opcode, (outs cls:$R1),
1314                     (ins imm:$I2, cond4:$valid, cond4:$R3),
1315             mnemonic#"$R3\t$R1, $I2", []>,
1316    Requires<[FeatureLoadStoreOnCond2]> {
1317  let CCMaskLast = 1;
1318}
1319
1320// Like CondUnaryRRF, but used for the raw assembly form.  The condition-code
1321// mask is the third operand rather than being part of the mnemonic.
1322class AsmCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1323                      RegisterOperand cls2>
1324  : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2, imm32zx4:$R3),
1325            mnemonic#"r\t$R1, $R2, $R3", []>,
1326    Requires<[FeatureLoadStoreOnCond]> {
1327  let Constraints = "$R1 = $R1src";
1328  let DisableEncoding = "$R1src";
1329  let R4 = 0;
1330}
1331
1332class AsmCondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1333                   Immediate imm>
1334  : InstRIEd<opcode, (outs cls:$R1),
1335                     (ins cls:$R1src, imm:$I2, imm32zx4:$R3),
1336             mnemonic#"\t$R1, $I2, $R3", []>,
1337    Requires<[FeatureLoadStoreOnCond2]> {
1338  let Constraints = "$R1 = $R1src";
1339  let DisableEncoding = "$R1src";
1340}
1341
1342// Like CondUnaryRRF, but with a fixed CC mask.
1343class FixedCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1344                        RegisterOperand cls2, bits<4> ccmask>
1345  : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
1346            mnemonic#"\t$R1, $R2", []>,
1347    Requires<[FeatureLoadStoreOnCond]> {
1348  let Constraints = "$R1 = $R1src";
1349  let DisableEncoding = "$R1src";
1350  let R3 = ccmask;
1351  let R4 = 0;
1352}
1353
1354class FixedCondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1355                   Immediate imm, bits<4> ccmask>
1356  : InstRIEd<opcode, (outs cls:$R1),
1357                     (ins cls:$R1src, imm:$I2),
1358             mnemonic#"\t$R1, $I2", []>,
1359    Requires<[FeatureLoadStoreOnCond2]> {
1360  let Constraints = "$R1 = $R1src";
1361  let DisableEncoding = "$R1src";
1362  let R3 = ccmask;
1363}
1364
1365class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1366              RegisterOperand cls, Immediate imm>
1367  : InstRI<opcode, (outs cls:$R1), (ins imm:$I2),
1368           mnemonic#"\t$R1, $I2",
1369           [(set cls:$R1, (operator imm:$I2))]>;
1370
1371class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1372               RegisterOperand cls, Immediate imm>
1373  : InstRIL<opcode, (outs cls:$R1), (ins imm:$I2),
1374            mnemonic#"\t$R1, $I2",
1375            [(set cls:$R1, (operator imm:$I2))]>;
1376
1377class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1378                 RegisterOperand cls>
1379  : InstRIL<opcode, (outs cls:$R1), (ins pcrel32:$I2),
1380            mnemonic#"\t$R1, $I2",
1381            [(set cls:$R1, (operator pcrel32:$I2))]> {
1382  let mayLoad = 1;
1383  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
1384  // However, BDXs have two extra operands and are therefore 6 units more
1385  // complex.
1386  let AddedComplexity = 7;
1387}
1388
1389class CondUnaryRSY<string mnemonic, bits<16> opcode,
1390                   SDPatternOperator operator, RegisterOperand cls,
1391                   bits<5> bytes, AddressingMode mode = bdaddr20only>
1392  : InstRSY<opcode, (outs cls:$R1),
1393            (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3),
1394            mnemonic#"$R3\t$R1, $BD2",
1395            [(set cls:$R1,
1396                  (z_select_ccmask (load bdaddr20only:$BD2), cls:$R1src,
1397                                   cond4:$valid, cond4:$R3))]>,
1398    Requires<[FeatureLoadStoreOnCond]> {
1399  let Constraints = "$R1 = $R1src";
1400  let DisableEncoding = "$R1src";
1401  let mayLoad = 1;
1402  let AccessBytes = bytes;
1403  let CCMaskLast = 1;
1404}
1405
1406// Like CondUnaryRSY, but used for the raw assembly form.  The condition-code
1407// mask is the third operand rather than being part of the mnemonic.
1408class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
1409                      RegisterOperand cls, bits<5> bytes,
1410                      AddressingMode mode = bdaddr20only>
1411  : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, imm32zx4:$R3),
1412            mnemonic#"\t$R1, $BD2, $R3", []>,
1413    Requires<[FeatureLoadStoreOnCond]> {
1414  let mayLoad = 1;
1415  let AccessBytes = bytes;
1416  let Constraints = "$R1 = $R1src";
1417  let DisableEncoding = "$R1src";
1418}
1419
1420// Like CondUnaryRSY, but with a fixed CC mask.
1421class FixedCondUnaryRSY<string mnemonic, bits<16> opcode,
1422                        RegisterOperand cls, bits<4> ccmask, bits<5> bytes,
1423                        AddressingMode mode = bdaddr20only>
1424  : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
1425            mnemonic#"\t$R1, $BD2", []>,
1426    Requires<[FeatureLoadStoreOnCond]> {
1427  let Constraints = "$R1 = $R1src";
1428  let DisableEncoding = "$R1src";
1429  let R3 = ccmask;
1430  let mayLoad = 1;
1431  let AccessBytes = bytes;
1432}
1433
1434class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1435              RegisterOperand cls, bits<5> bytes,
1436              AddressingMode mode = bdxaddr12only>
1437  : InstRX<opcode, (outs cls:$R1), (ins mode:$XBD2),
1438           mnemonic#"\t$R1, $XBD2",
1439           [(set cls:$R1, (operator mode:$XBD2))]> {
1440  let OpKey = mnemonic ## cls;
1441  let OpType = "mem";
1442  let mayLoad = 1;
1443  let AccessBytes = bytes;
1444}
1445
1446class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1447               RegisterOperand cls, bits<5> bytes>
1448  : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
1449            mnemonic#"\t$R1, $XBD2",
1450            [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
1451  let OpKey = mnemonic ## cls;
1452  let OpType = "mem";
1453  let mayLoad = 1;
1454  let AccessBytes = bytes;
1455  let M3 = 0;
1456}
1457
1458class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1459               RegisterOperand cls, bits<5> bytes,
1460               AddressingMode mode = bdxaddr20only>
1461  : InstRXY<opcode, (outs cls:$R1), (ins mode:$XBD2),
1462            mnemonic#"\t$R1, $XBD2",
1463            [(set cls:$R1, (operator mode:$XBD2))]> {
1464  let OpKey = mnemonic ## cls;
1465  let OpType = "mem";
1466  let mayLoad = 1;
1467  let AccessBytes = bytes;
1468}
1469
1470multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1471                       SDPatternOperator operator, RegisterOperand cls,
1472                       bits<5> bytes> {
1473  let DispKey = mnemonic ## #cls in {
1474    let DispSize = "12" in
1475      def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
1476    let DispSize = "20" in
1477      def Y  : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
1478                        bdxaddr20pair>;
1479  }
1480}
1481
1482class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1483                TypedReg tr, Immediate imm, bits<4> type = 0>
1484  : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2),
1485             mnemonic#"\t$V1, $I2",
1486             [(set tr.op:$V1, (tr.vt (operator imm:$I2)))]> {
1487  let M3 = type;
1488}
1489
1490class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1491                TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0,
1492                bits<4> m5 = 0>
1493  : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
1494             mnemonic#"\t$V1, $V2",
1495             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]> {
1496  let M3 = type;
1497  let M4 = m4;
1498  let M5 = m5;
1499}
1500
1501multiclass UnaryVRRaSPair<string mnemonic, bits<16> opcode,
1502                          SDPatternOperator operator,
1503                          SDPatternOperator operator_cc, TypedReg tr1,
1504                          TypedReg tr2, bits<4> type, bits<4> modifier = 0,
1505                          bits<4> modifier_cc = 1> {
1506  def "" : UnaryVRRa<mnemonic, opcode, operator, tr1, tr2, type, 0, modifier>;
1507  let Defs = [CC] in
1508    def S : UnaryVRRa<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 0,
1509                      modifier_cc>;
1510}
1511
1512class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1513               TypedReg tr, bits<5> bytes, bits<4> type = 0>
1514  : InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2),
1515            mnemonic#"\t$V1, $XBD2",
1516            [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
1517  let M3 = type;
1518  let mayLoad = 1;
1519  let AccessBytes = bytes;
1520}
1521
1522class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1523               RegisterOperand cls1, RegisterOperand cls2>
1524  : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
1525           mnemonic#"r\t$R1, $R2",
1526           [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
1527  let OpKey = mnemonic ## cls1;
1528  let OpType = "reg";
1529  let Constraints = "$R1 = $R1src";
1530  let DisableEncoding = "$R1src";
1531}
1532
1533class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1534                RegisterOperand cls1, RegisterOperand cls2>
1535  : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
1536            mnemonic#"r\t$R1, $R2",
1537            [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
1538  let OpKey = mnemonic ## cls1;
1539  let OpType = "reg";
1540  let Constraints = "$R1 = $R1src";
1541  let DisableEncoding = "$R1src";
1542}
1543
1544class BinaryRRF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1545                RegisterOperand cls1, RegisterOperand cls2>
1546  : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R2, cls2:$R3),
1547            mnemonic#"r\t$R1, $R3, $R2",
1548            [(set cls1:$R1, (operator cls1:$R2, cls2:$R3))]> {
1549  let OpKey = mnemonic ## cls1;
1550  let OpType = "reg";
1551  let R4 = 0;
1552}
1553
1554class BinaryRRFK<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1555                 RegisterOperand cls1, RegisterOperand cls2>
1556  : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R2, cls2:$R3),
1557            mnemonic#"rk\t$R1, $R2, $R3",
1558            [(set cls1:$R1, (operator cls1:$R2, cls2:$R3))]> {
1559  let R4 = 0;
1560}
1561
1562multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
1563                        SDPatternOperator operator, RegisterOperand cls1,
1564                        RegisterOperand cls2> {
1565  let NumOpsKey = mnemonic in {
1566    let NumOpsValue = "3" in
1567      def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>,
1568              Requires<[FeatureDistinctOps]>;
1569    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1570      def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
1571  }
1572}
1573
1574multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
1575                         SDPatternOperator operator, RegisterOperand cls1,
1576                         RegisterOperand cls2> {
1577  let NumOpsKey = mnemonic in {
1578    let NumOpsValue = "3" in
1579      def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>,
1580              Requires<[FeatureDistinctOps]>;
1581    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1582      def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
1583  }
1584}
1585
1586class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1587               RegisterOperand cls, Immediate imm>
1588  : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
1589           mnemonic#"\t$R1, $I2",
1590           [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
1591  let Constraints = "$R1 = $R1src";
1592  let DisableEncoding = "$R1src";
1593}
1594
1595class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1596                RegisterOperand cls, Immediate imm>
1597  : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
1598             mnemonic#"\t$R1, $R3, $I2",
1599             [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
1600
1601multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
1602                        SDPatternOperator operator, RegisterOperand cls,
1603                        Immediate imm> {
1604  let NumOpsKey = mnemonic in {
1605    let NumOpsValue = "3" in
1606      def K : BinaryRIE<mnemonic##"k", opcode2, null_frag, cls, imm>,
1607              Requires<[FeatureDistinctOps]>;
1608    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1609      def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
1610  }
1611}
1612
1613class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1614                RegisterOperand cls, Immediate imm>
1615  : InstRIL<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
1616            mnemonic#"\t$R1, $I2",
1617            [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
1618  let Constraints = "$R1 = $R1src";
1619  let DisableEncoding = "$R1src";
1620}
1621
1622class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1623               RegisterOperand cls>
1624  : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
1625           mnemonic#"\t$R1, $BD2",
1626           [(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
1627  let R3 = 0;
1628  let Constraints = "$R1 = $R1src";
1629  let DisableEncoding = "$R1src";
1630}
1631
1632class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1633                RegisterOperand cls>
1634  : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
1635            mnemonic#"\t$R1, $R3, $BD2",
1636            [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
1637
1638multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
1639                        SDPatternOperator operator, RegisterOperand cls> {
1640  let NumOpsKey = mnemonic in {
1641    let NumOpsValue = "3" in
1642      def K  : BinaryRSY<mnemonic##"k", opcode2, null_frag, cls>,
1643               Requires<[FeatureDistinctOps]>;
1644    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1645      def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
1646  }
1647}
1648
1649class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1650               RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1651               AddressingMode mode = bdxaddr12only>
1652  : InstRX<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
1653           mnemonic#"\t$R1, $XBD2",
1654           [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
1655  let OpKey = mnemonic ## cls;
1656  let OpType = "mem";
1657  let Constraints = "$R1 = $R1src";
1658  let DisableEncoding = "$R1src";
1659  let mayLoad = 1;
1660  let AccessBytes = bytes;
1661}
1662
1663class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1664                  RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
1665  : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
1666            mnemonic#"\t$R1, $XBD2",
1667            [(set cls:$R1, (operator cls:$R1src,
1668                                     (load bdxaddr12only:$XBD2)))]> {
1669  let OpKey = mnemonic ## cls;
1670  let OpType = "mem";
1671  let Constraints = "$R1 = $R1src";
1672  let DisableEncoding = "$R1src";
1673  let mayLoad = 1;
1674  let AccessBytes = bytes;
1675  let M3 = 0;
1676}
1677
1678class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1679                RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1680                AddressingMode mode = bdxaddr20only>
1681  : InstRXY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
1682            mnemonic#"\t$R1, $XBD2",
1683            [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
1684  let OpKey = mnemonic ## cls;
1685  let OpType = "mem";
1686  let Constraints = "$R1 = $R1src";
1687  let DisableEncoding = "$R1src";
1688  let mayLoad = 1;
1689  let AccessBytes = bytes;
1690}
1691
1692multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1693                        SDPatternOperator operator, RegisterOperand cls,
1694                        SDPatternOperator load, bits<5> bytes> {
1695  let DispKey = mnemonic ## #cls in {
1696    let DispSize = "12" in
1697      def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
1698                        bdxaddr12pair>;
1699    let DispSize = "20" in
1700      def Y  : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes,
1701                         bdxaddr20pair>;
1702  }
1703}
1704
1705class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1706               Operand imm, AddressingMode mode = bdaddr12only>
1707  : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
1708           mnemonic#"\t$BD1, $I2",
1709           [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
1710  let mayLoad = 1;
1711  let mayStore = 1;
1712}
1713
1714class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1715                Operand imm, AddressingMode mode = bdaddr20only>
1716  : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
1717            mnemonic#"\t$BD1, $I2",
1718            [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
1719  let mayLoad = 1;
1720  let mayStore = 1;
1721}
1722
1723multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
1724                        bits<16> siyOpcode, SDPatternOperator operator,
1725                        Operand imm> {
1726  let DispKey = mnemonic ## #cls in {
1727    let DispSize = "12" in
1728      def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
1729    let DispSize = "20" in
1730      def Y  : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
1731  }
1732}
1733
1734class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1735                 TypedReg tr, bits<4> type>
1736  : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
1737             mnemonic#"\t$V1, $I2, $I3",
1738             [(set tr.op:$V1, (tr.vt (operator imm32zx8:$I2, imm32zx8:$I3)))]> {
1739  let M4 = type;
1740}
1741
1742class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1743                 TypedReg tr1, TypedReg tr2, bits<4> type>
1744  : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
1745             mnemonic#"\t$V1, $V3, $I2",
1746             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
1747                                                 imm32zx16:$I2)))]> {
1748  let M4 = type;
1749}
1750
1751class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1752                 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5>
1753  : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
1754             mnemonic#"\t$V1, $V2, $I3",
1755             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1756                                                 imm32zx12:$I3)))]> {
1757  let M4 = type;
1758  let M5 = m5;
1759}
1760
1761class BinaryVRRa<string mnemonic, bits<16> opcode>
1762  : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
1763             mnemonic#"\t$V1, $V2, $M3", []> {
1764  let M4 = 0;
1765  let M5 = 0;
1766}
1767
1768class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1769                 TypedReg tr1, TypedReg tr2, bits<4> type = 0,
1770                 bits<4> modifier = 0>
1771  : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
1772             mnemonic#"\t$V1, $V2, $V3",
1773             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1774                                                 (tr2.vt tr2.op:$V3))))]> {
1775  let M4 = type;
1776  let M5 = modifier;
1777}
1778
1779// Declare a pair of instructions, one which sets CC and one which doesn't.
1780// The CC-setting form ends with "S" and sets the low bit of M5.
1781multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode,
1782                           SDPatternOperator operator,
1783                           SDPatternOperator operator_cc, TypedReg tr1,
1784                           TypedReg tr2, bits<4> type,
1785                           bits<4> modifier = 0, bits<4> modifier_cc = 1> {
1786  def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type, modifier>;
1787  let Defs = [CC] in
1788    def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
1789                       modifier_cc>;
1790}
1791
1792class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1793                 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0,
1794                 bits<4> m6 = 0>
1795  : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
1796             mnemonic#"\t$V1, $V2, $V3",
1797             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1798                                                 (tr2.vt tr2.op:$V3))))]> {
1799  let M4 = type;
1800  let M5 = m5;
1801  let M6 = m6;
1802}
1803
1804multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode,
1805                           SDPatternOperator operator,
1806                           SDPatternOperator operator_cc, TypedReg tr1,
1807                           TypedReg tr2, bits<4> type, bits<4> m5,
1808                           bits<4> modifier = 0, bits<4> modifier_cc = 1> {
1809  def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type, m5, modifier>;
1810  let Defs = [CC] in
1811    def S : BinaryVRRc<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
1812                       m5, modifier_cc>;
1813}
1814
1815class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1816                 TypedReg tr>
1817  : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3),
1818             mnemonic#"\t$V1, $R2, $R3",
1819             [(set tr.op:$V1, (tr.vt (operator GR64:$R2, GR64:$R3)))]>;
1820
1821class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1822                 TypedReg tr1, TypedReg tr2, bits<4> type>
1823  : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
1824             mnemonic#"\t$V1, $V3, $BD2",
1825             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
1826                                                 shift12only:$BD2)))]> {
1827  let M4 = type;
1828}
1829
1830class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1831                 bits<5> bytes>
1832  : InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
1833             mnemonic#"\t$V1, $R3, $BD2",
1834             [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
1835  let M4 = 0;
1836  let mayLoad = 1;
1837  let AccessBytes = bytes;
1838}
1839
1840class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1841                 TypedReg tr, bits<4> type>
1842  : InstVRSc<opcode, (outs GR64:$R1), (ins tr.op:$V3, shift12only:$BD2),
1843           mnemonic#"\t$R1, $V3, $BD2",
1844           [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> {
1845  let M4 = type;
1846}
1847
1848class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1849                TypedReg tr, bits<5> bytes>
1850  : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
1851            mnemonic#"\t$V1, $XBD2, $M3",
1852            [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2,
1853                                              imm32zx4:$M3)))]> {
1854  let mayLoad = 1;
1855  let AccessBytes = bytes;
1856}
1857
1858class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
1859                     Immediate index>
1860  : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3),
1861            mnemonic#"\t$V1, $VBD2, $M3", []> {
1862  let mayStore = 1;
1863  let AccessBytes = bytes;
1864}
1865
1866class StoreBinaryVRX<string mnemonic, bits<16> opcode,
1867                     SDPatternOperator operator, TypedReg tr, bits<5> bytes,
1868                     Immediate index>
1869  : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3),
1870            mnemonic#"\t$V1, $XBD2, $M3",
1871            [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> {
1872  let mayStore = 1;
1873  let AccessBytes = bytes;
1874}
1875
1876class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1877                RegisterOperand cls1, RegisterOperand cls2>
1878  : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
1879           mnemonic#"r\t$R1, $R2",
1880           [(operator cls1:$R1, cls2:$R2)]> {
1881  let OpKey = mnemonic ## cls1;
1882  let OpType = "reg";
1883  let isCompare = 1;
1884}
1885
1886class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1887                 RegisterOperand cls1, RegisterOperand cls2>
1888  : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
1889            mnemonic#"r\t$R1, $R2",
1890            [(operator cls1:$R1, cls2:$R2)]> {
1891  let OpKey = mnemonic ## cls1;
1892  let OpType = "reg";
1893  let isCompare = 1;
1894}
1895
1896class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1897                RegisterOperand cls, Immediate imm>
1898  : InstRI<opcode, (outs), (ins cls:$R1, imm:$I2),
1899           mnemonic#"\t$R1, $I2",
1900           [(operator cls:$R1, imm:$I2)]> {
1901  let isCompare = 1;
1902}
1903
1904class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1905                 RegisterOperand cls, Immediate imm>
1906  : InstRIL<opcode, (outs), (ins cls:$R1, imm:$I2),
1907            mnemonic#"\t$R1, $I2",
1908            [(operator cls:$R1, imm:$I2)]> {
1909  let isCompare = 1;
1910}
1911
1912class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1913                   RegisterOperand cls, SDPatternOperator load>
1914  : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
1915            mnemonic#"\t$R1, $I2",
1916            [(operator cls:$R1, (load pcrel32:$I2))]> {
1917  let isCompare = 1;
1918  let mayLoad = 1;
1919  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
1920  // However, BDXs have two extra operands and are therefore 6 units more
1921  // complex.
1922  let AddedComplexity = 7;
1923}
1924
1925class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1926                RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1927                AddressingMode mode = bdxaddr12only>
1928  : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1929           mnemonic#"\t$R1, $XBD2",
1930           [(operator cls:$R1, (load mode:$XBD2))]> {
1931  let OpKey = mnemonic ## cls;
1932  let OpType = "mem";
1933  let isCompare = 1;
1934  let mayLoad = 1;
1935  let AccessBytes = bytes;
1936}
1937
1938class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1939                 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
1940  : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
1941            mnemonic#"\t$R1, $XBD2",
1942            [(operator cls:$R1, (load bdxaddr12only:$XBD2))]> {
1943  let OpKey = mnemonic ## cls;
1944  let OpType = "mem";
1945  let isCompare = 1;
1946  let mayLoad = 1;
1947  let AccessBytes = bytes;
1948  let M3 = 0;
1949}
1950
1951class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1952                 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1953                 AddressingMode mode = bdxaddr20only>
1954  : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1955            mnemonic#"\t$R1, $XBD2",
1956            [(operator cls:$R1, (load mode:$XBD2))]> {
1957  let OpKey = mnemonic ## cls;
1958  let OpType = "mem";
1959  let isCompare = 1;
1960  let mayLoad = 1;
1961  let AccessBytes = bytes;
1962}
1963
1964multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1965                         SDPatternOperator operator, RegisterOperand cls,
1966                         SDPatternOperator load, bits<5> bytes> {
1967  let DispKey = mnemonic ## #cls in {
1968    let DispSize = "12" in
1969      def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
1970                         load, bytes, bdxaddr12pair>;
1971    let DispSize = "20" in
1972      def Y  : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
1973                          load, bytes, bdxaddr20pair>;
1974  }
1975}
1976
1977class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1978                SDPatternOperator load, Immediate imm,
1979                AddressingMode mode = bdaddr12only>
1980  : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
1981           mnemonic#"\t$BD1, $I2",
1982           [(operator (load mode:$BD1), imm:$I2)]> {
1983  let isCompare = 1;
1984  let mayLoad = 1;
1985}
1986
1987class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1988                 SDPatternOperator load, Immediate imm>
1989  : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
1990            mnemonic#"\t$BD1, $I2",
1991            [(operator (load bdaddr12only:$BD1), imm:$I2)]> {
1992  let isCompare = 1;
1993  let mayLoad = 1;
1994}
1995
1996class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1997                 SDPatternOperator load, Immediate imm,
1998                 AddressingMode mode = bdaddr20only>
1999  : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
2000            mnemonic#"\t$BD1, $I2",
2001            [(operator (load mode:$BD1), imm:$I2)]> {
2002  let isCompare = 1;
2003  let mayLoad = 1;
2004}
2005
2006multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
2007                         SDPatternOperator operator, SDPatternOperator load,
2008                         Immediate imm> {
2009  let DispKey = mnemonic in {
2010    let DispSize = "12" in
2011      def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>;
2012    let DispSize = "20" in
2013      def Y  : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm,
2014                          bdaddr20pair>;
2015  }
2016}
2017
2018class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2019                  TypedReg tr, bits<4> type>
2020  : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2),
2021             mnemonic#"\t$V1, $V2",
2022             [(operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2))]> {
2023  let isCompare = 1;
2024  let M3 = type;
2025  let M4 = 0;
2026  let M5 = 0;
2027}
2028
2029class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2030              RegisterOperand cls>
2031  : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
2032            mnemonic#"\t$R1, $XBD2",
2033            [(operator cls:$R1, bdxaddr12only:$XBD2)]> {
2034  let M3 = 0;
2035}
2036
2037class TernaryRRD<string mnemonic, bits<16> opcode,
2038                 SDPatternOperator operator, RegisterOperand cls>
2039  : InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2),
2040            mnemonic#"r\t$R1, $R3, $R2",
2041            [(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> {
2042  let OpKey = mnemonic ## cls;
2043  let OpType = "reg";
2044  let Constraints = "$R1 = $R1src";
2045  let DisableEncoding = "$R1src";
2046}
2047
2048class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2049                bits<5> bytes, AddressingMode mode = bdaddr12only>
2050  : InstRS<opcode, (outs cls:$R1),
2051          (ins cls:$R1src, imm32zx4:$R3, mode:$BD2),
2052           mnemonic#"\t$R1, $R3, $BD2", []> {
2053
2054  let Constraints = "$R1 = $R1src";
2055  let DisableEncoding = "$R1src";
2056  let mayLoad = 1;
2057  let AccessBytes = bytes;
2058}
2059
2060class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2061                bits<5> bytes, AddressingMode mode = bdaddr20only>
2062  : InstRSY<opcode, (outs cls:$R1),
2063           (ins cls:$R1src, imm32zx4:$R3, mode:$BD2),
2064            mnemonic#"\t$R1, $R3, $BD2", []> {
2065
2066  let Constraints = "$R1 = $R1src";
2067  let DisableEncoding = "$R1src";
2068  let mayLoad = 1;
2069  let AccessBytes = bytes;
2070}
2071
2072multiclass TernaryRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
2073                         RegisterOperand cls, bits<5> bytes> {
2074  let DispKey = mnemonic ## #cls in {
2075    let DispSize = "12" in
2076      def "" : TernaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
2077    let DispSize = "20" in
2078      def Y  : TernaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
2079  }
2080}
2081
2082class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2083                 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
2084  : InstRXF<opcode, (outs cls:$R1),
2085            (ins cls:$R1src, cls:$R3, bdxaddr12only:$XBD2),
2086            mnemonic#"\t$R1, $R3, $XBD2",
2087            [(set cls:$R1, (operator cls:$R1src, cls:$R3,
2088                                     (load bdxaddr12only:$XBD2)))]> {
2089  let OpKey = mnemonic ## cls;
2090  let OpType = "mem";
2091  let Constraints = "$R1 = $R1src";
2092  let DisableEncoding = "$R1src";
2093  let mayLoad = 1;
2094  let AccessBytes = bytes;
2095}
2096
2097class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2098                  TypedReg tr1, TypedReg tr2, Immediate imm, Immediate index>
2099  : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
2100             mnemonic#"\t$V1, $I2, $M3",
2101             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2102                                                 imm:$I2, index:$M3)))]> {
2103  let Constraints = "$V1 = $V1src";
2104  let DisableEncoding = "$V1src";
2105}
2106
2107class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2108                  TypedReg tr1, TypedReg tr2, bits<4> type>
2109  : InstVRId<opcode, (outs tr1.op:$V1),
2110             (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
2111             mnemonic#"\t$V1, $V2, $V3, $I4",
2112             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2113                                                 (tr2.vt tr2.op:$V3),
2114                                                 imm32zx8:$I4)))]> {
2115  let M5 = type;
2116}
2117
2118class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2119                  TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or>
2120  : InstVRRa<opcode, (outs tr1.op:$V1),
2121             (ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5),
2122             mnemonic#"\t$V1, $V2, $M4, $M5",
2123             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2124                                                 imm32zx4:$M4,
2125                                                 imm32zx4:$M5)))],
2126             m4or> {
2127  let M3 = type;
2128}
2129
2130class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2131                  TypedReg tr1, TypedReg tr2, bits<4> type,
2132                  SDPatternOperator m5mask, bits<4> m5or>
2133  : InstVRRb<opcode, (outs tr1.op:$V1),
2134             (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5),
2135             mnemonic#"\t$V1, $V2, $V3, $M5",
2136             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2137                                                 (tr2.vt tr2.op:$V3),
2138                                                 m5mask:$M5)))],
2139             m5or> {
2140  let M4 = type;
2141}
2142
2143multiclass TernaryVRRbSPair<string mnemonic, bits<16> opcode,
2144                            SDPatternOperator operator,
2145                            SDPatternOperator operator_cc, TypedReg tr1,
2146                            TypedReg tr2, bits<4> type, bits<4> m5or> {
2147  def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
2148                       imm32zx4even, !and (m5or, 14)>;
2149  def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
2150                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
2151                                            tr2.op:$V3, 0)>;
2152  let Defs = [CC] in
2153    def S : TernaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
2154                        imm32zx4even, !add(!and (m5or, 14), 1)>;
2155  def : InstAlias<mnemonic#"s\t$V1, $V2, $V3",
2156                  (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
2157                                                tr2.op:$V3, 0)>;
2158}
2159
2160class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2161                  TypedReg tr1, TypedReg tr2>
2162  : InstVRRc<opcode, (outs tr1.op:$V1),
2163             (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4),
2164             mnemonic#"\t$V1, $V2, $V3, $M4",
2165             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2166                                                 (tr2.vt tr2.op:$V3),
2167                                                 imm32zx4:$M4)))]> {
2168  let M5 = 0;
2169  let M6 = 0;
2170}
2171
2172class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2173                  TypedReg tr1, TypedReg tr2, bits<4> type = 0>
2174  : InstVRRd<opcode, (outs tr1.op:$V1),
2175             (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
2176             mnemonic#"\t$V1, $V2, $V3, $V4",
2177             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2178                                                 (tr2.vt tr2.op:$V3),
2179                                                 (tr1.vt tr1.op:$V4))))]> {
2180  let M5 = type;
2181  let M6 = 0;
2182}
2183
2184class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2185                  TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0>
2186  : InstVRRe<opcode, (outs tr1.op:$V1),
2187             (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
2188             mnemonic#"\t$V1, $V2, $V3, $V4",
2189             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2190                                                 (tr2.vt tr2.op:$V3),
2191                                                 (tr1.vt tr1.op:$V4))))]> {
2192  let M5 = m5;
2193  let M6 = type;
2194}
2195
2196class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2197                  TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type>
2198  : InstVRSb<opcode, (outs tr1.op:$V1),
2199             (ins tr2.op:$V1src, cls:$R3, shift12only:$BD2),
2200             mnemonic#"\t$V1, $R3, $BD2",
2201             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2202                                                 cls:$R3,
2203                                                 shift12only:$BD2)))]> {
2204  let Constraints = "$V1 = $V1src";
2205  let DisableEncoding = "$V1src";
2206  let M4 = type;
2207}
2208
2209class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
2210                 Immediate index>
2211  : InstVRV<opcode, (outs VR128:$V1),
2212           (ins VR128:$V1src, bdvaddr12only:$VBD2, index:$M3),
2213           mnemonic#"\t$V1, $VBD2, $M3", []> {
2214  let Constraints = "$V1 = $V1src";
2215  let DisableEncoding = "$V1src";
2216  let mayLoad = 1;
2217  let AccessBytes = bytes;
2218}
2219
2220class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2221                 TypedReg tr1, TypedReg tr2, bits<5> bytes, Immediate index>
2222  : InstVRX<opcode, (outs tr1.op:$V1),
2223           (ins tr2.op:$V1src, bdxaddr12only:$XBD2, index:$M3),
2224           mnemonic#"\t$V1, $XBD2, $M3",
2225           [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2226                                               bdxaddr12only:$XBD2,
2227                                               index:$M3)))]> {
2228  let Constraints = "$V1 = $V1src";
2229  let DisableEncoding = "$V1src";
2230  let mayLoad = 1;
2231  let AccessBytes = bytes;
2232}
2233
2234class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2235                     TypedReg tr1, TypedReg tr2, bits<4> type>
2236  : InstVRId<opcode, (outs tr1.op:$V1),
2237             (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
2238             mnemonic#"\t$V1, $V2, $V3, $I4",
2239             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2240                                                 (tr2.vt tr2.op:$V2),
2241                                                 (tr2.vt tr2.op:$V3),
2242                                                 imm32zx8:$I4)))]> {
2243  let Constraints = "$V1 = $V1src";
2244  let DisableEncoding = "$V1src";
2245  let M5 = type;
2246}
2247
2248class QuaternaryVRRd<string mnemonic, bits<16> opcode,
2249                     SDPatternOperator operator, TypedReg tr1, TypedReg tr2,
2250                     bits<4> type, SDPatternOperator m6mask, bits<4> m6or>
2251  : InstVRRd<opcode, (outs tr1.op:$V1),
2252             (ins tr2.op:$V2, tr2.op:$V3, tr2.op:$V4, m6mask:$M6),
2253             mnemonic#"\t$V1, $V2, $V3, $V4, $M6",
2254             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2255                                                 (tr2.vt tr2.op:$V3),
2256                                                 (tr2.vt tr2.op:$V4),
2257                                                 m6mask:$M6)))],
2258             m6or> {
2259  let M5 = type;
2260}
2261
2262multiclass QuaternaryVRRdSPair<string mnemonic, bits<16> opcode,
2263                               SDPatternOperator operator,
2264                               SDPatternOperator operator_cc, TypedReg tr1,
2265                               TypedReg tr2, bits<4> type, bits<4> m6or> {
2266  def "" : QuaternaryVRRd<mnemonic, opcode, operator, tr1, tr2, type,
2267                          imm32zx4even, !and (m6or, 14)>;
2268  def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
2269                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
2270                                            tr2.op:$V3, tr2.op:$V4, 0)>;
2271  let Defs = [CC] in
2272    def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
2273                           imm32zx4even, !add (!and (m6or, 14), 1)>;
2274  def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
2275                  (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
2276                                                tr2.op:$V3, tr2.op:$V4, 0)>;
2277}
2278
2279class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2280                  RegisterOperand cls, AddressingMode mode = bdaddr20only>
2281  : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
2282            mnemonic#"\t$R1, $R3, $BD2",
2283            [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
2284  let mayLoad = 1;
2285  let mayStore = 1;
2286}
2287
2288class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2289                RegisterOperand cls, AddressingMode mode = bdaddr12only>
2290  : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
2291           mnemonic#"\t$R1, $R3, $BD2",
2292           [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
2293  let Constraints = "$R1 = $R1src";
2294  let DisableEncoding = "$R1src";
2295  let mayLoad = 1;
2296  let mayStore = 1;
2297}
2298
2299class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2300                 RegisterOperand cls, AddressingMode mode = bdaddr20only>
2301  : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
2302            mnemonic#"\t$R1, $R3, $BD2",
2303            [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
2304  let Constraints = "$R1 = $R1src";
2305  let DisableEncoding = "$R1src";
2306  let mayLoad = 1;
2307  let mayStore = 1;
2308}
2309
2310multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
2311                         SDPatternOperator operator, RegisterOperand cls> {
2312  let DispKey = mnemonic ## #cls in {
2313    let DispSize = "12" in
2314      def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
2315    let DispSize = "20" in
2316      def Y  : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
2317  }
2318}
2319
2320class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
2321                       RegisterOperand cls2>
2322  : InstRIEf<opcode, (outs cls1:$R1),
2323             (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
2324                  imm32zx6:$I5),
2325             mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
2326  let Constraints = "$R1 = $R1src";
2327  let DisableEncoding = "$R1src";
2328}
2329
2330class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
2331  : InstRXY<opcode, (outs), (ins imm32zx4:$R1, bdxaddr20only:$XBD2),
2332            mnemonic##"\t$R1, $XBD2",
2333            [(operator imm32zx4:$R1, bdxaddr20only:$XBD2)]>;
2334
2335class PrefetchRILPC<string mnemonic, bits<12> opcode,
2336                    SDPatternOperator operator>
2337  : InstRIL<opcode, (outs), (ins imm32zx4:$R1, pcrel32:$I2),
2338            mnemonic##"\t$R1, $I2",
2339            [(operator imm32zx4:$R1, pcrel32:$I2)]> {
2340  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2341  // However, BDXs have two extra operands and are therefore 6 units more
2342  // complex.
2343  let AddedComplexity = 7;
2344}
2345
2346// A floating-point load-and test operation.  Create both a normal unary
2347// operation and one that acts as a comparison against zero.
2348// Note that the comparison against zero operation is not available if we
2349// have vector support, since load-and-test instructions will partially
2350// clobber the target (vector) register.
2351multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode,
2352                          RegisterOperand cls> {
2353  def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>;
2354  let isCodeGenOnly = 1, Predicates = [FeatureNoVector] in
2355    def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>;
2356}
2357
2358//===----------------------------------------------------------------------===//
2359// Pseudo instructions
2360//===----------------------------------------------------------------------===//
2361//
2362// Convenience instructions that get lowered to real instructions
2363// by either SystemZTargetLowering::EmitInstrWithCustomInserter()
2364// or SystemZInstrInfo::expandPostRAPseudo().
2365//
2366//===----------------------------------------------------------------------===//
2367
2368class Pseudo<dag outs, dag ins, list<dag> pattern>
2369  : InstSystemZ<0, outs, ins, "", pattern> {
2370  let isPseudo = 1;
2371  let isCodeGenOnly = 1;
2372}
2373
2374// Like UnaryRI, but expanded after RA depending on the choice of register.
2375class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
2376                    Immediate imm>
2377  : Pseudo<(outs cls:$R1), (ins imm:$I2),
2378           [(set cls:$R1, (operator imm:$I2))]>;
2379
2380// Like UnaryRXY, but expanded after RA depending on the choice of register.
2381class UnaryRXYPseudo<string key, SDPatternOperator operator,
2382                     RegisterOperand cls, bits<5> bytes,
2383                     AddressingMode mode = bdxaddr20only>
2384  : Pseudo<(outs cls:$R1), (ins mode:$XBD2),
2385           [(set cls:$R1, (operator mode:$XBD2))]> {
2386  let OpKey = key ## cls;
2387  let OpType = "mem";
2388  let mayLoad = 1;
2389  let Has20BitOffset = 1;
2390  let HasIndex = 1;
2391  let AccessBytes = bytes;
2392}
2393
2394// Like UnaryRR, but expanded after RA depending on the choice of registers.
2395class UnaryRRPseudo<string key, SDPatternOperator operator,
2396                    RegisterOperand cls1, RegisterOperand cls2>
2397  : Pseudo<(outs cls1:$R1), (ins cls2:$R2),
2398           [(set cls1:$R1, (operator cls2:$R2))]> {
2399  let OpKey = key ## cls1;
2400  let OpType = "reg";
2401}
2402
2403// Like BinaryRI, but expanded after RA depending on the choice of register.
2404class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
2405                     Immediate imm>
2406  : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2),
2407           [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2408  let Constraints = "$R1 = $R1src";
2409}
2410
2411// Like BinaryRIE, but expanded after RA depending on the choice of register.
2412class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls,
2413                      Immediate imm>
2414  : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
2415           [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
2416
2417// Like BinaryRIAndK, but expanded after RA depending on the choice of register.
2418multiclass BinaryRIAndKPseudo<string key, SDPatternOperator operator,
2419                              RegisterOperand cls, Immediate imm> {
2420  let NumOpsKey = key in {
2421    let NumOpsValue = "3" in
2422      def K : BinaryRIEPseudo<null_frag, cls, imm>,
2423              Requires<[FeatureHighWord, FeatureDistinctOps]>;
2424    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
2425      def "" : BinaryRIPseudo<operator, cls, imm>,
2426               Requires<[FeatureHighWord]>;
2427  }
2428}
2429
2430// Like CompareRI, but expanded after RA depending on the choice of register.
2431class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
2432                      Immediate imm>
2433  : Pseudo<(outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]>;
2434
2435// Like CompareRXY, but expanded after RA depending on the choice of register.
2436class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
2437                       SDPatternOperator load, bits<5> bytes,
2438                       AddressingMode mode = bdxaddr20only>
2439  : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
2440           [(operator cls:$R1, (load mode:$XBD2))]> {
2441  let mayLoad = 1;
2442  let Has20BitOffset = 1;
2443  let HasIndex = 1;
2444  let AccessBytes = bytes;
2445}
2446
2447// Like StoreRXY, but expanded after RA depending on the choice of register.
2448class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
2449                     bits<5> bytes, AddressingMode mode = bdxaddr20only>
2450  : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
2451           [(operator cls:$R1, mode:$XBD2)]> {
2452  let mayStore = 1;
2453  let Has20BitOffset = 1;
2454  let HasIndex = 1;
2455  let AccessBytes = bytes;
2456}
2457
2458// Like RotateSelectRIEf, but expanded after RA depending on the choice
2459// of registers.
2460class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2>
2461  : Pseudo<(outs cls1:$R1),
2462           (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
2463                imm32zx6:$I5),
2464           []> {
2465  let Constraints = "$R1 = $R1src";
2466  let DisableEncoding = "$R1src";
2467}
2468
2469// Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
2470// the value of the PSW's 2-bit condition code field.
2471class SelectWrapper<RegisterOperand cls>
2472  : Pseudo<(outs cls:$dst),
2473           (ins cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc),
2474           [(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2,
2475                                            imm32zx4:$valid, imm32zx4:$cc))]> {
2476  let usesCustomInserter = 1;
2477  // Although the instructions used by these nodes do not in themselves
2478  // change CC, the insertion requires new blocks, and CC cannot be live
2479  // across them.
2480  let Defs = [CC];
2481  let Uses = [CC];
2482}
2483
2484// Stores $new to $addr if $cc is true ("" case) or false (Inv case).
2485multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
2486                      SDPatternOperator load, AddressingMode mode> {
2487  let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in {
2488    def "" : Pseudo<(outs),
2489                    (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
2490                    [(store (z_select_ccmask cls:$new, (load mode:$addr),
2491                                             imm32zx4:$valid, imm32zx4:$cc),
2492                            mode:$addr)]>;
2493    def Inv : Pseudo<(outs),
2494                     (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
2495                     [(store (z_select_ccmask (load mode:$addr), cls:$new,
2496                                              imm32zx4:$valid, imm32zx4:$cc),
2497                              mode:$addr)]>;
2498  }
2499}
2500
2501// OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation.  PAT and OPERAND
2502// describe the second (non-memory) operand.
2503class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls,
2504                       dag pat, DAGOperand operand>
2505  : Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2),
2506           [(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> {
2507  let Defs = [CC];
2508  let Has20BitOffset = 1;
2509  let mayLoad = 1;
2510  let mayStore = 1;
2511  let usesCustomInserter = 1;
2512}
2513
2514// Specializations of AtomicLoadWBinary.
2515class AtomicLoadBinaryReg32<SDPatternOperator operator>
2516  : AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>;
2517class AtomicLoadBinaryImm32<SDPatternOperator operator, Immediate imm>
2518  : AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>;
2519class AtomicLoadBinaryReg64<SDPatternOperator operator>
2520  : AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>;
2521class AtomicLoadBinaryImm64<SDPatternOperator operator, Immediate imm>
2522  : AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>;
2523
2524// OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation.  PAT and OPERAND
2525// describe the second (non-memory) operand.
2526class AtomicLoadWBinary<SDPatternOperator operator, dag pat,
2527                        DAGOperand operand>
2528  : Pseudo<(outs GR32:$dst),
2529           (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift,
2530                ADDR32:$negbitshift, uimm32:$bitsize),
2531           [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift,
2532                                      ADDR32:$negbitshift, uimm32:$bitsize))]> {
2533  let Defs = [CC];
2534  let Has20BitOffset = 1;
2535  let mayLoad = 1;
2536  let mayStore = 1;
2537  let usesCustomInserter = 1;
2538}
2539
2540// Specializations of AtomicLoadWBinary.
2541class AtomicLoadWBinaryReg<SDPatternOperator operator>
2542  : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>;
2543class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm>
2544  : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>;
2545
2546// Define an instruction that operates on two fixed-length blocks of memory,
2547// and associated pseudo instructions for operating on blocks of any size.
2548// The Sequence form uses a straight-line sequence of instructions and
2549// the Loop form uses a loop of length-256 instructions followed by
2550// another instruction to handle the excess.
2551multiclass MemorySS<string mnemonic, bits<8> opcode,
2552                    SDPatternOperator sequence, SDPatternOperator loop> {
2553  def "" : InstSS<opcode, (outs), (ins bdladdr12onlylen8:$BDL1,
2554                                       bdaddr12only:$BD2),
2555                  mnemonic##"\t$BDL1, $BD2", []>;
2556  let usesCustomInserter = 1 in {
2557    def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
2558                                       imm64:$length),
2559                           [(sequence bdaddr12only:$dest, bdaddr12only:$src,
2560                                      imm64:$length)]>;
2561    def Loop : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
2562                                   imm64:$length, GR64:$count256),
2563                      [(loop bdaddr12only:$dest, bdaddr12only:$src,
2564                             imm64:$length, GR64:$count256)]>;
2565  }
2566}
2567
2568// Define an instruction that operates on two strings, both terminated
2569// by the character in R0.  The instruction processes a CPU-determinated
2570// number of bytes at a time and sets CC to 3 if the instruction needs
2571// to be repeated.  Also define a pseudo instruction that represents
2572// the full loop (the main instruction plus the branch on CC==3).
2573multiclass StringRRE<string mnemonic, bits<16> opcode,
2574                     SDPatternOperator operator> {
2575  def "" : InstRRE<opcode, (outs GR64:$R1, GR64:$R2),
2576                   (ins GR64:$R1src, GR64:$R2src),
2577                   mnemonic#"\t$R1, $R2", []> {
2578    let Uses = [R0L];
2579    let Constraints = "$R1 = $R1src, $R2 = $R2src";
2580    let DisableEncoding = "$R1src, $R2src";
2581  }
2582  let usesCustomInserter = 1 in
2583    def Loop : Pseudo<(outs GR64:$end),
2584                      (ins GR64:$start1, GR64:$start2, GR32:$char),
2585                      [(set GR64:$end, (operator GR64:$start1, GR64:$start2,
2586                                                 GR32:$char))]>;
2587}
2588
2589// A pseudo instruction that is a direct alias of a real instruction.
2590// These aliases are used in cases where a particular register operand is
2591// fixed or where the same instruction is used with different register sizes.
2592// The size parameter is the size in bytes of the associated real instruction.
2593class Alias<int size, dag outs, dag ins, list<dag> pattern>
2594  : InstSystemZ<size, outs, ins, "", pattern> {
2595  let isPseudo = 1;
2596  let isCodeGenOnly = 1;
2597}
2598
2599class UnaryAliasVRS<RegisterOperand cls1, RegisterOperand cls2>
2600 : Alias<6, (outs cls1:$src1), (ins cls2:$src2), []>;
2601
2602// An alias of a UnaryVRR*, but with different register sizes.
2603class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2>
2604  : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2),
2605          [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]>;
2606
2607// An alias of a UnaryVRX, but with different register sizes.
2608class UnaryAliasVRX<SDPatternOperator operator, TypedReg tr,
2609                    AddressingMode mode = bdxaddr12only>
2610  : Alias<6, (outs tr.op:$V1), (ins mode:$XBD2),
2611          [(set tr.op:$V1, (tr.vt (operator mode:$XBD2)))]>;
2612
2613// An alias of a StoreVRX, but with different register sizes.
2614class StoreAliasVRX<SDPatternOperator operator, TypedReg tr,
2615                    AddressingMode mode = bdxaddr12only>
2616  : Alias<6, (outs), (ins tr.op:$V1, mode:$XBD2),
2617          [(operator (tr.vt tr.op:$V1), mode:$XBD2)]>;
2618
2619// An alias of a BinaryRI, but with different register sizes.
2620class BinaryAliasRI<SDPatternOperator operator, RegisterOperand cls,
2621                    Immediate imm>
2622  : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
2623          [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2624  let Constraints = "$R1 = $R1src";
2625}
2626
2627// An alias of a BinaryRIL, but with different register sizes.
2628class BinaryAliasRIL<SDPatternOperator operator, RegisterOperand cls,
2629                     Immediate imm>
2630  : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
2631          [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2632  let Constraints = "$R1 = $R1src";
2633}
2634
2635// An alias of a BinaryVRRf, but with different register sizes.
2636class BinaryAliasVRRf<RegisterOperand cls>
2637  : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>;
2638
2639// An alias of a CompareRI, but with different register sizes.
2640class CompareAliasRI<SDPatternOperator operator, RegisterOperand cls,
2641                     Immediate imm>
2642  : Alias<4, (outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]> {
2643  let isCompare = 1;
2644}
2645
2646// An alias of a RotateSelectRIEf, but with different register sizes.
2647class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2>
2648  : Alias<6, (outs cls1:$R1),
2649          (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
2650               imm32zx6:$I5), []> {
2651  let Constraints = "$R1 = $R1src";
2652}
2653