1; RUN: llc -O0 -fast-isel-abort=1 -mtriple=arm64-apple-darwin -mcpu=cyclone -verify-machineinstrs < %s | FileCheck %s
2
3define void @branch1() nounwind uwtable ssp {
4  %x = alloca i32, align 4
5  store i32 0, i32* %x, align 4
6  %1 = load i32, i32* %x, align 4
7  %2 = icmp ne i32 %1, 0
8  br i1 %2, label %3, label %4
9
10; <label>:3                                       ; preds = %0
11  br label %4
12
13; <label>:4                                       ; preds = %3, %0
14  ret void
15}
16
17define void @branch2() nounwind uwtable ssp {
18  %1 = alloca i32, align 4
19  %x = alloca i32, align 4
20  %y = alloca i32, align 4
21  %z = alloca i32, align 4
22  store i32 0, i32* %1
23  store i32 1, i32* %y, align 4
24  store i32 1, i32* %x, align 4
25  store i32 0, i32* %z, align 4
26  %2 = load i32, i32* %x, align 4
27  %3 = icmp ne i32 %2, 0
28  br i1 %3, label %4, label %5
29
30; <label>:4                                       ; preds = %0
31  store i32 0, i32* %1
32  br label %14
33
34; <label>:5                                       ; preds = %0
35  %6 = load i32, i32* %y, align 4
36  %7 = icmp ne i32 %6, 0
37  br i1 %7, label %8, label %13
38
39; <label>:8                                       ; preds = %5
40  %9 = load i32, i32* %z, align 4
41  %10 = icmp ne i32 %9, 0
42  br i1 %10, label %11, label %12
43
44; <label>:11                                      ; preds = %8
45  store i32 1, i32* %1
46  br label %14
47
48; <label>:12                                      ; preds = %8
49  store i32 0, i32* %1
50  br label %14
51
52; <label>:13                                      ; preds = %5
53  br label %14
54
55; <label>:14                                      ; preds = %4, %11, %12, %13
56  %15 = load i32, i32* %1
57  ret void
58}
59
60define void @true_() nounwind uwtable ssp {
61; CHECK: @true_
62; CHECK: b LBB2_1
63  br i1 true, label %1, label %2
64
65; <label>:1
66; CHECK: LBB2_1
67  br label %2
68
69; <label>:2
70  ret void
71}
72
73define void @false_() nounwind uwtable ssp {
74; CHECK: @false_
75; CHECK: b LBB3_2
76  br i1 false, label %1, label %2
77
78; <label>:1
79  br label %2
80
81; <label>:2
82; CHECK: LBB3_2
83  ret void
84}
85
86define zeroext i8 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) {
87entry:
88  %a.addr = alloca i8, align 1
89  %b.addr = alloca i16, align 2
90  %c.addr = alloca i32, align 4
91  %d.addr = alloca i64, align 8
92  store i8 %a, i8* %a.addr, align 1
93  store i16 %b, i16* %b.addr, align 2
94  store i32 %c, i32* %c.addr, align 4
95  store i64 %d, i64* %d.addr, align 8
96  %0 = load i16, i16* %b.addr, align 2
97; CHECK: tbz w0, #0, LBB4_2
98  %conv = trunc i16 %0 to i1
99  br i1 %conv, label %if.then, label %if.end
100
101if.then:                                          ; preds = %entry
102  call void @foo1()
103  br label %if.end
104
105if.end:                                           ; preds = %if.then, %entry
106  %1 = load i32, i32* %c.addr, align 4
107; CHECK: tbz w{{[0-9]+}}, #0, LBB4_4
108  %conv1 = trunc i32 %1 to i1
109  br i1 %conv1, label %if.then3, label %if.end4
110
111if.then3:                                         ; preds = %if.end
112  call void @foo1()
113  br label %if.end4
114
115if.end4:                                          ; preds = %if.then3, %if.end
116  %2 = load i64, i64* %d.addr, align 8
117; CHECK: tbz w{{[0-9]+}}, #0, LBB4_6
118  %conv5 = trunc i64 %2 to i1
119  br i1 %conv5, label %if.then7, label %if.end8
120
121if.then7:                                         ; preds = %if.end4
122  call void @foo1()
123  br label %if.end8
124
125if.end8:                                          ; preds = %if.then7, %if.end4
126  %3 = load i8, i8* %a.addr, align 1
127  ret i8 %3
128}
129
130declare void @foo1()
131
132; rdar://15174028
133define i32 @trunc64(i64 %foo) nounwind {
134; CHECK: trunc64
135; CHECK: and  [[REG1:x[0-9]+]], x0, #0x1
136; CHECK: mov  x[[REG2:[0-9]+]], [[REG1]]
137; CHECK: tbz w[[REG2]], #0, LBB5_2
138  %a = and i64 %foo, 1
139  %b = trunc i64 %a to i1
140  br i1 %b, label %if.then, label %if.else
141
142if.then:
143  ret i32 1
144
145if.else:
146  ret i32 0
147}
148