1; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
2
3define void @t0(i32 %a) nounwind {
4entry:
5; CHECK: t0
6; CHECK: str {{w[0-9]+}}, [sp, #12]
7; CHECK-NEXT: ldr [[REGISTER:w[0-9]+]], [sp, #12]
8; CHECK-NEXT: str [[REGISTER]], [sp, #12]
9; CHECK: ret
10  %a.addr = alloca i32, align 4
11  store i32 %a, i32* %a.addr
12  %tmp = load i32, i32* %a.addr
13  store i32 %tmp, i32* %a.addr
14  ret void
15}
16
17define void @t1(i64 %a) nounwind {
18; CHECK: t1
19; CHECK: str {{x[0-9]+}}, [sp, #8]
20; CHECK-NEXT: ldr [[REGISTER:x[0-9]+]], [sp, #8]
21; CHECK-NEXT: str [[REGISTER]], [sp, #8]
22; CHECK: ret
23  %a.addr = alloca i64, align 4
24  store i64 %a, i64* %a.addr
25  %tmp = load i64, i64* %a.addr
26  store i64 %tmp, i64* %a.addr
27  ret void
28}
29
30define zeroext i1 @i1(i1 %a) nounwind {
31entry:
32; CHECK: @i1
33; CHECK: and w0, w0, #0x1
34; CHECK: strb w0, [sp, #15]
35; CHECK: ldrb w0, [sp, #15]
36; CHECK: and w0, w0, #0x1
37; CHECK: and w0, w0, #0x1
38; CHECK: add sp, sp, #16
39; CHECK: ret
40  %a.addr = alloca i1, align 1
41  store i1 %a, i1* %a.addr, align 1
42  %0 = load i1, i1* %a.addr, align 1
43  ret i1 %0
44}
45
46define i32 @t2(i32 *%ptr) nounwind {
47entry:
48; CHECK-LABEL: t2:
49; CHECK: ldur w0, [x0, #-4]
50; CHECK: ret
51  %0 = getelementptr i32, i32 *%ptr, i32 -1
52  %1 = load i32, i32* %0, align 4
53  ret i32 %1
54}
55
56define i32 @t3(i32 *%ptr) nounwind {
57entry:
58; CHECK-LABEL: t3:
59; CHECK: ldur w0, [x0, #-256]
60; CHECK: ret
61  %0 = getelementptr i32, i32 *%ptr, i32 -64
62  %1 = load i32, i32* %0, align 4
63  ret i32 %1
64}
65
66define void @t4(i32 *%ptr) nounwind {
67entry:
68; CHECK-LABEL: t4:
69; CHECK: stur wzr, [x0, #-4]
70; CHECK: ret
71  %0 = getelementptr i32, i32 *%ptr, i32 -1
72  store i32 0, i32* %0, align 4
73  ret void
74}
75
76define void @t5(i32 *%ptr) nounwind {
77entry:
78; CHECK-LABEL: t5:
79; CHECK: stur wzr, [x0, #-256]
80; CHECK: ret
81  %0 = getelementptr i32, i32 *%ptr, i32 -64
82  store i32 0, i32* %0, align 4
83  ret void
84}
85
86define void @t6() nounwind {
87; CHECK: t6
88; CHECK: brk #0x1
89  tail call void @llvm.trap()
90  ret void
91}
92
93declare void @llvm.trap() nounwind
94
95define void @ands(i32* %addr) {
96; CHECK-LABEL: ands:
97; CHECK: tst [[COND:w[0-9]+]], #0x1
98; CHECK-NEXT: csel [[COND]],
99entry:
100  %cond91 = select i1 undef, i32 1, i32 2
101  store i32 %cond91, i32* %addr, align 4
102  ret void
103}
104
105define i64 @mul_umul(i64 %arg) {
106; CHECK-LABEL: mul_umul:
107; CHECK: mul x{{[0-9]+}}, [[ARG1:x[0-9]+]], [[ARG2:x[0-9]+]]
108; CHECK-NEXT: umulh x{{[0-9]+}}, [[ARG1]], [[ARG2]]
109entry:
110  %sub.ptr.div = sdiv exact i64 %arg, 8
111  %tmp = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %sub.ptr.div, i64 8)
112  %tmp1 = extractvalue { i64, i1 } %tmp, 0
113  ret i64 %tmp1
114}
115
116declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)
117
118define void @logicalReg() {
119; Make sure we generate a logical reg = reg, reg instruction without any
120; machine verifier errors.
121; CHECK-LABEL: logicalReg:
122; CHECK: orr w{{[0-9]+}}, w{{[0-9]+}}, w{{[0-9]+}}
123; CHECK: ret
124entry:
125  br i1 undef, label %cond.end, label %cond.false
126
127cond.false:
128  %cond = select i1 undef, i1 true, i1 false
129  br label %cond.end
130
131cond.end:
132  %cond13 = phi i1 [ %cond, %cond.false ], [ true, %entry ]
133  ret void
134}
135
136