1; RUN: llc -mtriple=aarch64-eabi %s -o - | FileCheck %s
2
3; These tests just check that the plumbing is in place for @llvm.bitreverse. The
4; actual output is massive at the moment as llvm.bitreverse is not yet legal.
5
6declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>) readnone
7
8define <2 x i16> @f(<2 x i16> %a) {
9; CHECK-LABEL: f:
10; CHECK: rev32
11; CHECK: ushr
12  %b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
13  ret <2 x i16> %b
14}
15
16declare i8 @llvm.bitreverse.i8(i8) readnone
17
18; Unfortunately some of the shift-and-inserts become BFIs, and some do not :(
19define i8 @g(i8 %a) {
20; CHECK-LABEL: g:
21; CHECK-DAG: lsr [[S5:w.*]], w0, #5
22; CHECK-DAG: lsr [[S4:w.*]], w0, #4
23; CHECK-DAG: lsr [[S3:w.*]], w0, #3
24; CHECK-DAG: lsr [[S2:w.*]], w0, #2
25; CHECK-DAG: lsl [[L1:w.*]], w0, #29
26; CHECK-DAG: lsl [[L2:w.*]], w0, #19
27; CHECK-DAG: lsl [[L3:w.*]], w0, #17
28
29; CHECK-DAG: and [[T1:w.*]], [[L1]], #0x40000000
30; CHECK-DAG: bfi [[T1]], w0, #31, #1
31; CHECK-DAG: bfi [[T1]], [[S2]], #29, #1
32; CHECK-DAG: bfi [[T1]], [[S3]], #28, #1
33; CHECK-DAG: bfi [[T1]], [[S4]], #27, #1
34; CHECK-DAG: bfi [[T1]], [[S5]], #26, #1
35; CHECK-DAG: and [[T2:w.*]], [[L2]], #0x2000000
36; CHECK-DAG: and [[T3:w.*]], [[L3]], #0x1000000
37; CHECK-DAG: orr [[T4:w.*]], [[T1]], [[T2]]
38; CHECK-DAG: orr [[T5:w.*]], [[T4]], [[T3]]
39; CHECK:     lsr w0, [[T5]], #24
40
41  %b = call i8 @llvm.bitreverse.i8(i8 %a)
42  ret i8 %b
43}
44
45declare <8 x i8> @llvm.bitreverse.v8i8(<8 x i8>) readnone
46
47define <8 x i8> @g_vec(<8 x i8> %a) {
48; Try and match as much of the sequence as precisely as possible.
49
50; CHECK-LABEL: g_vec:
51; CHECK-DAG: movi [[M1:v.*]], #128
52; CHECK-DAG: movi [[M2:v.*]], #64
53; CHECK-DAG: movi [[M3:v.*]], #32
54; CHECK-DAG: movi [[M4:v.*]], #16
55; CHECK-DAG: movi [[M5:v.*]], #8{{$}}
56; CHECK-DAG: movi [[M6:v.*]], #4{{$}}
57; CHECK-DAG: movi [[M7:v.*]], #2{{$}}
58; CHECK-DAG: movi [[M8:v.*]], #1{{$}}
59; CHECK-DAG: shl  [[S1:v.*]], v0.8b, #7
60; CHECK-DAG: shl  [[S2:v.*]], v0.8b, #5
61; CHECK-DAG: shl  [[S3:v.*]], v0.8b, #3
62; CHECK-DAG: shl  [[S4:v.*]], v0.8b, #1
63; CHECK-DAG: ushr [[S5:v.*]], v0.8b, #1
64; CHECK-DAG: ushr [[S6:v.*]], v0.8b, #3
65; CHECK-DAG: ushr [[S7:v.*]], v0.8b, #5
66; CHECK-DAG: ushr [[S8:v.*]], v0.8b, #7
67; CHECK-DAG: and  [[A1:v.*]], [[S1]], [[M1]]
68; CHECK-DAG: and  [[A2:v.*]], [[S2]], [[M2]]
69; CHECK-DAG: and  [[A3:v.*]], [[S3]], [[M3]]
70; CHECK-DAG: and  [[A4:v.*]], [[S4]], [[M4]]
71; CHECK-DAG: and  [[A5:v.*]], [[S5]], [[M5]]
72; CHECK-DAG: and  [[A6:v.*]], [[S6]], [[M6]]
73; CHECK-DAG: and  [[A7:v.*]], [[S7]], [[M7]]
74; CHECK-DAG: and  [[A8:v.*]], [[S8]], [[M8]]
75
76; The rest can be ORRed together in any order; it's not worth the test
77; maintenance to match them precisely.
78; CHECK-DAG: orr
79; CHECK-DAG: orr
80; CHECK-DAG: orr
81; CHECK-DAG: orr
82; CHECK-DAG: orr
83; CHECK-DAG: orr
84; CHECK-DAG: orr
85; CHECK: ret
86  %b = call <8 x i8> @llvm.bitreverse.v8i8(<8 x i8> %a)
87  ret <8 x i8> %b
88}
89