1; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
2
3define <2 x i64> @test_v2f32_to_signed_v2i64(<2 x float> %in) {
4; CHECK-LABEL: test_v2f32_to_signed_v2i64:
5; CHECK: fcvtl [[VAL64:v[0-9]+]].2d, v0.2s
6; CHECK: fcvtzs.2d v0, [[VAL64]]
7
8  %val = fptosi <2 x float> %in to <2 x i64>
9  ret <2 x i64> %val
10}
11
12define <2 x i64> @test_v2f32_to_unsigned_v2i64(<2 x float> %in) {
13; CHECK-LABEL: test_v2f32_to_unsigned_v2i64:
14; CHECK: fcvtl [[VAL64:v[0-9]+]].2d, v0.2s
15; CHECK: fcvtzu.2d v0, [[VAL64]]
16
17  %val = fptoui <2 x float> %in to <2 x i64>
18  ret <2 x i64> %val
19}
20
21define <2 x i16> @test_v2f32_to_signed_v2i16(<2 x float> %in) {
22; CHECK-LABEL: test_v2f32_to_signed_v2i16:
23; CHECK: fcvtzs.2s v0, v0
24
25  %val = fptosi <2 x float> %in to <2 x i16>
26  ret <2 x i16> %val
27}
28
29define <2 x i16> @test_v2f32_to_unsigned_v2i16(<2 x float> %in) {
30; CHECK-LABEL: test_v2f32_to_unsigned_v2i16:
31; CHECK: fcvtzs.2s v0, v0
32
33  %val = fptoui <2 x float> %in to <2 x i16>
34  ret <2 x i16> %val
35}
36
37define <2 x i8> @test_v2f32_to_signed_v2i8(<2 x float> %in) {
38; CHECK-LABEL: test_v2f32_to_signed_v2i8:
39; CHECK: fcvtzs.2s v0, v0
40
41  %val = fptosi <2 x float> %in to <2 x i8>
42  ret <2 x i8> %val
43}
44
45define <2 x i8> @test_v2f32_to_unsigned_v2i8(<2 x float> %in) {
46; CHECK-LABEL: test_v2f32_to_unsigned_v2i8:
47; CHECK: fcvtzs.2s v0, v0
48
49  %val = fptoui <2 x float> %in to <2 x i8>
50  ret <2 x i8> %val
51}
52
53define <4 x i16> @test_v4f32_to_signed_v4i16(<4 x float> %in) {
54; CHECK-LABEL: test_v4f32_to_signed_v4i16:
55; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
56; CHECK: xtn.4h v0, [[VAL64]]
57
58  %val = fptosi <4 x float> %in to <4 x i16>
59  ret <4 x i16> %val
60}
61
62define <4 x i16> @test_v4f32_to_unsigned_v4i16(<4 x float> %in) {
63; CHECK-LABEL: test_v4f32_to_unsigned_v4i16:
64; CHECK: fcvtzu.4s [[VAL64:v[0-9]+]], v0
65; CHECK: xtn.4h v0, [[VAL64]]
66
67  %val = fptoui <4 x float> %in to <4 x i16>
68  ret <4 x i16> %val
69}
70
71define <4 x i8> @test_v4f32_to_signed_v4i8(<4 x float> %in) {
72; CHECK-LABEL: test_v4f32_to_signed_v4i8:
73; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
74; CHECK: xtn.4h v0, [[VAL64]]
75
76  %val = fptosi <4 x float> %in to <4 x i8>
77  ret <4 x i8> %val
78}
79
80define <4 x i8> @test_v4f32_to_unsigned_v4i8(<4 x float> %in) {
81; CHECK-LABEL: test_v4f32_to_unsigned_v4i8:
82; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
83; CHECK: xtn.4h v0, [[VAL64]]
84
85  %val = fptoui <4 x float> %in to <4 x i8>
86  ret <4 x i8> %val
87}
88
89define <2 x i32> @test_v2f64_to_signed_v2i32(<2 x double> %in) {
90; CHECK-LABEL: test_v2f64_to_signed_v2i32:
91; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
92; CHECK: xtn.2s v0, [[VAL64]]
93
94  %val = fptosi <2 x double> %in to <2 x i32>
95  ret <2 x i32> %val
96}
97
98define <2 x i32> @test_v2f64_to_unsigned_v2i32(<2 x double> %in) {
99; CHECK-LABEL: test_v2f64_to_unsigned_v2i32:
100; CHECK: fcvtzu.2d [[VAL64:v[0-9]+]], v0
101; CHECK: xtn.2s v0, [[VAL64]]
102
103  %val = fptoui <2 x double> %in to <2 x i32>
104  ret <2 x i32> %val
105}
106
107define <2 x i16> @test_v2f64_to_signed_v2i16(<2 x double> %in) {
108; CHECK-LABEL: test_v2f64_to_signed_v2i16:
109; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
110; CHECK: xtn.2s v0, [[VAL64]]
111
112  %val = fptosi <2 x double> %in to <2 x i16>
113  ret <2 x i16> %val
114}
115
116define <2 x i16> @test_v2f64_to_unsigned_v2i16(<2 x double> %in) {
117; CHECK-LABEL: test_v2f64_to_unsigned_v2i16:
118; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
119; CHECK: xtn.2s v0, [[VAL64]]
120
121  %val = fptoui <2 x double> %in to <2 x i16>
122  ret <2 x i16> %val
123}
124
125define <2 x i8> @test_v2f64_to_signed_v2i8(<2 x double> %in) {
126; CHECK-LABEL: test_v2f64_to_signed_v2i8:
127; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
128; CHECK: xtn.2s v0, [[VAL64]]
129
130  %val = fptosi <2 x double> %in to <2 x i8>
131  ret <2 x i8> %val
132}
133
134define <2 x i8> @test_v2f64_to_unsigned_v2i8(<2 x double> %in) {
135; CHECK-LABEL: test_v2f64_to_unsigned_v2i8:
136; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
137; CHECK: xtn.2s v0, [[VAL64]]
138
139  %val = fptoui <2 x double> %in to <2 x i8>
140  ret <2 x i8> %val
141}
142