1; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
3; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
4
5declare i32 @llvm.r600.read.tidig.x() #0
6
7; FUNC-LABEL: {{^}}ashr_v2i32:
8; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
9; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
10
11; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
12; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
13
14; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
15; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
16define void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
17  %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
18  %a = load <2 x i32>, <2 x i32> addrspace(1)* %in
19  %b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr
20  %result = ashr <2 x i32> %a, %b
21  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
22  ret void
23}
24
25; FUNC-LABEL: {{^}}ashr_v4i32:
26; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
27; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
28; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
29; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
30
31; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
32; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
33; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
34; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
35
36; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
37; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
38; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
39; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
40define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
41  %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
42  %a = load <4 x i32>, <4 x i32> addrspace(1)* %in
43  %b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr
44  %result = ashr <4 x i32> %a, %b
45  store <4 x i32> %result, <4 x i32> addrspace(1)* %out
46  ret void
47}
48
49; FUNC-LABEL: {{^}}s_ashr_i64:
50; GCN: s_ashr_i64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8
51
52; EG: ASHR
53define void @s_ashr_i64(i64 addrspace(1)* %out, i32 %in) {
54entry:
55  %in.ext = sext i32 %in to i64
56  %ashr = ashr i64 %in.ext, 8
57  store i64 %ashr, i64 addrspace(1)* %out
58  ret void
59}
60
61; FUNC-LABEL: {{^}}ashr_i64_2:
62; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
63
64; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
65
66; EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]
67; EG: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}
68; EG-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
69; EG-DAG: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
70; EG-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]]
71; EG-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]|PS}}, {{[[OVERF]]|PV.[XYZW]}}
72; EG-DAG: ASHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|PV.[XYZW]|[[SHIFT]]}}
73; EG-DAG: ASHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal
74; EG-DAG: ASHR {{\*? *}}[[HIBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal
75; EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
76; EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
77; EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
78define void @ashr_i64_2(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
79entry:
80  %b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1
81  %a = load i64, i64 addrspace(1)* %in
82  %b = load i64, i64 addrspace(1)* %b_ptr
83  %result = ashr i64 %a, %b
84  store i64 %result, i64 addrspace(1)* %out
85  ret void
86}
87
88; FUNC-LABEL: {{^}}ashr_v2i64:
89; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
90; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
91
92; EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
93; EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
94; EG-DAG: LSHL {{\*? *}}[[COMPSHA]]
95; EG-DAG: LSHL {{\*? *}}[[COMPSHB]]
96; EG-DAG: LSHL {{.*}}, 1
97; EG-DAG: LSHL {{.*}}, 1
98; EG-DAG: ASHR {{.*}}, [[SHA]]
99; EG-DAG: ASHR {{.*}}, [[SHB]]
100; EG-DAG: LSHR {{.*}}, [[SHA]]
101; EG-DAG: LSHR {{.*}}, [[SHB]]
102; EG-DAG: OR_INT
103; EG-DAG: OR_INT
104; EG-DAG: ADD_INT  {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
105; EG-DAG: ADD_INT  {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
106; EG-DAG: ASHR
107; EG-DAG: ASHR
108; EG-DAG: ASHR {{.*}}, literal
109; EG-DAG: ASHR {{.*}}, literal
110; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
111; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
112; EG-DAG: CNDE_INT
113; EG-DAG: CNDE_INT
114; EG-DAG: CNDE_INT
115; EG-DAG: CNDE_INT
116define void @ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
117  %b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1
118  %a = load <2 x i64>, <2 x i64> addrspace(1)* %in
119  %b = load <2 x i64>, <2 x i64> addrspace(1)* %b_ptr
120  %result = ashr <2 x i64> %a, %b
121  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
122  ret void
123}
124
125; FIXME: Broken on r600
126; XFUNC-LABEL: {{^}}s_ashr_v2i64:
127; XGCN: s_ashr_i64 {{s\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], s[0-9]+}}
128; XGCN: s_ashr_i64 {{s\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], s[0-9]+}}
129; define void @s_ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in, <2 x i64> %a, <2 x i64> %b) {
130;   %result = ashr <2 x i64> %a, %b
131;   store <2 x i64> %result, <2 x i64> addrspace(1)* %out
132;   ret void
133; }
134
135; FUNC-LABEL: {{^}}ashr_v4i64:
136; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
137; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
138; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
139; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
140
141; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
142; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
143; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
144; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
145
146; EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
147; EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
148; EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]]
149; EG-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]]
150; EG-DAG: LSHL {{\*? *}}[[COMPSHA]]
151; EG-DAG: LSHL {{\*? *}}[[COMPSHB]]
152; EG-DAG: LSHL {{\*? *}}[[COMPSHC]]
153; EG-DAG: LSHL {{\*? *}}[[COMPSHD]]
154; EG-DAG: LSHL {{.*}}, 1
155; EG-DAG: LSHL {{.*}}, 1
156; EG-DAG: LSHL {{.*}}, 1
157; EG-DAG: LSHL {{.*}}, 1
158; EG-DAG: ASHR {{.*}}, [[SHA]]
159; EG-DAG: ASHR {{.*}}, [[SHB]]
160; EG-DAG: ASHR {{.*}}, [[SHC]]
161; EG-DAG: ASHR {{.*}}, [[SHD]]
162; EG-DAG: LSHR {{.*}}, [[SHA]]
163; EG-DAG: LSHR {{.*}}, [[SHB]]
164; EG-DAG: LSHR {{.*}}, [[SHA]]
165; EG-DAG: LSHR {{.*}}, [[SHB]]
166; EG-DAG: OR_INT
167; EG-DAG: OR_INT
168; EG-DAG: OR_INT
169; EG-DAG: OR_INT
170; EG-DAG: ADD_INT  {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
171; EG-DAG: ADD_INT  {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
172; EG-DAG: ADD_INT  {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal
173; EG-DAG: ADD_INT  {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal
174; EG-DAG: ASHR
175; EG-DAG: ASHR
176; EG-DAG: ASHR
177; EG-DAG: ASHR
178; EG-DAG: ASHR {{.*}}, literal
179; EG-DAG: ASHR {{.*}}, literal
180; EG-DAG: ASHR {{.*}}, literal
181; EG-DAG: ASHR {{.*}}, literal
182; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
183; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
184; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal
185; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal
186; EG-DAG: CNDE_INT
187; EG-DAG: CNDE_INT
188; EG-DAG: CNDE_INT
189; EG-DAG: CNDE_INT
190; EG-DAG: CNDE_INT
191; EG-DAG: CNDE_INT
192; EG-DAG: CNDE_INT
193; EG-DAG: CNDE_INT
194define void @ashr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
195  %b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1
196  %a = load <4 x i64>, <4 x i64> addrspace(1)* %in
197  %b = load <4 x i64>, <4 x i64> addrspace(1)* %b_ptr
198  %result = ashr <4 x i64> %a, %b
199  store <4 x i64> %result, <4 x i64> addrspace(1)* %out
200  ret void
201}
202
203; GCN-LABEL: {{^}}s_ashr_32_i64:
204; GCN: s_load_dword s[[HI:[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, {{0xc|0x30}}
205; GCN: s_ashr_i32 s[[SHIFT:[0-9]+]], s[[HI]], 31
206; GCN: s_add_u32 s{{[0-9]+}}, s[[HI]], s{{[0-9]+}}
207; GCN: s_addc_u32 s{{[0-9]+}}, s[[SHIFT]], s{{[0-9]+}}
208define void @s_ashr_32_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
209  %result = ashr i64 %a, 32
210  %add = add i64 %result, %b
211  store i64 %add, i64 addrspace(1)* %out
212  ret void
213}
214
215; GCN-LABEL: {{^}}v_ashr_32_i64:
216; SI: buffer_load_dword v[[HI:[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
217; VI: flat_load_dword v[[HI:[0-9]+]]
218; GCN: v_ashrrev_i32_e32 v[[SHIFT:[0-9]+]], 31, v[[HI]]
219; GCN: {{buffer|flat}}_store_dwordx2 {{.*}}v{{\[}}[[HI]]:[[SHIFT]]{{\]}}
220define void @v_ashr_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
221  %tid = call i32 @llvm.r600.read.tidig.x() #0
222  %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
223  %gep.out = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
224  %a = load i64, i64 addrspace(1)* %gep.in
225  %result = ashr i64 %a, 32
226  store i64 %result, i64 addrspace(1)* %gep.out
227  ret void
228}
229
230; GCN-LABEL: {{^}}s_ashr_63_i64:
231; GCN: s_load_dword s[[HI:[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, {{0xc|0x30}}
232; GCN: s_ashr_i32 s[[SHIFT:[0-9]+]], s[[HI]], 31
233; GCN: s_add_u32 {{s[0-9]+}}, s[[SHIFT]], {{s[0-9]+}}
234; GCN: s_addc_u32 {{s[0-9]+}}, s[[SHIFT]], {{s[0-9]+}}
235define void @s_ashr_63_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
236  %result = ashr i64 %a, 63
237  %add = add i64 %result, %b
238  store i64 %add, i64 addrspace(1)* %out
239  ret void
240}
241
242; GCN-LABEL: {{^}}v_ashr_63_i64:
243; SI: buffer_load_dword v[[HI:[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
244; VI: flat_load_dword v[[HI:[0-9]+]]
245; GCN: v_ashrrev_i32_e32 v[[SHIFT:[0-9]+]], 31, v[[HI]]
246; GCN: v_mov_b32_e32 v[[COPY:[0-9]+]], v[[SHIFT]]
247; GCN: {{buffer|flat}}_store_dwordx2 {{.*}}v{{\[}}[[SHIFT]]:[[COPY]]{{\]}}
248define void @v_ashr_63_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
249  %tid = call i32 @llvm.r600.read.tidig.x() #0
250  %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
251  %gep.out = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
252  %a = load i64, i64 addrspace(1)* %gep.in
253  %result = ashr i64 %a, 63
254  store i64 %result, i64 addrspace(1)* %gep.out
255  ret void
256}
257
258attributes #0 = { nounwind readnone }
259