1; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \ 2; RUN: -verify-machineinstrs < %s | FileCheck %s 3; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \ 4; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE 5 6define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 7entry: 8; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_ 9; CHECK: xxsldwi 0, 35, 35, 2 10; CHECK: xxinsertw 34, 0, 12 11; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_ 12; CHECK-BE: xxsldwi 0, 35, 35, 3 13; CHECK-BE: xxinsertw 34, 0, 0 14 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3> 15 ret <4 x float> %vecins 16} 17 18define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 19entry: 20; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_ 21; CHECK: xxsldwi 0, 35, 35, 1 22; CHECK: xxinsertw 34, 0, 12 23; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_ 24; CHECK-BE-NOT: xxsldwi 25; CHECK-BE: xxinsertw 34, 35, 0 26 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3> 27 ret <4 x float> %vecins 28} 29 30define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 31entry: 32; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_ 33; CHECK-NOT: xxsldwi 34; CHECK: xxinsertw 34, 35, 12 35; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_ 36; CHECK-BE: xxsldwi 0, 35, 35, 1 37; CHECK-BE: xxinsertw 34, 0, 0 38 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3> 39 ret <4 x float> %vecins 40} 41 42define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 43entry: 44; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_ 45; CHECK: xxsldwi 0, 35, 35, 3 46; CHECK: xxinsertw 34, 0, 12 47; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_ 48; CHECK-BE: xxsldwi 0, 35, 35, 2 49; CHECK-BE: xxinsertw 34, 0, 0 50 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3> 51 ret <4 x float> %vecins 52} 53 54define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 55entry: 56; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_ 57; CHECK: xxsldwi 0, 35, 35, 2 58; CHECK: xxinsertw 34, 0, 8 59; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_ 60; CHECK-BE: xxsldwi 0, 35, 35, 3 61; CHECK-BE: xxinsertw 34, 0, 4 62 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3> 63 ret <4 x float> %vecins 64} 65 66define <4 x float> @_Z7testInsILj1ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 67entry: 68; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_ 69; CHECK: xxsldwi 0, 35, 35, 1 70; CHECK: xxinsertw 34, 0, 8 71; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_ 72; CHECK-BE-NOT: xxsldwi 73; CHECK-BE: xxinsertw 34, 35, 4 74 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3> 75 ret <4 x float> %vecins 76} 77 78define <4 x float> @_Z7testInsILj1ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 79entry: 80; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_ 81; CHECK-NOT: xxsldwi 82; CHECK: xxinsertw 34, 35, 8 83; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_ 84; CHECK-BE: xxsldwi 0, 35, 35, 1 85; CHECK-BE: xxinsertw 34, 0, 4 86 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3> 87 ret <4 x float> %vecins 88} 89 90define <4 x float> @_Z7testInsILj1ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 91entry: 92; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_ 93; CHECK: xxsldwi 0, 35, 35, 3 94; CHECK: xxinsertw 34, 0, 8 95; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_ 96; CHECK-BE: xxsldwi 0, 35, 35, 2 97; CHECK-BE: xxinsertw 34, 0, 4 98 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3> 99 ret <4 x float> %vecins 100} 101 102define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 103entry: 104; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_ 105; CHECK: xxsldwi 0, 35, 35, 2 106; CHECK: xxinsertw 34, 0, 4 107; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_ 108; CHECK-BE: xxsldwi 0, 35, 35, 3 109; CHECK-BE: xxinsertw 34, 0, 8 110 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3> 111 ret <4 x float> %vecins 112} 113 114define <4 x float> @_Z7testInsILj2ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 115entry: 116; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_ 117; CHECK: xxsldwi 0, 35, 35, 1 118; CHECK: xxinsertw 34, 0, 4 119; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_ 120; CHECK-BE-NOT: xxsldwi 121; CHECK-BE: xxinsertw 34, 35, 8 122 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3> 123 ret <4 x float> %vecins 124} 125 126define <4 x float> @_Z7testInsILj2ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 127entry: 128; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_ 129; CHECK-NOT: xxsldwi 130; CHECK: xxinsertw 34, 35, 4 131; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_ 132; CHECK-BE: xxsldwi 0, 35, 35, 1 133; CHECK-BE: xxinsertw 34, 0, 8 134 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3> 135 ret <4 x float> %vecins 136} 137 138define <4 x float> @_Z7testInsILj2ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 139entry: 140; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_ 141; CHECK: xxsldwi 0, 35, 35, 3 142; CHECK: xxinsertw 34, 0, 4 143; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_ 144; CHECK-BE: xxsldwi 0, 35, 35, 2 145; CHECK-BE: xxinsertw 34, 0, 8 146 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3> 147 ret <4 x float> %vecins 148} 149 150define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 151entry: 152; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_ 153; CHECK: xxsldwi 0, 35, 35, 2 154; CHECK: xxinsertw 34, 0, 0 155; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_ 156; CHECK-BE: xxsldwi 0, 35, 35, 3 157; CHECK-BE: xxinsertw 34, 0, 12 158 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4> 159 ret <4 x float> %vecins 160} 161 162define <4 x float> @_Z7testInsILj3ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 163entry: 164; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_ 165; CHECK: xxsldwi 0, 35, 35, 1 166; CHECK: xxinsertw 34, 0, 0 167; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_ 168; CHECK-BE-NOT: xxsldwi 169; CHECK-BE: xxinsertw 34, 35, 12 170 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 5> 171 ret <4 x float> %vecins 172} 173 174define <4 x float> @_Z7testInsILj3ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 175entry: 176; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_ 177; CHECK-NOT: xxsldwi 178; CHECK: xxinsertw 34, 35, 0 179; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_ 180; CHECK-BE: xxsldwi 0, 35, 35, 1 181; CHECK-BE: xxinsertw 34, 0, 12 182 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 6> 183 ret <4 x float> %vecins 184} 185 186define <4 x float> @_Z7testInsILj3ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { 187entry: 188; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_ 189; CHECK: xxsldwi 0, 35, 35, 3 190; CHECK: xxinsertw 34, 0, 0 191; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_ 192; CHECK-BE: xxsldwi 0, 35, 35, 2 193; CHECK-BE: xxinsertw 34, 0, 12 194 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7> 195 ret <4 x float> %vecins 196} 197 198define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 199entry: 200; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_ 201; CHECK: xxsldwi 0, 35, 35, 2 202; CHECK: xxinsertw 34, 0, 12 203; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_ 204; CHECK-BE: xxsldwi 0, 35, 35, 3 205; CHECK-BE: xxinsertw 34, 0, 0 206 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3> 207 ret <4 x i32> %vecins 208} 209 210define <4 x i32> @_Z7testInsILj0ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 211entry: 212; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_ 213; CHECK: xxsldwi 0, 35, 35, 1 214; CHECK: xxinsertw 34, 0, 12 215; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_ 216; CHECK-BE-NOT: xxsldwi 217; CHECK-BE: xxinsertw 34, 35, 0 218 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3> 219 ret <4 x i32> %vecins 220} 221 222define <4 x i32> @_Z7testInsILj0ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 223entry: 224; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_ 225; CHECK-NOT: xxsldwi 226; CHECK: xxinsertw 34, 35, 12 227; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_ 228; CHECK-BE: xxsldwi 0, 35, 35, 1 229; CHECK-BE: xxinsertw 34, 0, 0 230 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3> 231 ret <4 x i32> %vecins 232} 233 234define <4 x i32> @_Z7testInsILj0ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 235entry: 236; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_ 237; CHECK: xxsldwi 0, 35, 35, 3 238; CHECK: xxinsertw 34, 0, 12 239; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_ 240; CHECK-BE: xxsldwi 0, 35, 35, 2 241; CHECK-BE: xxinsertw 34, 0, 0 242 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3> 243 ret <4 x i32> %vecins 244} 245 246define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 247entry: 248; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_ 249; CHECK: xxsldwi 0, 35, 35, 2 250; CHECK: xxinsertw 34, 0, 8 251; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_ 252; CHECK-BE: xxsldwi 0, 35, 35, 3 253; CHECK-BE: xxinsertw 34, 0, 4 254 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3> 255 ret <4 x i32> %vecins 256} 257 258define <4 x i32> @_Z7testInsILj1ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 259entry: 260; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_ 261; CHECK: xxsldwi 0, 35, 35, 1 262; CHECK: xxinsertw 34, 0, 8 263; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_ 264; CHECK-BE-NOT: xxsldwi 265; CHECK-BE: xxinsertw 34, 35, 4 266 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3> 267 ret <4 x i32> %vecins 268} 269 270define <4 x i32> @_Z7testInsILj1ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 271entry: 272; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_ 273; CHECK-NOT: xxsldwi 274; CHECK: xxinsertw 34, 35, 8 275; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_ 276; CHECK-BE: xxsldwi 0, 35, 35, 1 277; CHECK-BE: xxinsertw 34, 0, 4 278 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3> 279 ret <4 x i32> %vecins 280} 281 282define <4 x i32> @_Z7testInsILj1ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 283entry: 284; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_ 285; CHECK: xxsldwi 0, 35, 35, 3 286; CHECK: xxinsertw 34, 0, 8 287; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_ 288; CHECK-BE: xxsldwi 0, 35, 35, 2 289; CHECK-BE: xxinsertw 34, 0, 4 290 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3> 291 ret <4 x i32> %vecins 292} 293 294define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 295entry: 296; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_ 297; CHECK: xxsldwi 0, 35, 35, 2 298; CHECK: xxinsertw 34, 0, 4 299; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_ 300; CHECK-BE: xxsldwi 0, 35, 35, 3 301; CHECK-BE: xxinsertw 34, 0, 8 302 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3> 303 ret <4 x i32> %vecins 304} 305 306define <4 x i32> @_Z7testInsILj2ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 307entry: 308; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_ 309; CHECK: xxsldwi 0, 35, 35, 1 310; CHECK: xxinsertw 34, 0, 4 311; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_ 312; CHECK-BE-NOT: xxsldwi 313; CHECK-BE: xxinsertw 34, 35, 8 314 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3> 315 ret <4 x i32> %vecins 316} 317 318define <4 x i32> @_Z7testInsILj2ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 319entry: 320; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_ 321; CHECK-NOT: xxsldwi 322; CHECK: xxinsertw 34, 35, 4 323; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_ 324; CHECK-BE: xxsldwi 0, 35, 35, 1 325; CHECK-BE: xxinsertw 34, 0, 8 326 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3> 327 ret <4 x i32> %vecins 328} 329 330define <4 x i32> @_Z7testInsILj2ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 331entry: 332; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_ 333; CHECK: xxsldwi 0, 35, 35, 3 334; CHECK: xxinsertw 34, 0, 4 335; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_ 336; CHECK-BE: xxsldwi 0, 35, 35, 2 337; CHECK-BE: xxinsertw 34, 0, 8 338 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3> 339 ret <4 x i32> %vecins 340} 341 342define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 343entry: 344; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_ 345; CHECK: xxsldwi 0, 35, 35, 2 346; CHECK: xxinsertw 34, 0, 0 347; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_ 348; CHECK-BE: xxsldwi 0, 35, 35, 3 349; CHECK-BE: xxinsertw 34, 0, 12 350 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4> 351 ret <4 x i32> %vecins 352} 353 354define <4 x i32> @_Z7testInsILj3ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 355entry: 356; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_ 357; CHECK: xxsldwi 0, 35, 35, 1 358; CHECK: xxinsertw 34, 0, 0 359; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_ 360; CHECK-BE-NOT: xxsldwi 361; CHECK-BE: xxinsertw 34, 35, 12 362 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 5> 363 ret <4 x i32> %vecins 364} 365 366define <4 x i32> @_Z7testInsILj3ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 367entry: 368; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_ 369; CHECK-NOT: xxsldwi 370; CHECK: xxinsertw 34, 35, 0 371; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_ 372; CHECK-BE: xxsldwi 0, 35, 35, 1 373; CHECK-BE: xxinsertw 34, 0, 12 374 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 6> 375 ret <4 x i32> %vecins 376} 377 378define <4 x i32> @_Z7testInsILj3ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { 379entry: 380; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_ 381; CHECK: xxsldwi 0, 35, 35, 3 382; CHECK: xxinsertw 34, 0, 0 383; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_ 384; CHECK-BE: xxsldwi 0, 35, 35, 2 385; CHECK-BE: xxinsertw 34, 0, 12 386 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7> 387 ret <4 x i32> %vecins 388} 389 390define float @_Z13testUiToFpExtILj0EEfDv4_j(<4 x i32> %a) { 391entry: 392; CHECK-LABEL: _Z13testUiToFpExtILj0EEfDv4_j 393; CHECK: xxextractuw 0, 34, 12 394; CHECK: xscvuxdsp 1, 0 395; CHECK-BE-LABEL: _Z13testUiToFpExtILj0EEfDv4_j 396; CHECK-BE: xxextractuw 0, 34, 0 397; CHECK-BE: xscvuxdsp 1, 0 398 %vecext = extractelement <4 x i32> %a, i32 0 399 %conv = uitofp i32 %vecext to float 400 ret float %conv 401} 402 403define float @_Z13testUiToFpExtILj1EEfDv4_j(<4 x i32> %a) { 404entry: 405; CHECK-LABEL: _Z13testUiToFpExtILj1EEfDv4_j 406; CHECK: xxextractuw 0, 34, 8 407; CHECK: xscvuxdsp 1, 0 408; CHECK-BE-LABEL: _Z13testUiToFpExtILj1EEfDv4_j 409; CHECK-BE: xxextractuw 0, 34, 4 410; CHECK-BE: xscvuxdsp 1, 0 411 %vecext = extractelement <4 x i32> %a, i32 1 412 %conv = uitofp i32 %vecext to float 413 ret float %conv 414} 415 416define float @_Z13testUiToFpExtILj2EEfDv4_j(<4 x i32> %a) { 417entry: 418; CHECK-LABEL: _Z13testUiToFpExtILj2EEfDv4_j 419; CHECK: xxextractuw 0, 34, 4 420; CHECK: xscvuxdsp 1, 0 421; CHECK-BE-LABEL: _Z13testUiToFpExtILj2EEfDv4_j 422; CHECK-BE: xxextractuw 0, 34, 8 423; CHECK-BE: xscvuxdsp 1, 0 424 %vecext = extractelement <4 x i32> %a, i32 2 425 %conv = uitofp i32 %vecext to float 426 ret float %conv 427} 428 429define float @_Z13testUiToFpExtILj3EEfDv4_j(<4 x i32> %a) { 430entry: 431; CHECK-LABEL: _Z13testUiToFpExtILj3EEfDv4_j 432; CHECK: xxextractuw 0, 34, 0 433; CHECK: xscvuxdsp 1, 0 434; CHECK-BE-LABEL: _Z13testUiToFpExtILj3EEfDv4_j 435; CHECK-BE: xxextractuw 0, 34, 12 436; CHECK-BE: xscvuxdsp 1, 0 437 %vecext = extractelement <4 x i32> %a, i32 3 438 %conv = uitofp i32 %vecext to float 439 ret float %conv 440} 441 442define <4 x float> @_Z10testInsEltILj0EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) { 443entry: 444; CHECK-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_ 445; CHECK: xscvdpspn 0, 1 446; CHECK: xxsldwi 0, 0, 0, 3 447; CHECK: xxinsertw 34, 0, 12 448; CHECK-BE-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_ 449; CHECK-BE: xscvdpspn 0, 1 450; CHECK-BE: xxsldwi 0, 0, 0, 3 451; CHECK-BE: xxinsertw 34, 0, 0 452 %vecins = insertelement <4 x float> %a, float %b, i32 0 453 ret <4 x float> %vecins 454} 455 456define <4 x float> @_Z10testInsEltILj1EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) { 457entry: 458; CHECK-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_ 459; CHECK: xscvdpspn 0, 1 460; CHECK: xxsldwi 0, 0, 0, 3 461; CHECK: xxinsertw 34, 0, 8 462; CHECK-BE-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_ 463; CHECK-BE: xscvdpspn 0, 1 464; CHECK-BE: xxsldwi 0, 0, 0, 3 465; CHECK-BE: xxinsertw 34, 0, 4 466 %vecins = insertelement <4 x float> %a, float %b, i32 1 467 ret <4 x float> %vecins 468} 469 470define <4 x float> @_Z10testInsEltILj2EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) { 471entry: 472; CHECK-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_ 473; CHECK: xscvdpspn 0, 1 474; CHECK: xxsldwi 0, 0, 0, 3 475; CHECK: xxinsertw 34, 0, 4 476; CHECK-BE-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_ 477; CHECK-BE: xscvdpspn 0, 1 478; CHECK-BE: xxsldwi 0, 0, 0, 3 479; CHECK-BE: xxinsertw 34, 0, 8 480 %vecins = insertelement <4 x float> %a, float %b, i32 2 481 ret <4 x float> %vecins 482} 483 484define <4 x float> @_Z10testInsEltILj3EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) { 485entry: 486; CHECK-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_ 487; CHECK: xscvdpspn 0, 1 488; CHECK: xxsldwi 0, 0, 0, 3 489; CHECK: xxinsertw 34, 0, 0 490; CHECK-BE-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_ 491; CHECK-BE: xscvdpspn 0, 1 492; CHECK-BE: xxsldwi 0, 0, 0, 3 493; CHECK-BE: xxinsertw 34, 0, 12 494 %vecins = insertelement <4 x float> %a, float %b, i32 3 495 ret <4 x float> %vecins 496} 497 498define <4 x i32> @_Z10testInsEltILj0EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) { 499entry: 500; CHECK-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_ 501; CHECK: mtvsrwz 0, 5 502; CHECK: xxinsertw 34, 0, 12 503; CHECK-BE-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_ 504; CHECK-BE: mtvsrwz 0, 5 505; CHECK-BE: xxinsertw 34, 0, 0 506 %vecins = insertelement <4 x i32> %a, i32 %b, i32 0 507 ret <4 x i32> %vecins 508} 509 510define <4 x i32> @_Z10testInsEltILj1EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) { 511entry: 512; CHECK-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_ 513; CHECK: mtvsrwz 0, 5 514; CHECK: xxinsertw 34, 0, 8 515; CHECK-BE-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_ 516; CHECK-BE: mtvsrwz 0, 5 517; CHECK-BE: xxinsertw 34, 0, 4 518 %vecins = insertelement <4 x i32> %a, i32 %b, i32 1 519 ret <4 x i32> %vecins 520} 521 522define <4 x i32> @_Z10testInsEltILj2EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) { 523entry: 524; CHECK-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_ 525; CHECK: mtvsrwz 0, 5 526; CHECK: xxinsertw 34, 0, 4 527; CHECK-BE-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_ 528; CHECK-BE: mtvsrwz 0, 5 529; CHECK-BE: xxinsertw 34, 0, 8 530 %vecins = insertelement <4 x i32> %a, i32 %b, i32 2 531 ret <4 x i32> %vecins 532} 533 534define <4 x i32> @_Z10testInsEltILj3EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) { 535entry: 536; CHECK-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_ 537; CHECK: mtvsrwz 0, 5 538; CHECK: xxinsertw 34, 0, 0 539; CHECK-BE-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_ 540; CHECK-BE: mtvsrwz 0, 5 541; CHECK-BE: xxinsertw 34, 0, 12 542 %vecins = insertelement <4 x i32> %a, i32 %b, i32 3 543 ret <4 x i32> %vecins 544} 545 546define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 547entry: 548; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_ 549; CHECK: xxsldwi 0, 35, 35, 2 550; CHECK: xxinsertw 34, 0, 12 551; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_ 552; CHECK-BE: xxsldwi 0, 35, 35, 3 553; CHECK-BE: xxinsertw 34, 0, 0 554 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7> 555 ret <4 x float> %vecins 556} 557 558define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 559entry: 560; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_ 561; CHECK: xxsldwi 0, 35, 35, 1 562; CHECK: xxinsertw 34, 0, 12 563; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_ 564; CHECK-BE-NOT: xxsldwi 565; CHECK-BE: xxinsertw 34, 35, 0 566 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 1, i32 5, i32 6, i32 7> 567 ret <4 x float> %vecins 568} 569 570define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 571entry: 572; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_ 573; CHECK-NOT: xxsldwi 574; CHECK: xxinsertw 34, 35, 12 575; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_ 576; CHECK-BE: xxsldwi 0, 35, 35, 1 577; CHECK-BE: xxinsertw 34, 0, 0 578 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 6, i32 7> 579 ret <4 x float> %vecins 580} 581 582define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 583entry: 584; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_ 585; CHECK: xxsldwi 0, 35, 35, 3 586; CHECK: xxinsertw 34, 0, 12 587; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_ 588; CHECK-BE: xxsldwi 0, 35, 35, 2 589; CHECK-BE: xxinsertw 34, 0, 0 590 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7> 591 ret <4 x float> %vecins 592} 593 594define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 595entry: 596; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_ 597; CHECK: xxsldwi 0, 35, 35, 2 598; CHECK: xxinsertw 34, 0, 8 599; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_ 600; CHECK-BE: xxsldwi 0, 35, 35, 3 601; CHECK-BE: xxinsertw 34, 0, 4 602 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 0, i32 6, i32 7> 603 ret <4 x float> %vecins 604} 605 606define <4 x float> @_Z7testInsILj1ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 607entry: 608; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_ 609; CHECK: xxsldwi 0, 35, 35, 1 610; CHECK: xxinsertw 34, 0, 8 611; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_ 612; CHECK-BE-NOT: xxsldwi 613; CHECK-BE: xxinsertw 34, 35, 4 614 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 7> 615 ret <4 x float> %vecins 616} 617 618define <4 x float> @_Z7testInsILj1ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 619entry: 620; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_ 621; CHECK-NOT: xxsldwi 622; CHECK: xxinsertw 34, 35, 8 623; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_ 624; CHECK-BE: xxsldwi 0, 35, 35, 1 625; CHECK-BE: xxinsertw 34, 0, 4 626 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 2, i32 6, i32 7> 627 ret <4 x float> %vecins 628} 629 630define <4 x float> @_Z7testInsILj1ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 631entry: 632; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_ 633; CHECK: xxsldwi 0, 35, 35, 3 634; CHECK: xxinsertw 34, 0, 8 635; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_ 636; CHECK-BE: xxsldwi 0, 35, 35, 2 637; CHECK-BE: xxinsertw 34, 0, 4 638 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7> 639 ret <4 x float> %vecins 640} 641 642define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 643entry: 644; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_ 645; CHECK: xxsldwi 0, 35, 35, 2 646; CHECK: xxinsertw 34, 0, 4 647; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_ 648; CHECK-BE: xxsldwi 0, 35, 35, 3 649; CHECK-BE: xxinsertw 34, 0, 8 650 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 7> 651 ret <4 x float> %vecins 652} 653 654define <4 x float> @_Z7testInsILj2ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 655entry: 656; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_ 657; CHECK: xxsldwi 0, 35, 35, 1 658; CHECK: xxinsertw 34, 0, 4 659; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_ 660; CHECK-BE-NOT: xxsldwi 661; CHECK-BE: xxinsertw 34, 35, 8 662 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 7> 663 ret <4 x float> %vecins 664} 665 666define <4 x float> @_Z7testInsILj2ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 667entry: 668; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_ 669; CHECK-NOT: xxsldwi 670; CHECK: xxinsertw 34, 35, 4 671; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_ 672; CHECK-BE: xxsldwi 0, 35, 35, 1 673; CHECK-BE: xxinsertw 34, 0, 8 674 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 7> 675 ret <4 x float> %vecins 676} 677 678define <4 x float> @_Z7testInsILj2ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 679entry: 680; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_ 681; CHECK: xxsldwi 0, 35, 35, 3 682; CHECK: xxinsertw 34, 0, 4 683; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_ 684; CHECK-BE: xxsldwi 0, 35, 35, 2 685; CHECK-BE: xxinsertw 34, 0, 8 686 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7> 687 ret <4 x float> %vecins 688} 689 690define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 691entry: 692; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_ 693; CHECK: xxsldwi 0, 35, 35, 2 694; CHECK: xxinsertw 34, 0, 0 695; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_ 696; CHECK-BE: xxsldwi 0, 35, 35, 3 697; CHECK-BE: xxinsertw 34, 0, 12 698 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 0> 699 ret <4 x float> %vecins 700} 701 702define <4 x float> @_Z7testInsILj3ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 703entry: 704; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_ 705; CHECK: xxsldwi 0, 35, 35, 1 706; CHECK: xxinsertw 34, 0, 0 707; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_ 708; CHECK-BE-NOT: xxsldwi 709; CHECK-BE: xxinsertw 34, 35, 12 710 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 1> 711 ret <4 x float> %vecins 712} 713 714define <4 x float> @_Z7testInsILj3ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 715entry: 716; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_ 717; CHECK-NOT: xxsldwi 718; CHECK: xxinsertw 34, 35, 0 719; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_ 720; CHECK-BE: xxsldwi 0, 35, 35, 1 721; CHECK-BE: xxinsertw 34, 0, 12 722 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 2> 723 ret <4 x float> %vecins 724} 725 726define <4 x float> @_Z7testInsILj3ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { 727entry: 728; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_ 729; CHECK: xxsldwi 0, 35, 35, 3 730; CHECK: xxinsertw 34, 0, 0 731; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_ 732; CHECK-BE: xxsldwi 0, 35, 35, 2 733; CHECK-BE: xxinsertw 34, 0, 12 734 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3> 735 ret <4 x float> %vecins 736} 737 738define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 739entry: 740; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_ 741; CHECK: xxsldwi 0, 35, 35, 2 742; CHECK: xxinsertw 34, 0, 12 743; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_ 744; CHECK-BE: xxsldwi 0, 35, 35, 3 745; CHECK-BE: xxinsertw 34, 0, 0 746 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7> 747 ret <4 x i32> %vecins 748} 749 750define <4 x i32> @_Z7testInsILj0ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 751entry: 752; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_ 753; CHECK: xxsldwi 0, 35, 35, 1 754; CHECK: xxinsertw 34, 0, 12 755; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_ 756; CHECK-BE-NOT: xxsldwi 757; CHECK-BE: xxinsertw 34, 35, 0 758 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 1, i32 5, i32 6, i32 7> 759 ret <4 x i32> %vecins 760} 761 762define <4 x i32> @_Z7testInsILj0ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 763entry: 764; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_ 765; CHECK-NOT: xxsldwi 766; CHECK: xxinsertw 34, 35, 12 767; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_ 768; CHECK-BE: xxsldwi 0, 35, 35, 1 769; CHECK-BE: xxinsertw 34, 0, 0 770 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 2, i32 5, i32 6, i32 7> 771 ret <4 x i32> %vecins 772} 773 774define <4 x i32> @_Z7testInsILj0ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 775entry: 776; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_ 777; CHECK: xxsldwi 0, 35, 35, 3 778; CHECK: xxinsertw 34, 0, 12 779; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_ 780; CHECK-BE: xxsldwi 0, 35, 35, 2 781; CHECK-BE: xxinsertw 34, 0, 0 782 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7> 783 ret <4 x i32> %vecins 784} 785 786define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 787entry: 788; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_ 789; CHECK: xxsldwi 0, 35, 35, 2 790; CHECK: xxinsertw 34, 0, 8 791; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_ 792; CHECK-BE: xxsldwi 0, 35, 35, 3 793; CHECK-BE: xxinsertw 34, 0, 4 794 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 0, i32 6, i32 7> 795 ret <4 x i32> %vecins 796} 797 798define <4 x i32> @_Z7testInsILj1ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 799entry: 800; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_ 801; CHECK: xxsldwi 0, 35, 35, 1 802; CHECK: xxinsertw 34, 0, 8 803; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_ 804; CHECK-BE-NOT: xxsldwi 805; CHECK-BE: xxinsertw 34, 35, 4 806 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 7> 807 ret <4 x i32> %vecins 808} 809 810define <4 x i32> @_Z7testInsILj1ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 811entry: 812; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_ 813; CHECK-NOT: xxsldwi 814; CHECK: xxinsertw 34, 35, 8 815; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_ 816; CHECK-BE: xxsldwi 0, 35, 35, 1 817; CHECK-BE: xxinsertw 34, 0, 4 818 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 2, i32 6, i32 7> 819 ret <4 x i32> %vecins 820} 821 822define <4 x i32> @_Z7testInsILj1ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 823entry: 824; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_ 825; CHECK: xxsldwi 0, 35, 35, 3 826; CHECK: xxinsertw 34, 0, 8 827; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_ 828; CHECK-BE: xxsldwi 0, 35, 35, 2 829; CHECK-BE: xxinsertw 34, 0, 4 830 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7> 831 ret <4 x i32> %vecins 832} 833 834define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 835entry: 836; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_ 837; CHECK: xxsldwi 0, 35, 35, 2 838; CHECK: xxinsertw 34, 0, 4 839; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_ 840; CHECK-BE: xxsldwi 0, 35, 35, 3 841; CHECK-BE: xxinsertw 34, 0, 8 842 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 7> 843 ret <4 x i32> %vecins 844} 845 846define <4 x i32> @_Z7testInsILj2ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 847entry: 848; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_ 849; CHECK: xxsldwi 0, 35, 35, 1 850; CHECK: xxinsertw 34, 0, 4 851; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_ 852; CHECK-BE-NOT: xxsldwi 853; CHECK-BE: xxinsertw 34, 35, 8 854 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 7> 855 ret <4 x i32> %vecins 856} 857 858define <4 x i32> @_Z7testInsILj2ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 859entry: 860; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_ 861; CHECK-NOT: xxsldwi 862; CHECK: xxinsertw 34, 35, 4 863; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_ 864; CHECK-BE: xxsldwi 0, 35, 35, 1 865; CHECK-BE: xxinsertw 34, 0, 8 866 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 7> 867 ret <4 x i32> %vecins 868} 869 870define <4 x i32> @_Z7testInsILj2ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 871entry: 872; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_ 873; CHECK: xxsldwi 0, 35, 35, 3 874; CHECK: xxinsertw 34, 0, 4 875; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_ 876; CHECK-BE: xxsldwi 0, 35, 35, 2 877; CHECK-BE: xxinsertw 34, 0, 8 878 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7> 879 ret <4 x i32> %vecins 880} 881 882define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 883entry: 884; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_ 885; CHECK: xxsldwi 0, 35, 35, 2 886; CHECK: xxinsertw 34, 0, 0 887; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_ 888; CHECK-BE: xxsldwi 0, 35, 35, 3 889; CHECK-BE: xxinsertw 34, 0, 12 890 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 0> 891 ret <4 x i32> %vecins 892} 893 894define <4 x i32> @_Z7testInsILj3ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 895entry: 896; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_ 897; CHECK: xxsldwi 0, 35, 35, 1 898; CHECK: xxinsertw 34, 0, 0 899; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_ 900; CHECK-BE-NOT: xxsldwi 901; CHECK-BE: xxinsertw 34, 35, 12 902 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 1> 903 ret <4 x i32> %vecins 904} 905 906define <4 x i32> @_Z7testInsILj3ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 907entry: 908; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_ 909; CHECK-NOT: xxsldwi 910; CHECK: xxinsertw 34, 35, 0 911; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_ 912; CHECK-BE: xxsldwi 0, 35, 35, 1 913; CHECK-BE: xxinsertw 34, 0, 12 914 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 2> 915 ret <4 x i32> %vecins 916} 917 918define <4 x i32> @_Z7testInsILj3ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { 919entry: 920; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_ 921; CHECK: xxsldwi 0, 35, 35, 3 922; CHECK: xxinsertw 34, 0, 0 923; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_ 924; CHECK-BE: xxsldwi 0, 35, 35, 2 925; CHECK-BE: xxinsertw 34, 0, 12 926 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3> 927 ret <4 x i32> %vecins 928} 929define <4 x float> @testSameVecEl0BE(<4 x float> %a) { 930entry: 931; CHECK-BE-LABEL: testSameVecEl0BE 932; CHECK-BE: xxinsertw 34, 34, 0 933 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 5, i32 1, i32 2, i32 3> 934 ret <4 x float> %vecins 935} 936define <4 x float> @testSameVecEl2BE(<4 x float> %a) { 937entry: 938; CHECK-BE-LABEL: testSameVecEl2BE 939; CHECK-BE: xxinsertw 34, 34, 8 940 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 5, i32 3> 941 ret <4 x float> %vecins 942} 943define <4 x float> @testSameVecEl3BE(<4 x float> %a) { 944entry: 945; CHECK-BE-LABEL: testSameVecEl3BE 946; CHECK-BE: xxinsertw 34, 34, 12 947 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 5> 948 ret <4 x float> %vecins 949} 950define <4 x float> @testSameVecEl0LE(<4 x float> %a) { 951entry: 952; CHECK-LABEL: testSameVecEl0LE 953; CHECK: xxinsertw 34, 34, 12 954 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 6, i32 1, i32 2, i32 3> 955 ret <4 x float> %vecins 956} 957define <4 x float> @testSameVecEl1LE(<4 x float> %a) { 958entry: 959; CHECK-LABEL: testSameVecEl1LE 960; CHECK: xxinsertw 34, 34, 8 961 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3> 962 ret <4 x float> %vecins 963} 964define <4 x float> @testSameVecEl3LE(<4 x float> %a) { 965entry: 966; CHECK-LABEL: testSameVecEl3LE 967; CHECK: xxinsertw 34, 34, 0 968 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6> 969 ret <4 x float> %vecins 970} 971