1; RUN: llc < %s | FileCheck %s
2target datalayout = "E-m:e-i64:64-n32:64"
3target triple = "powerpc64-unknown-linux-gnu"
4
5; CHECK-LABEL: test:
6; CHECK: {{^}}.L[[test_BEGIN:.*]]:{{$}}
7
8; CHECK-LABEL: property_access1:
9; CHECK: {{^}}.L[[property_access1_BEGIN:.*]]:{{$}}
10
11; CHECK-LABEL: property_access2:
12; CHECK: {{^}}.L[[property_access2_BEGIN:.*]]:{{$}}
13
14; CHECK-LABEL: property_access3:
15; CHECK: {{^}}.L[[property_access3_BEGIN:.*]]:{{$}}
16
17; CHECK-LABEL: anyreg_test1:
18; CHECK: {{^}}.L[[anyreg_test1_BEGIN:.*]]:{{$}}
19
20; CHECK-LABEL: anyreg_test2:
21; CHECK: {{^}}.L[[anyreg_test2_BEGIN:.*]]:{{$}}
22
23; CHECK-LABEL: patchpoint_spilldef:
24; CHECK: {{^}}.L[[patchpoint_spilldef_BEGIN:.*]]:{{$}}
25
26; CHECK-LABEL: patchpoint_spillargs:
27; CHECK: {{^}}.L[[patchpoint_spillargs_BEGIN:.*]]:{{$}}
28
29
30; Stackmap Header: no constants - 6 callsites
31; CHECK-LABEL: .section	.llvm_stackmaps
32; CHECK-NEXT:  __LLVM_StackMaps:
33; Header
34; CHECK-NEXT:   .byte 1
35; CHECK-NEXT:   .byte 0
36; CHECK-NEXT:   .short 0
37; Num Functions
38; CHECK-NEXT:   .long 8
39; Num LargeConstants
40; CHECK-NEXT:   .long 0
41; Num Callsites
42; CHECK-NEXT:   .long 8
43
44; Functions and stack size
45; CHECK-NEXT:   .quad test
46; CHECK-NEXT:   .quad 128
47; CHECK-NEXT:   .quad property_access1
48; CHECK-NEXT:   .quad 128
49; CHECK-NEXT:   .quad property_access2
50; CHECK-NEXT:   .quad 128
51; CHECK-NEXT:   .quad property_access3
52; CHECK-NEXT:   .quad 128
53; CHECK-NEXT:   .quad anyreg_test1
54; CHECK-NEXT:   .quad 144
55; CHECK-NEXT:   .quad anyreg_test2
56; CHECK-NEXT:   .quad 144
57; CHECK-NEXT:   .quad patchpoint_spilldef
58; CHECK-NEXT:   .quad 256
59; CHECK-NEXT:   .quad patchpoint_spillargs
60; CHECK-NEXT:   .quad 288
61
62
63; test
64; CHECK:  .long   .L{{.*}}-.L[[test_BEGIN]]
65; CHECK-NEXT:   .short  0
66; 3 locations
67; CHECK-NEXT:   .short  3
68; Loc 0: Register
69; CHECK-NEXT:   .byte 1
70; CHECK-NEXT:   .byte 4
71; CHECK-NEXT:   .short {{[0-9]+}}
72; CHECK-NEXT:   .long 0
73; Loc 1: Register
74; CHECK-NEXT:   .byte 1
75; CHECK-NEXT:   .byte 4
76; CHECK-NEXT:   .short {{[0-9]+}}
77; CHECK-NEXT:   .long 0
78; Loc 2: Constant 3
79; CHECK-NEXT:   .byte 4
80; CHECK-NEXT:   .byte 8
81; CHECK-NEXT:   .short  0
82; CHECK-NEXT:   .long 3
83define i64 @test() nounwind ssp uwtable {
84entry:
85  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 40, i8* null, i32 2, i32 1, i32 2, i64 3)
86  ret i64 0
87}
88
89; property access 1 - %obj is an anyreg call argument and should therefore be in a register
90; CHECK:  .long   .L{{.*}}-.L[[property_access1_BEGIN]]
91; CHECK-NEXT:   .short  0
92; 2 locations
93; CHECK-NEXT:   .short  2
94; Loc 0: Register <-- this is the return register
95; CHECK-NEXT:   .byte 1
96; CHECK-NEXT:   .byte 8
97; CHECK-NEXT:   .short {{[0-9]+}}
98; CHECK-NEXT:   .long 0
99; Loc 1: Register
100; CHECK-NEXT:   .byte 1
101; CHECK-NEXT:   .byte 8
102; CHECK-NEXT:   .short {{[0-9]+}}
103; CHECK-NEXT:   .long 0
104define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
105entry:
106  %f = inttoptr i64 281474417671919 to i8*
107  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 40, i8* %f, i32 1, i8* %obj)
108  ret i64 %ret
109}
110
111; property access 2 - %obj is an anyreg call argument and should therefore be in a register
112; CHECK:  .long   .L{{.*}}-.L[[property_access2_BEGIN]]
113; CHECK-NEXT:   .short  0
114; 2 locations
115; CHECK-NEXT:   .short  2
116; Loc 0: Register <-- this is the return register
117; CHECK-NEXT:   .byte 1
118; CHECK-NEXT:   .byte 8
119; CHECK-NEXT:   .short {{[0-9]+}}
120; CHECK-NEXT:   .long 0
121; Loc 1: Register
122; CHECK-NEXT:   .byte 1
123; CHECK-NEXT:   .byte 8
124; CHECK-NEXT:   .short {{[0-9]+}}
125; CHECK-NEXT:   .long 0
126define i64 @property_access2() nounwind ssp uwtable {
127entry:
128  %obj = alloca i64, align 8
129  %f = inttoptr i64 281474417671919 to i8*
130  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 40, i8* %f, i32 1, i64* %obj)
131  ret i64 %ret
132}
133
134; property access 3 - %obj is a frame index
135; CHECK:  .long   .L{{.*}}-.L[[property_access3_BEGIN]]
136; CHECK-NEXT:   .short  0
137; 2 locations
138; CHECK-NEXT:   .short  2
139; Loc 0: Register <-- this is the return register
140; CHECK-NEXT:   .byte 1
141; CHECK-NEXT:   .byte 8
142; CHECK-NEXT:   .short {{[0-9]+}}
143; CHECK-NEXT:   .long 0
144; Loc 1: Direct FP - 8
145; CHECK-NEXT:   .byte 2
146; CHECK-NEXT:   .byte 8
147; CHECK-NEXT:   .short 31
148; CHECK-NEXT:   .long 112
149define i64 @property_access3() nounwind ssp uwtable {
150entry:
151  %obj = alloca i64, align 8
152  %f = inttoptr i64 281474417671919 to i8*
153  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 40, i8* %f, i32 0, i64* %obj)
154  ret i64 %ret
155}
156
157; anyreg_test1
158; CHECK:  .long   .L{{.*}}-.L[[anyreg_test1_BEGIN]]
159; CHECK-NEXT:   .short  0
160; 14 locations
161; CHECK-NEXT:   .short  14
162; Loc 0: Register <-- this is the return register
163; CHECK-NEXT:   .byte 1
164; CHECK-NEXT:   .byte 8
165; CHECK-NEXT:   .short {{[0-9]+}}
166; CHECK-NEXT:   .long 0
167; Loc 1: Register
168; CHECK-NEXT:   .byte 1
169; CHECK-NEXT:   .byte 8
170; CHECK-NEXT:   .short {{[0-9]+}}
171; CHECK-NEXT:   .long 0
172; Loc 2: Register
173; CHECK-NEXT:   .byte 1
174; CHECK-NEXT:   .byte 8
175; CHECK-NEXT:   .short {{[0-9]+}}
176; CHECK-NEXT:   .long 0
177; Loc 3: Register
178; CHECK-NEXT:   .byte 1
179; CHECK-NEXT:   .byte 8
180; CHECK-NEXT:   .short {{[0-9]+}}
181; CHECK-NEXT:   .long 0
182; Loc 4: Register
183; CHECK-NEXT:   .byte 1
184; CHECK-NEXT:   .byte 8
185; CHECK-NEXT:   .short {{[0-9]+}}
186; CHECK-NEXT:   .long 0
187; Loc 5: Register
188; CHECK-NEXT:   .byte 1
189; CHECK-NEXT:   .byte 8
190; CHECK-NEXT:   .short {{[0-9]+}}
191; CHECK-NEXT:   .long 0
192; Loc 6: Register
193; CHECK-NEXT:   .byte 1
194; CHECK-NEXT:   .byte 8
195; CHECK-NEXT:   .short {{[0-9]+}}
196; CHECK-NEXT:   .long 0
197; Loc 7: Register
198; CHECK-NEXT:   .byte 1
199; CHECK-NEXT:   .byte 8
200; CHECK-NEXT:   .short {{[0-9]+}}
201; CHECK-NEXT:   .long 0
202; Loc 8: Register
203; CHECK-NEXT:   .byte 1
204; CHECK-NEXT:   .byte 8
205; CHECK-NEXT:   .short {{[0-9]+}}
206; CHECK-NEXT:   .long 0
207; Loc 9: Register
208; CHECK-NEXT:   .byte 1
209; CHECK-NEXT:   .byte 8
210; CHECK-NEXT:   .short {{[0-9]+}}
211; CHECK-NEXT:   .long 0
212; Loc 10: Register
213; CHECK-NEXT:   .byte 1
214; CHECK-NEXT:   .byte 8
215; CHECK-NEXT:   .short {{[0-9]+}}
216; CHECK-NEXT:   .long 0
217; Loc 11: Register
218; CHECK-NEXT:   .byte 1
219; CHECK-NEXT:   .byte 8
220; CHECK-NEXT:   .short {{[0-9]+}}
221; CHECK-NEXT:   .long 0
222; Loc 12: Register
223; CHECK-NEXT:   .byte 1
224; CHECK-NEXT:   .byte 8
225; CHECK-NEXT:   .short {{[0-9]+}}
226; CHECK-NEXT:   .long 0
227; Loc 13: Register
228; CHECK-NEXT:   .byte 1
229; CHECK-NEXT:   .byte 8
230; CHECK-NEXT:   .short {{[0-9]+}}
231; CHECK-NEXT:   .long 0
232define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
233entry:
234  %f = inttoptr i64 281474417671919 to i8*
235  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 40, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
236  ret i64 %ret
237}
238
239; anyreg_test2
240; CHECK:  .long   .L{{.*}}-.L[[anyreg_test2_BEGIN]]
241; CHECK-NEXT:   .short  0
242; 14 locations
243; CHECK-NEXT:   .short  14
244; Loc 0: Register <-- this is the return register
245; CHECK-NEXT:   .byte 1
246; CHECK-NEXT:   .byte 8
247; CHECK-NEXT:   .short {{[0-9]+}}
248; CHECK-NEXT:   .long 0
249; Loc 1: Register
250; CHECK-NEXT:   .byte 1
251; CHECK-NEXT:   .byte 8
252; CHECK-NEXT:   .short {{[0-9]+}}
253; CHECK-NEXT:   .long 0
254; Loc 2: Register
255; CHECK-NEXT:   .byte 1
256; CHECK-NEXT:   .byte 8
257; CHECK-NEXT:   .short {{[0-9]+}}
258; CHECK-NEXT:   .long 0
259; Loc 3: Register
260; CHECK-NEXT:   .byte 1
261; CHECK-NEXT:   .byte 8
262; CHECK-NEXT:   .short {{[0-9]+}}
263; CHECK-NEXT:   .long 0
264; Loc 4: Register
265; CHECK-NEXT:   .byte 1
266; CHECK-NEXT:   .byte 8
267; CHECK-NEXT:   .short {{[0-9]+}}
268; CHECK-NEXT:   .long 0
269; Loc 5: Register
270; CHECK-NEXT:   .byte 1
271; CHECK-NEXT:   .byte 8
272; CHECK-NEXT:   .short {{[0-9]+}}
273; CHECK-NEXT:   .long 0
274; Loc 6: Register
275; CHECK-NEXT:   .byte 1
276; CHECK-NEXT:   .byte 8
277; CHECK-NEXT:   .short {{[0-9]+}}
278; CHECK-NEXT:   .long 0
279; Loc 7: Register
280; CHECK-NEXT:   .byte 1
281; CHECK-NEXT:   .byte 8
282; CHECK-NEXT:   .short {{[0-9]+}}
283; CHECK-NEXT:   .long 0
284; Loc 8: Register
285; CHECK-NEXT:   .byte 1
286; CHECK-NEXT:   .byte 8
287; CHECK-NEXT:   .short {{[0-9]+}}
288; CHECK-NEXT:   .long 0
289; Loc 9: Register
290; CHECK-NEXT:   .byte 1
291; CHECK-NEXT:   .byte 8
292; CHECK-NEXT:   .short {{[0-9]+}}
293; CHECK-NEXT:   .long 0
294; Loc 10: Register
295; CHECK-NEXT:   .byte 1
296; CHECK-NEXT:   .byte 8
297; CHECK-NEXT:   .short {{[0-9]+}}
298; CHECK-NEXT:   .long 0
299; Loc 11: Register
300; CHECK-NEXT:   .byte 1
301; CHECK-NEXT:   .byte 8
302; CHECK-NEXT:   .short {{[0-9]+}}
303; CHECK-NEXT:   .long 0
304; Loc 12: Register
305; CHECK-NEXT:   .byte 1
306; CHECK-NEXT:   .byte 8
307; CHECK-NEXT:   .short {{[0-9]+}}
308; CHECK-NEXT:   .long 0
309; Loc 13: Register
310; CHECK-NEXT:   .byte 1
311; CHECK-NEXT:   .byte 8
312; CHECK-NEXT:   .short {{[0-9]+}}
313; CHECK-NEXT:   .long 0
314define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
315entry:
316  %f = inttoptr i64 281474417671919 to i8*
317  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 40, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
318  ret i64 %ret
319}
320
321; Test spilling the return value of an anyregcc call.
322;
323; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
324;
325; CHECK: .long .L{{.*}}-.L[[patchpoint_spilldef_BEGIN]]
326; CHECK-NEXT: .short 0
327; CHECK-NEXT: .short 3
328; Loc 0: Register (some register that will be spilled to the stack)
329; CHECK-NEXT: .byte  1
330; CHECK-NEXT: .byte  8
331; CHECK-NEXT: .short {{[0-9]+}}
332; CHECK-NEXT: .long  0
333; Loc 1: Register
334; CHECK-NEXT: .byte  1
335; CHECK-NEXT: .byte  8
336; CHECK-NEXT: .short {{[0-9]+}}
337; CHECK-NEXT: .long  0
338; Loc 1: Register
339; CHECK-NEXT: .byte  1
340; CHECK-NEXT: .byte  8
341; CHECK-NEXT: .short {{[0-9]+}}
342; CHECK-NEXT: .long  0
343define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
344entry:
345  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 40, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
346  tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17
347},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
348  ret i64 %result
349}
350
351; Test spilling the arguments of an anyregcc call.
352;
353; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
354;
355; CHECK: .long .L{{.*}}-.L[[patchpoint_spillargs_BEGIN]]
356; CHECK-NEXT: .short 0
357; CHECK-NEXT: .short 5
358; Loc 0: Return a register
359; CHECK-NEXT: .byte  1
360; CHECK-NEXT: .byte  8
361; CHECK-NEXT: .short {{[0-9]+}}
362; CHECK-NEXT: .long  0
363; Loc 1: Arg0 in a Register
364; CHECK-NEXT: .byte  1
365; CHECK-NEXT: .byte  8
366; CHECK-NEXT: .short {{[0-9]+}}
367; CHECK-NEXT: .long  0
368; Loc 2: Arg1 in a Register
369; CHECK-NEXT: .byte  1
370; CHECK-NEXT: .byte  8
371; CHECK-NEXT: .short {{[0-9]+}}
372; CHECK-NEXT: .long  0
373; Loc 3: Arg2 spilled to FP -96
374; CHECK-NEXT: .byte  3
375; CHECK-NEXT: .byte  8
376; CHECK-NEXT: .short 31
377; CHECK-NEXT: .long 128
378; Loc 4: Arg3 spilled to FP - 88
379; CHECK-NEXT: .byte  3
380; CHECK-NEXT: .byte  8
381; CHECK-NEXT: .short 31
382; CHECK-NEXT: .long 136
383define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
384entry:
385  tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17
386},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
387  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 40, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
388  ret i64 %result
389}
390
391declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
392declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
393