1; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mtriple=x86_64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK -check-prefix=SSE41
2; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx -mtriple=x86_64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK -check-prefix=AVX
3
4
5define double @test1_add(double %A, double %B) {
6  %1 = bitcast double %A to <2 x i32>
7  %2 = bitcast double %B to <2 x i32>
8  %add = add <2 x i32> %1, %2
9  %3 = bitcast <2 x i32> %add to double
10  ret double %3
11}
12; CHECK-LABEL: test1_add
13; SSE41: paddd
14; AVX: vpaddd
15; CHECK-NEXT: ret
16
17
18define double @test2_add(double %A, double %B) {
19  %1 = bitcast double %A to <4 x i16>
20  %2 = bitcast double %B to <4 x i16>
21  %add = add <4 x i16> %1, %2
22  %3 = bitcast <4 x i16> %add to double
23  ret double %3
24}
25; CHECK-LABEL: test2_add
26; SSE41: paddw
27; AVX: vpaddw
28; CHECK-NEXT: ret
29
30define double @test3_add(double %A, double %B) {
31  %1 = bitcast double %A to <8 x i8>
32  %2 = bitcast double %B to <8 x i8>
33  %add = add <8 x i8> %1, %2
34  %3 = bitcast <8 x i8> %add to double
35  ret double %3
36}
37; CHECK-LABEL: test3_add
38; SSE41: paddb
39; AVX: vpaddb
40; CHECK-NEXT: ret
41
42
43define double @test1_sub(double %A, double %B) {
44  %1 = bitcast double %A to <2 x i32>
45  %2 = bitcast double %B to <2 x i32>
46  %sub = sub <2 x i32> %1, %2
47  %3 = bitcast <2 x i32> %sub to double
48  ret double %3
49}
50; CHECK-LABEL: test1_sub
51; SSE41: psubd
52; AVX: vpsubd
53; CHECK-NEXT: ret
54
55
56define double @test2_sub(double %A, double %B) {
57  %1 = bitcast double %A to <4 x i16>
58  %2 = bitcast double %B to <4 x i16>
59  %sub = sub <4 x i16> %1, %2
60  %3 = bitcast <4 x i16> %sub to double
61  ret double %3
62}
63; CHECK-LABEL: test2_sub
64; SSE41: psubw
65; AVX: vpsubw
66; CHECK-NEXT: ret
67
68
69define double @test3_sub(double %A, double %B) {
70  %1 = bitcast double %A to <8 x i8>
71  %2 = bitcast double %B to <8 x i8>
72  %sub = sub <8 x i8> %1, %2
73  %3 = bitcast <8 x i8> %sub to double
74  ret double %3
75}
76; CHECK-LABEL: test3_sub
77; SSE41: psubb
78; AVX: vpsubb
79; CHECK-NEXT: ret
80
81
82define double @test1_mul(double %A, double %B) {
83  %1 = bitcast double %A to <2 x i32>
84  %2 = bitcast double %B to <2 x i32>
85  %mul = mul <2 x i32> %1, %2
86  %3 = bitcast <2 x i32> %mul to double
87  ret double %3
88}
89; CHECK-LABEL: test1_mul
90; SSE41: pmulld
91; AVX: vpmulld
92; CHECK-NEXT: ret
93
94
95define double @test2_mul(double %A, double %B) {
96  %1 = bitcast double %A to <4 x i16>
97  %2 = bitcast double %B to <4 x i16>
98  %mul = mul <4 x i16> %1, %2
99  %3 = bitcast <4 x i16> %mul to double
100  ret double %3
101}
102; CHECK-LABEL: test2_mul
103; SSE41: pmullw
104; AVX: vpmullw
105; CHECK-NEXT: ret
106
107; There is no legal ISD::MUL with type MVT::v8i16.
108define double @test3_mul(double %A, double %B) {
109  %1 = bitcast double %A to <8 x i8>
110  %2 = bitcast double %B to <8 x i8>
111  %mul = mul <8 x i8> %1, %2
112  %3 = bitcast <8 x i8> %mul to double
113  ret double %3
114}
115; CHECK-LABEL: test3_mul
116; CHECK: pmullw
117; CHECK-NEXT: pshufb
118; CHECK-NEXT: ret
119
120
121define double @test1_and(double %A, double %B) {
122  %1 = bitcast double %A to <2 x i32>
123  %2 = bitcast double %B to <2 x i32>
124  %and = and <2 x i32> %1, %2
125  %3 = bitcast <2 x i32> %and to double
126  ret double %3
127}
128; CHECK-LABEL: test1_and
129; SSE41: andps
130; AVX: vandps
131; CHECK-NEXT: ret
132
133
134define double @test2_and(double %A, double %B) {
135  %1 = bitcast double %A to <4 x i16>
136  %2 = bitcast double %B to <4 x i16>
137  %and = and <4 x i16> %1, %2
138  %3 = bitcast <4 x i16> %and to double
139  ret double %3
140}
141; CHECK-LABEL: test2_and
142; SSE41: andps
143; AVX: vandps
144; CHECK-NEXT: ret
145
146
147define double @test3_and(double %A, double %B) {
148  %1 = bitcast double %A to <8 x i8>
149  %2 = bitcast double %B to <8 x i8>
150  %and = and <8 x i8> %1, %2
151  %3 = bitcast <8 x i8> %and to double
152  ret double %3
153}
154; CHECK-LABEL: test3_and
155; SSE41: andps
156; AVX: vandps
157; CHECK-NEXT: ret
158
159
160define double @test1_or(double %A, double %B) {
161  %1 = bitcast double %A to <2 x i32>
162  %2 = bitcast double %B to <2 x i32>
163  %or = or <2 x i32> %1, %2
164  %3 = bitcast <2 x i32> %or to double
165  ret double %3
166}
167; CHECK-LABEL: test1_or
168; SSE41: orps
169; AVX: vorps
170; CHECK-NEXT: ret
171
172
173define double @test2_or(double %A, double %B) {
174  %1 = bitcast double %A to <4 x i16>
175  %2 = bitcast double %B to <4 x i16>
176  %or = or <4 x i16> %1, %2
177  %3 = bitcast <4 x i16> %or to double
178  ret double %3
179}
180; CHECK-LABEL: test2_or
181; SSE41: orps
182; AVX: vorps
183; CHECK-NEXT: ret
184
185
186define double @test3_or(double %A, double %B) {
187  %1 = bitcast double %A to <8 x i8>
188  %2 = bitcast double %B to <8 x i8>
189  %or = or <8 x i8> %1, %2
190  %3 = bitcast <8 x i8> %or to double
191  ret double %3
192}
193; CHECK-LABEL: test3_or
194; SSE41: orps
195; AVX: vorps
196; CHECK-NEXT: ret
197
198
199define double @test1_xor(double %A, double %B) {
200  %1 = bitcast double %A to <2 x i32>
201  %2 = bitcast double %B to <2 x i32>
202  %xor = xor <2 x i32> %1, %2
203  %3 = bitcast <2 x i32> %xor to double
204  ret double %3
205}
206; CHECK-LABEL: test1_xor
207; SSE41: xorps
208; AVX: vxorps
209; CHECK-NEXT: ret
210
211
212define double @test2_xor(double %A, double %B) {
213  %1 = bitcast double %A to <4 x i16>
214  %2 = bitcast double %B to <4 x i16>
215  %xor = xor <4 x i16> %1, %2
216  %3 = bitcast <4 x i16> %xor to double
217  ret double %3
218}
219; CHECK-LABEL: test2_xor
220; SSE41: xorps
221; AVX: vxorps
222; CHECK-NEXT: ret
223
224
225define double @test3_xor(double %A, double %B) {
226  %1 = bitcast double %A to <8 x i8>
227  %2 = bitcast double %B to <8 x i8>
228  %xor = xor <8 x i8> %1, %2
229  %3 = bitcast <8 x i8> %xor to double
230  ret double %3
231}
232; CHECK-LABEL: test3_xor
233; SSE41: xorps
234; AVX: vxorps
235; CHECK-NEXT: ret
236
237
238define double @test_fadd(double %A, double %B) {
239  %1 = bitcast double %A to <2 x float>
240  %2 = bitcast double %B to <2 x float>
241  %add = fadd <2 x float> %1, %2
242  %3 = bitcast <2 x float> %add to double
243  ret double %3
244}
245; CHECK-LABEL: test_fadd
246; SSE41: addps
247; AVX: vaddps
248; CHECK-NEXT: ret
249
250define double @test_fsub(double %A, double %B) {
251  %1 = bitcast double %A to <2 x float>
252  %2 = bitcast double %B to <2 x float>
253  %sub = fsub <2 x float> %1, %2
254  %3 = bitcast <2 x float> %sub to double
255  ret double %3
256}
257; CHECK-LABEL: test_fsub
258; SSE41: subps
259; AVX: vsubps
260; CHECK-NEXT: ret
261
262define double @test_fmul(double %A, double %B) {
263  %1 = bitcast double %A to <2 x float>
264  %2 = bitcast double %B to <2 x float>
265  %mul = fmul <2 x float> %1, %2
266  %3 = bitcast <2 x float> %mul to double
267  ret double %3
268}
269; CHECK-LABEL: test_fmul
270; SSE41: mulps
271; AVX: vmulps
272; CHECK-NEXT: ret
273
274