1# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
2
3#==---------------------------------------------------------------------------==
4# 5.4.2 Logical (immediate)
5#==---------------------------------------------------------------------------==
6
70x00 0x00 0x00 0x12
80x00 0x00 0x40 0x92
90x41 0x0c 0x00 0x12
100x41 0x0c 0x40 0x92
110xbf 0xec 0x7c 0x92
120x00 0x00 0x00 0x72
130x00 0x00 0x40 0xf2
140x41 0x0c 0x00 0x72
150x41 0x0c 0x40 0xf2
160x5f 0x0c 0x40 0xf2
17
18# CHECK: and  w0, w0, #0x1
19# CHECK: and  x0, x0, #0x1
20# CHECK: and  w1, w2, #0xf
21# CHECK: and  x1, x2, #0xf
22# CHECK: and  sp, x5, #0xfffffffffffffff0
23# CHECK: ands w0, w0, #0x1
24# CHECK: ands x0, x0, #0x1
25# CHECK: ands w1, w2, #0xf
26# CHECK: ands x1, x2, #0xf
27# CHECK: tst x2, #0xf
28
290x41 0x00 0x12 0x52
300x41 0x00 0x71 0xd2
310x5f 0x00 0x71 0xd2
32
33# CHECK: eor w1, w2, #0x4000
34# CHECK: eor x1, x2, #0x8000
35# CHECK: eor sp, x2, #0x8000
36
370x41 0x00 0x12 0x32
380x41 0x00 0x71 0xb2
390x5f 0x00 0x71 0xb2
40
41# CHECK: orr w1, w2, #0x4000
42# CHECK: orr x1, x2, #0x8000
43# CHECK: orr sp, x2, #0x8000
44
45#==---------------------------------------------------------------------------==
46# 5.5.3 Logical (shifted register)
47#==---------------------------------------------------------------------------==
48
490x41 0x00 0x03 0x0a
500x41 0x00 0x03 0x8a
510x41 0x08 0x03 0x0a
520x41 0x08 0x03 0x8a
530x41 0x08 0x43 0x0a
540x41 0x08 0x43 0x8a
550x41 0x08 0x83 0x0a
560x41 0x08 0x83 0x8a
570x41 0x08 0xc3 0x0a
580x41 0x08 0xc3 0x8a
59
60# CHECK: and  w1, w2, w3
61# CHECK: and  x1, x2, x3
62# CHECK: and  w1, w2, w3, lsl #2
63# CHECK: and  x1, x2, x3, lsl #2
64# CHECK: and  w1, w2, w3, lsr #2
65# CHECK: and  x1, x2, x3, lsr #2
66# CHECK: and  w1, w2, w3, asr #2
67# CHECK: and  x1, x2, x3, asr #2
68# CHECK: and  w1, w2, w3, ror #2
69# CHECK: and  x1, x2, x3, ror #2
70
710x41 0x00 0x03 0x6a
720x41 0x00 0x03 0xea
730x41 0x08 0x03 0x6a
740x41 0x08 0x03 0xea
750x41 0x08 0x43 0x6a
760x41 0x08 0x43 0xea
770x41 0x08 0x83 0x6a
780x41 0x08 0x83 0xea
790x41 0x08 0xc3 0x6a
800x41 0x08 0xc3 0xea
81
82# CHECK: ands w1, w2, w3
83# CHECK: ands x1, x2, x3
84# CHECK: ands w1, w2, w3, lsl #2
85# CHECK: ands x1, x2, x3, lsl #2
86# CHECK: ands w1, w2, w3, lsr #2
87# CHECK: ands x1, x2, x3, lsr #2
88# CHECK: ands w1, w2, w3, asr #2
89# CHECK: ands x1, x2, x3, asr #2
90# CHECK: ands w1, w2, w3, ror #2
91# CHECK: ands x1, x2, x3, ror #2
92
930x41 0x00 0x23 0x0a
940x41 0x00 0x23 0x8a
950x41 0x0c 0x23 0x0a
960x41 0x0c 0x23 0x8a
970x41 0x0c 0x63 0x0a
980x41 0x0c 0x63 0x8a
990x41 0x0c 0xa3 0x0a
1000x41 0x0c 0xa3 0x8a
1010x41 0x0c 0xe3 0x0a
1020x41 0x0c 0xe3 0x8a
103
104# CHECK: bic w1, w2, w3
105# CHECK: bic x1, x2, x3
106# CHECK: bic w1, w2, w3, lsl #3
107# CHECK: bic x1, x2, x3, lsl #3
108# CHECK: bic w1, w2, w3, lsr #3
109# CHECK: bic x1, x2, x3, lsr #3
110# CHECK: bic w1, w2, w3, asr #3
111# CHECK: bic x1, x2, x3, asr #3
112# CHECK: bic w1, w2, w3, ror #3
113# CHECK: bic x1, x2, x3, ror #3
114
1150x41 0x00 0x23 0x6a
1160x41 0x00 0x23 0xea
1170x41 0x0c 0x23 0x6a
1180x41 0x0c 0x23 0xea
1190x41 0x0c 0x63 0x6a
1200x41 0x0c 0x63 0xea
1210x41 0x0c 0xa3 0x6a
1220x41 0x0c 0xa3 0xea
1230x41 0x0c 0xe3 0x6a
1240x41 0x0c 0xe3 0xea
125
126# CHECK: bics w1, w2, w3
127# CHECK: bics x1, x2, x3
128# CHECK: bics w1, w2, w3, lsl #3
129# CHECK: bics x1, x2, x3, lsl #3
130# CHECK: bics w1, w2, w3, lsr #3
131# CHECK: bics x1, x2, x3, lsr #3
132# CHECK: bics w1, w2, w3, asr #3
133# CHECK: bics x1, x2, x3, asr #3
134# CHECK: bics w1, w2, w3, ror #3
135# CHECK: bics x1, x2, x3, ror #3
136
1370x41 0x00 0x23 0x4a
1380x41 0x00 0x23 0xca
1390x41 0x10 0x23 0x4a
1400x41 0x10 0x23 0xca
1410x41 0x10 0x63 0x4a
1420x41 0x10 0x63 0xca
1430x41 0x10 0xa3 0x4a
1440x41 0x10 0xa3 0xca
1450x41 0x10 0xe3 0x4a
1460x41 0x10 0xe3 0xca
147
148# CHECK: eon w1, w2, w3
149# CHECK: eon x1, x2, x3
150# CHECK: eon w1, w2, w3, lsl #4
151# CHECK: eon x1, x2, x3, lsl #4
152# CHECK: eon w1, w2, w3, lsr #4
153# CHECK: eon x1, x2, x3, lsr #4
154# CHECK: eon w1, w2, w3, asr #4
155# CHECK: eon x1, x2, x3, asr #4
156# CHECK: eon w1, w2, w3, ror #4
157# CHECK: eon x1, x2, x3, ror #4
158
1590x41 0x00 0x03 0x4a
1600x41 0x00 0x03 0xca
1610x41 0x14 0x03 0x4a
1620x41 0x14 0x03 0xca
1630x41 0x14 0x43 0x4a
1640x41 0x14 0x43 0xca
1650x41 0x14 0x83 0x4a
1660x41 0x14 0x83 0xca
1670x41 0x14 0xc3 0x4a
1680x41 0x14 0xc3 0xca
169
170# CHECK: eor w1, w2, w3
171# CHECK: eor x1, x2, x3
172# CHECK: eor w1, w2, w3, lsl #5
173# CHECK: eor x1, x2, x3, lsl #5
174# CHECK: eor w1, w2, w3, lsr #5
175# CHECK: eor x1, x2, x3, lsr #5
176# CHECK: eor w1, w2, w3, asr #5
177# CHECK: eor x1, x2, x3, asr #5
178# CHECK: eor w1, w2, w3, ror #5
179# CHECK: eor x1, x2, x3, ror #5
180
1810x41 0x00 0x03 0x2a
1820x41 0x00 0x03 0xaa
1830x41 0x18 0x03 0x2a
1840x41 0x18 0x03 0xaa
1850x41 0x18 0x43 0x2a
1860x41 0x18 0x43 0xaa
1870x41 0x18 0x83 0x2a
1880x41 0x18 0x83 0xaa
1890x41 0x18 0xc3 0x2a
1900x41 0x18 0xc3 0xaa
191
192# CHECK: orr w1, w2, w3
193# CHECK: orr x1, x2, x3
194# CHECK: orr w1, w2, w3, lsl #6
195# CHECK: orr x1, x2, x3, lsl #6
196# CHECK: orr w1, w2, w3, lsr #6
197# CHECK: orr x1, x2, x3, lsr #6
198# CHECK: orr w1, w2, w3, asr #6
199# CHECK: orr x1, x2, x3, asr #6
200# CHECK: orr w1, w2, w3, ror #6
201# CHECK: orr x1, x2, x3, ror #6
202
2030x41 0x00 0x23 0x2a
2040x41 0x00 0x23 0xaa
2050x41 0x1c 0x23 0x2a
2060x41 0x1c 0x23 0xaa
2070x41 0x1c 0x63 0x2a
2080x41 0x1c 0x63 0xaa
2090x41 0x1c 0xa3 0x2a
2100x41 0x1c 0xa3 0xaa
2110x41 0x1c 0xe3 0x2a
2120x41 0x1c 0xe3 0xaa
213
214# CHECK: orn w1, w2, w3
215# CHECK: orn x1, x2, x3
216# CHECK: orn w1, w2, w3, lsl #7
217# CHECK: orn x1, x2, x3, lsl #7
218# CHECK: orn w1, w2, w3, lsr #7
219# CHECK: orn x1, x2, x3, lsr #7
220# CHECK: orn w1, w2, w3, asr #7
221# CHECK: orn x1, x2, x3, asr #7
222# CHECK: orn w1, w2, w3, ror #7
223# CHECK: orn x1, x2, x3, ror #7
224