1 /* 2 * Copyright © 2016 Bas Nieuwenhuizen 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #ifndef AC_NIR_TO_LLVM_H 25 #define AC_NIR_TO_LLVM_H 26 27 #include <stdbool.h> 28 #include "llvm-c/Core.h" 29 #include "llvm-c/TargetMachine.h" 30 #include "amd_family.h" 31 #include "../vulkan/radv_descriptor_set.h" 32 #include "ac_shader_info.h" 33 #include "compiler/shader_enums.h" 34 struct ac_shader_binary; 35 struct ac_shader_config; 36 struct nir_shader; 37 struct radv_pipeline_layout; 38 39 struct ac_llvm_context; 40 struct ac_shader_abi; 41 42 struct ac_vs_variant_key { 43 uint32_t instance_rate_inputs; 44 uint32_t as_es:1; 45 uint32_t as_ls:1; 46 uint32_t export_prim_id:1; 47 }; 48 49 struct ac_tes_variant_key { 50 uint32_t as_es:1; 51 uint32_t export_prim_id:1; 52 }; 53 54 struct ac_tcs_variant_key { 55 struct ac_vs_variant_key vs_key; 56 unsigned primitive_mode; 57 unsigned input_vertices; 58 uint32_t tes_reads_tess_factors:1; 59 }; 60 61 struct ac_fs_variant_key { 62 uint32_t col_format; 63 uint8_t log2_ps_iter_samples; 64 uint8_t log2_num_samples; 65 uint32_t is_int8; 66 uint32_t is_int10; 67 uint32_t multisample : 1; 68 }; 69 70 struct ac_shader_variant_key { 71 union { 72 struct ac_vs_variant_key vs; 73 struct ac_fs_variant_key fs; 74 struct ac_tes_variant_key tes; 75 struct ac_tcs_variant_key tcs; 76 }; 77 bool has_multiview_view_index; 78 }; 79 80 struct ac_nir_compiler_options { 81 struct radv_pipeline_layout *layout; 82 struct ac_shader_variant_key key; 83 bool unsafe_math; 84 bool supports_spill; 85 bool clamp_shadow_reference; 86 bool dump_preoptir; 87 enum radeon_family family; 88 enum chip_class chip_class; 89 }; 90 91 struct ac_userdata_info { 92 int8_t sgpr_idx; 93 uint8_t num_sgprs; 94 bool indirect; 95 uint32_t indirect_offset; 96 }; 97 98 enum ac_ud_index { 99 AC_UD_SCRATCH_RING_OFFSETS = 0, 100 AC_UD_PUSH_CONSTANTS = 1, 101 AC_UD_INDIRECT_DESCRIPTOR_SETS = 2, 102 AC_UD_VIEW_INDEX = 3, 103 AC_UD_SHADER_START = 4, 104 AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START, 105 AC_UD_VS_BASE_VERTEX_START_INSTANCE, 106 AC_UD_VS_LS_TCS_IN_LAYOUT, 107 AC_UD_VS_MAX_UD, 108 AC_UD_PS_SAMPLE_POS_OFFSET = AC_UD_SHADER_START, 109 AC_UD_PS_MAX_UD, 110 AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START, 111 AC_UD_CS_MAX_UD, 112 AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_VS_MAX_UD, 113 AC_UD_GS_MAX_UD, 114 AC_UD_TCS_OFFCHIP_LAYOUT = AC_UD_VS_MAX_UD, 115 AC_UD_TCS_MAX_UD, 116 AC_UD_TES_OFFCHIP_LAYOUT = AC_UD_SHADER_START, 117 AC_UD_TES_MAX_UD, 118 AC_UD_MAX_UD = AC_UD_TCS_MAX_UD, 119 }; 120 121 /* descriptor index into scratch ring offsets */ 122 #define RING_SCRATCH 0 123 #define RING_ESGS_VS 1 124 #define RING_ESGS_GS 2 125 #define RING_GSVS_VS 3 126 #define RING_GSVS_GS 4 127 #define RING_HS_TESS_FACTOR 5 128 #define RING_HS_TESS_OFFCHIP 6 129 #define RING_PS_SAMPLE_POSITIONS 7 130 131 // Match MAX_SETS from radv_descriptor_set.h 132 #define AC_UD_MAX_SETS MAX_SETS 133 134 struct ac_userdata_locations { 135 struct ac_userdata_info descriptor_sets[AC_UD_MAX_SETS]; 136 struct ac_userdata_info shader_data[AC_UD_MAX_UD]; 137 }; 138 139 struct ac_vs_output_info { 140 uint8_t vs_output_param_offset[VARYING_SLOT_MAX]; 141 uint8_t clip_dist_mask; 142 uint8_t cull_dist_mask; 143 uint8_t param_exports; 144 bool writes_pointsize; 145 bool writes_layer; 146 bool writes_viewport_index; 147 bool export_prim_id; 148 uint32_t export_mask; 149 unsigned pos_exports; 150 }; 151 152 struct ac_es_output_info { 153 uint32_t esgs_itemsize; 154 }; 155 156 struct ac_shader_variant_info { 157 struct ac_userdata_locations user_sgprs_locs; 158 struct ac_shader_info info; 159 unsigned num_user_sgprs; 160 unsigned num_input_sgprs; 161 unsigned num_input_vgprs; 162 bool need_indirect_descriptor_sets; 163 struct { 164 struct { 165 struct ac_vs_output_info outinfo; 166 struct ac_es_output_info es_info; 167 unsigned vgpr_comp_cnt; 168 bool as_es; 169 bool as_ls; 170 uint64_t outputs_written; 171 } vs; 172 struct { 173 unsigned num_interp; 174 uint32_t input_mask; 175 uint32_t flat_shaded_mask; 176 bool has_pcoord; 177 bool can_discard; 178 bool writes_z; 179 bool writes_stencil; 180 bool writes_sample_mask; 181 bool early_fragment_test; 182 bool writes_memory; 183 bool prim_id_input; 184 bool layer_input; 185 } fs; 186 struct { 187 unsigned block_size[3]; 188 } cs; 189 struct { 190 unsigned vertices_in; 191 unsigned vertices_out; 192 unsigned output_prim; 193 unsigned invocations; 194 unsigned gsvs_vertex_size; 195 unsigned max_gsvs_emit_size; 196 unsigned es_type; /* GFX9: VS or TES */ 197 } gs; 198 struct { 199 unsigned tcs_vertices_out; 200 /* Which outputs are actually written */ 201 uint64_t outputs_written; 202 /* Which patch outputs are actually written */ 203 uint32_t patch_outputs_written; 204 205 } tcs; 206 struct { 207 struct ac_vs_output_info outinfo; 208 struct ac_es_output_info es_info; 209 bool as_es; 210 unsigned primitive_mode; 211 enum gl_tess_spacing spacing; 212 bool ccw; 213 bool point_mode; 214 } tes; 215 }; 216 }; 217 218 void ac_compile_nir_shader(LLVMTargetMachineRef tm, 219 struct ac_shader_binary *binary, 220 struct ac_shader_config *config, 221 struct ac_shader_variant_info *shader_info, 222 struct nir_shader *const *nir, 223 int nir_count, 224 const struct ac_nir_compiler_options *options, 225 bool dump_shader); 226 227 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm, 228 struct nir_shader *geom_shader, 229 struct ac_shader_binary *binary, 230 struct ac_shader_config *config, 231 struct ac_shader_variant_info *shader_info, 232 const struct ac_nir_compiler_options *options, 233 bool dump_shader); 234 235 struct nir_to_llvm_context; 236 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi, 237 struct nir_shader *nir, struct nir_to_llvm_context *nctx); 238 239 #endif /* AC_NIR_TO_LLVM_H */ 240