1 /**************************************************************************
2  *
3  * Copyright 2013 Advanced Micro Devices, Inc.
4  * All Rights Reserved.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the
15  * next paragraph) shall be included in all copies or substantial portions
16  * of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  *
26  **************************************************************************/
27 
28 #include <unistd.h>
29 
30 #include "util/u_memory.h"
31 #include "util/u_video.h"
32 
33 #include "vl/vl_defines.h"
34 #include "vl/vl_video_buffer.h"
35 
36 #include "radeonsi/si_pipe.h"
37 #include "radeon_video.h"
38 #include "radeon_vce.h"
39 
40 /* generate an stream handle */
si_vid_alloc_stream_handle()41 unsigned si_vid_alloc_stream_handle()
42 {
43 	static unsigned counter = 0;
44 	unsigned stream_handle = 0;
45 	unsigned pid = getpid();
46 	int i;
47 
48 	for (i = 0; i < 32; ++i)
49 		stream_handle |= ((pid >> i) & 1) << (31 - i);
50 
51 	stream_handle ^= ++counter;
52 	return stream_handle;
53 }
54 
55 /* create a buffer in the winsys */
si_vid_create_buffer(struct pipe_screen * screen,struct rvid_buffer * buffer,unsigned size,unsigned usage)56 bool si_vid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer,
57 			  unsigned size, unsigned usage)
58 {
59 	memset(buffer, 0, sizeof(*buffer));
60 	buffer->usage = usage;
61 
62 	/* Hardware buffer placement restrictions require the kernel to be
63 	 * able to move buffers around individually, so request a
64 	 * non-sub-allocated buffer.
65 	 */
66 	buffer->res = (struct r600_resource *)
67 		pipe_buffer_create(screen, PIPE_BIND_SHARED,
68 				   usage, size);
69 
70 	return buffer->res != NULL;
71 }
72 
73 /* destroy a buffer */
si_vid_destroy_buffer(struct rvid_buffer * buffer)74 void si_vid_destroy_buffer(struct rvid_buffer *buffer)
75 {
76 	r600_resource_reference(&buffer->res, NULL);
77 }
78 
79 /* reallocate a buffer, preserving its content */
si_vid_resize_buffer(struct pipe_screen * screen,struct radeon_winsys_cs * cs,struct rvid_buffer * new_buf,unsigned new_size)80 bool si_vid_resize_buffer(struct pipe_screen *screen, struct radeon_winsys_cs *cs,
81 			  struct rvid_buffer *new_buf, unsigned new_size)
82 {
83 	struct si_screen *sscreen = (struct si_screen *)screen;
84 	struct radeon_winsys* ws = sscreen->ws;
85 	unsigned bytes = MIN2(new_buf->res->buf->size, new_size);
86 	struct rvid_buffer old_buf = *new_buf;
87 	void *src = NULL, *dst = NULL;
88 
89 	if (!si_vid_create_buffer(screen, new_buf, new_size, new_buf->usage))
90 		goto error;
91 
92 	src = ws->buffer_map(old_buf.res->buf, cs, PIPE_TRANSFER_READ);
93 	if (!src)
94 		goto error;
95 
96 	dst = ws->buffer_map(new_buf->res->buf, cs, PIPE_TRANSFER_WRITE);
97 	if (!dst)
98 		goto error;
99 
100 	memcpy(dst, src, bytes);
101 	if (new_size > bytes) {
102 		new_size -= bytes;
103 		dst += bytes;
104 		memset(dst, 0, new_size);
105 	}
106 	ws->buffer_unmap(new_buf->res->buf);
107 	ws->buffer_unmap(old_buf.res->buf);
108 	si_vid_destroy_buffer(&old_buf);
109 	return true;
110 
111 error:
112 	if (src)
113 		ws->buffer_unmap(old_buf.res->buf);
114 	si_vid_destroy_buffer(new_buf);
115 	*new_buf = old_buf;
116 	return false;
117 }
118 
119 /* clear the buffer with zeros */
si_vid_clear_buffer(struct pipe_context * context,struct rvid_buffer * buffer)120 void si_vid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
121 {
122 	struct r600_common_context *rctx = (struct r600_common_context*)context;
123 
124 	rctx->dma_clear_buffer(context, &buffer->res->b.b, 0,
125 			       buffer->res->buf->size, 0);
126 	context->flush(context, NULL, 0);
127 }
128 
129 /**
130  * join surfaces into the same buffer with identical tiling params
131  * sumup their sizes and replace the backend buffers with a single bo
132  */
si_vid_join_surfaces(struct r600_common_context * rctx,struct pb_buffer ** buffers[VL_NUM_COMPONENTS],struct radeon_surf * surfaces[VL_NUM_COMPONENTS])133 void si_vid_join_surfaces(struct r600_common_context *rctx,
134 			  struct pb_buffer** buffers[VL_NUM_COMPONENTS],
135 			  struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
136 {
137 	struct radeon_winsys* ws;
138 	unsigned best_tiling, best_wh, off;
139 	unsigned size, alignment;
140 	struct pb_buffer *pb;
141 	unsigned i, j;
142 
143 	ws = rctx->ws;
144 
145 	for (i = 0, best_tiling = 0, best_wh = ~0; i < VL_NUM_COMPONENTS; ++i) {
146 		unsigned wh;
147 
148 		if (!surfaces[i])
149 			continue;
150 
151 		if (rctx->chip_class < GFX9) {
152 			/* choose the smallest bank w/h for now */
153 			wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh;
154 			if (wh < best_wh) {
155 				best_wh = wh;
156 				best_tiling = i;
157 			}
158 		}
159 	}
160 
161 	for (i = 0, off = 0; i < VL_NUM_COMPONENTS; ++i) {
162 		if (!surfaces[i])
163 			continue;
164 
165 		/* adjust the texture layer offsets */
166 		off = align(off, surfaces[i]->surf_alignment);
167 
168 		if (rctx->chip_class < GFX9) {
169 			/* copy the tiling parameters */
170 			surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw;
171 			surfaces[i]->u.legacy.bankh = surfaces[best_tiling]->u.legacy.bankh;
172 			surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea;
173 			surfaces[i]->u.legacy.tile_split = surfaces[best_tiling]->u.legacy.tile_split;
174 
175 			for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.legacy.level); ++j)
176 				surfaces[i]->u.legacy.level[j].offset += off;
177 		} else {
178 			surfaces[i]->u.gfx9.surf_offset += off;
179 			for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.gfx9.offset); ++j)
180 				surfaces[i]->u.gfx9.offset[j] += off;
181 		}
182 
183 		off += surfaces[i]->surf_size;
184 	}
185 
186 	for (i = 0, size = 0, alignment = 0; i < VL_NUM_COMPONENTS; ++i) {
187 		if (!buffers[i] || !*buffers[i])
188 			continue;
189 
190 		size = align(size, (*buffers[i])->alignment);
191 		size += (*buffers[i])->size;
192 		alignment = MAX2(alignment, (*buffers[i])->alignment * 1);
193 	}
194 
195 	if (!size)
196 		return;
197 
198 	/* TODO: 2D tiling workaround */
199 	alignment *= 2;
200 
201 	pb = ws->buffer_create(ws, size, alignment, RADEON_DOMAIN_VRAM,
202 			       RADEON_FLAG_GTT_WC);
203 	if (!pb)
204 		return;
205 
206 	for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
207 		if (!buffers[i] || !*buffers[i])
208 			continue;
209 
210 		pb_reference(buffers[i], pb);
211 	}
212 
213 	pb_reference(&pb, NULL);
214 }
215