1 /*
2 * Copyright © 2014-2015 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * DOC: Render command list generation
26 *
27 * In the VC4 driver, render command list generation is performed by the
28 * kernel instead of userspace. We do this because validating a
29 * user-submitted command list is hard to get right and has high CPU overhead,
30 * while the number of valid configurations for render command lists is
31 * actually fairly low.
32 */
33
34 #include "vc4_drv.h"
35 #include "vc4_packet.h"
36
37 struct vc4_rcl_setup {
38 struct drm_gem_cma_object *color_read;
39 struct drm_gem_cma_object *color_write;
40 struct drm_gem_cma_object *zs_read;
41 struct drm_gem_cma_object *zs_write;
42 struct drm_gem_cma_object *msaa_color_write;
43 struct drm_gem_cma_object *msaa_zs_write;
44
45 struct drm_gem_cma_object *rcl;
46 u32 next_offset;
47 };
48
rcl_u8(struct vc4_rcl_setup * setup,u8 val)49 static inline void rcl_u8(struct vc4_rcl_setup *setup, u8 val)
50 {
51 *(u8 *)(setup->rcl->vaddr + setup->next_offset) = val;
52 setup->next_offset += 1;
53 }
54
rcl_u16(struct vc4_rcl_setup * setup,u16 val)55 static inline void rcl_u16(struct vc4_rcl_setup *setup, u16 val)
56 {
57 *(u16 *)(setup->rcl->vaddr + setup->next_offset) = val;
58 setup->next_offset += 2;
59 }
60
rcl_u32(struct vc4_rcl_setup * setup,u32 val)61 static inline void rcl_u32(struct vc4_rcl_setup *setup, u32 val)
62 {
63 *(u32 *)(setup->rcl->vaddr + setup->next_offset) = val;
64 setup->next_offset += 4;
65 }
66
67 /*
68 * Emits a no-op STORE_TILE_BUFFER_GENERAL.
69 *
70 * If we emit a PACKET_TILE_COORDINATES, it must be followed by a store of
71 * some sort before another load is triggered.
72 */
vc4_store_before_load(struct vc4_rcl_setup * setup)73 static void vc4_store_before_load(struct vc4_rcl_setup *setup)
74 {
75 rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
76 rcl_u16(setup,
77 VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_NONE,
78 VC4_LOADSTORE_TILE_BUFFER_BUFFER) |
79 VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR |
80 VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR |
81 VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR);
82 rcl_u32(setup, 0); /* no address, since we're in None mode */
83 }
84
85 /*
86 * Calculates the physical address of the start of a tile in a RCL surface.
87 *
88 * Unlike the other load/store packets,
89 * VC4_PACKET_LOAD/STORE_FULL_RES_TILE_BUFFER don't look at the tile
90 * coordinates packet, and instead just store to the address given.
91 */
vc4_full_res_offset(struct vc4_exec_info * exec,struct drm_gem_cma_object * bo,struct drm_vc4_submit_rcl_surface * surf,uint8_t x,uint8_t y)92 static uint32_t vc4_full_res_offset(struct vc4_exec_info *exec,
93 struct drm_gem_cma_object *bo,
94 struct drm_vc4_submit_rcl_surface *surf,
95 uint8_t x, uint8_t y)
96 {
97 return bo->paddr + surf->offset + VC4_TILE_BUFFER_SIZE *
98 (DIV_ROUND_UP(exec->args->width, exec->tile_width) * y + x);
99 }
100
101 /*
102 * Emits a PACKET_TILE_COORDINATES if one isn't already pending.
103 *
104 * The tile coordinates packet triggers a pending load if there is one, are
105 * used for clipping during rendering, and determine where loads/stores happen
106 * relative to their base address.
107 */
vc4_tile_coordinates(struct vc4_rcl_setup * setup,uint32_t x,uint32_t y)108 static void vc4_tile_coordinates(struct vc4_rcl_setup *setup,
109 uint32_t x, uint32_t y)
110 {
111 rcl_u8(setup, VC4_PACKET_TILE_COORDINATES);
112 rcl_u8(setup, x);
113 rcl_u8(setup, y);
114 }
115
emit_tile(struct vc4_exec_info * exec,struct vc4_rcl_setup * setup,uint8_t x,uint8_t y,bool first,bool last)116 static void emit_tile(struct vc4_exec_info *exec,
117 struct vc4_rcl_setup *setup,
118 uint8_t x, uint8_t y, bool first, bool last)
119 {
120 struct drm_vc4_submit_cl *args = exec->args;
121 bool has_bin = args->bin_cl_size != 0;
122
123 /* Note that the load doesn't actually occur until the
124 * tile coords packet is processed, and only one load
125 * may be outstanding at a time.
126 */
127 if (setup->color_read) {
128 if (args->color_read.flags &
129 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
130 rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER);
131 rcl_u32(setup,
132 vc4_full_res_offset(exec, setup->color_read,
133 &args->color_read, x, y) |
134 VC4_LOADSTORE_FULL_RES_DISABLE_ZS);
135 } else {
136 rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
137 rcl_u16(setup, args->color_read.bits);
138 rcl_u32(setup, setup->color_read->paddr +
139 args->color_read.offset);
140 }
141 }
142
143 if (setup->zs_read) {
144 if (args->zs_read.flags &
145 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
146 rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER);
147 rcl_u32(setup,
148 vc4_full_res_offset(exec, setup->zs_read,
149 &args->zs_read, x, y) |
150 VC4_LOADSTORE_FULL_RES_DISABLE_COLOR);
151 } else {
152 if (setup->color_read) {
153 /* Exec previous load. */
154 vc4_tile_coordinates(setup, x, y);
155 vc4_store_before_load(setup);
156 }
157
158 rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
159 rcl_u16(setup, args->zs_read.bits);
160 rcl_u32(setup, setup->zs_read->paddr +
161 args->zs_read.offset);
162 }
163 }
164
165 /* Clipping depends on tile coordinates having been
166 * emitted, so we always need one here.
167 */
168 vc4_tile_coordinates(setup, x, y);
169
170 /* Wait for the binner before jumping to the first
171 * tile's lists.
172 */
173 if (first && has_bin)
174 rcl_u8(setup, VC4_PACKET_WAIT_ON_SEMAPHORE);
175
176 if (has_bin) {
177 rcl_u8(setup, VC4_PACKET_BRANCH_TO_SUB_LIST);
178 rcl_u32(setup, (exec->tile_bo->paddr +
179 exec->tile_alloc_offset +
180 (y * exec->bin_tiles_x + x) * 32));
181 }
182
183 if (setup->msaa_color_write) {
184 bool last_tile_write = (!setup->msaa_zs_write &&
185 !setup->zs_write &&
186 !setup->color_write);
187 uint32_t bits = VC4_LOADSTORE_FULL_RES_DISABLE_ZS;
188
189 if (!last_tile_write)
190 bits |= VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL;
191 else if (last)
192 bits |= VC4_LOADSTORE_FULL_RES_EOF;
193 rcl_u8(setup, VC4_PACKET_STORE_FULL_RES_TILE_BUFFER);
194 rcl_u32(setup,
195 vc4_full_res_offset(exec, setup->msaa_color_write,
196 &args->msaa_color_write, x, y) |
197 bits);
198 }
199
200 if (setup->msaa_zs_write) {
201 bool last_tile_write = (!setup->zs_write &&
202 !setup->color_write);
203 uint32_t bits = VC4_LOADSTORE_FULL_RES_DISABLE_COLOR;
204
205 if (setup->msaa_color_write)
206 vc4_tile_coordinates(setup, x, y);
207 if (!last_tile_write)
208 bits |= VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL;
209 else if (last)
210 bits |= VC4_LOADSTORE_FULL_RES_EOF;
211 rcl_u8(setup, VC4_PACKET_STORE_FULL_RES_TILE_BUFFER);
212 rcl_u32(setup,
213 vc4_full_res_offset(exec, setup->msaa_zs_write,
214 &args->msaa_zs_write, x, y) |
215 bits);
216 }
217
218 if (setup->zs_write) {
219 bool last_tile_write = !setup->color_write;
220
221 if (setup->msaa_color_write || setup->msaa_zs_write)
222 vc4_tile_coordinates(setup, x, y);
223
224 rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
225 rcl_u16(setup, args->zs_write.bits |
226 (last_tile_write ?
227 0 : VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR));
228 rcl_u32(setup,
229 (setup->zs_write->paddr + args->zs_write.offset) |
230 ((last && last_tile_write) ?
231 VC4_LOADSTORE_TILE_BUFFER_EOF : 0));
232 }
233
234 if (setup->color_write) {
235 if (setup->msaa_color_write || setup->msaa_zs_write ||
236 setup->zs_write) {
237 vc4_tile_coordinates(setup, x, y);
238 }
239
240 if (last)
241 rcl_u8(setup, VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF);
242 else
243 rcl_u8(setup, VC4_PACKET_STORE_MS_TILE_BUFFER);
244 }
245 }
246
vc4_create_rcl_bo(struct drm_device * dev,struct vc4_exec_info * exec,struct vc4_rcl_setup * setup)247 static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec,
248 struct vc4_rcl_setup *setup)
249 {
250 struct drm_vc4_submit_cl *args = exec->args;
251 bool has_bin = args->bin_cl_size != 0;
252 uint8_t min_x_tile = args->min_x_tile;
253 uint8_t min_y_tile = args->min_y_tile;
254 uint8_t max_x_tile = args->max_x_tile;
255 uint8_t max_y_tile = args->max_y_tile;
256 uint8_t xtiles = max_x_tile - min_x_tile + 1;
257 uint8_t ytiles = max_y_tile - min_y_tile + 1;
258 uint8_t xi, yi;
259 uint32_t size, loop_body_size;
260 bool positive_x = true;
261 bool positive_y = true;
262
263 if (args->flags & VC4_SUBMIT_CL_FIXED_RCL_ORDER) {
264 if (!(args->flags & VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X))
265 positive_x = false;
266 if (!(args->flags & VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y))
267 positive_y = false;
268 }
269
270 size = VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE;
271 loop_body_size = VC4_PACKET_TILE_COORDINATES_SIZE;
272
273 if (args->flags & VC4_SUBMIT_CL_USE_CLEAR_COLOR) {
274 size += VC4_PACKET_CLEAR_COLORS_SIZE +
275 VC4_PACKET_TILE_COORDINATES_SIZE +
276 VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE;
277 }
278
279 if (setup->color_read) {
280 if (args->color_read.flags &
281 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
282 loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE;
283 } else {
284 loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE;
285 }
286 }
287 if (setup->zs_read) {
288 if (args->zs_read.flags &
289 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
290 loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE;
291 } else {
292 if (setup->color_read &&
293 !(args->color_read.flags &
294 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES)) {
295 loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE;
296 loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE;
297 }
298 loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE;
299 }
300 }
301
302 if (has_bin) {
303 size += VC4_PACKET_WAIT_ON_SEMAPHORE_SIZE;
304 loop_body_size += VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE;
305 }
306
307 if (setup->msaa_color_write)
308 loop_body_size += VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE;
309 if (setup->msaa_zs_write)
310 loop_body_size += VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE;
311
312 if (setup->zs_write)
313 loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE;
314 if (setup->color_write)
315 loop_body_size += VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE;
316
317 /* We need a VC4_PACKET_TILE_COORDINATES in between each store. */
318 loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE *
319 ((setup->msaa_color_write != NULL) +
320 (setup->msaa_zs_write != NULL) +
321 (setup->color_write != NULL) +
322 (setup->zs_write != NULL) - 1);
323
324 size += xtiles * ytiles * loop_body_size;
325
326 setup->rcl = drm_gem_cma_create(dev, size);
327 if (!setup->rcl)
328 return -ENOMEM;
329 list_addtail(&to_vc4_bo(&setup->rcl->base)->unref_head,
330 &exec->unref_list);
331
332 rcl_u8(setup, VC4_PACKET_TILE_RENDERING_MODE_CONFIG);
333 rcl_u32(setup,
334 (setup->color_write ? (setup->color_write->paddr +
335 args->color_write.offset) :
336 0));
337 rcl_u16(setup, args->width);
338 rcl_u16(setup, args->height);
339 rcl_u16(setup, args->color_write.bits);
340
341 /* The tile buffer gets cleared when the previous tile is stored. If
342 * the clear values changed between frames, then the tile buffer has
343 * stale clear values in it, so we have to do a store in None mode (no
344 * writes) so that we trigger the tile buffer clear.
345 */
346 if (args->flags & VC4_SUBMIT_CL_USE_CLEAR_COLOR) {
347 rcl_u8(setup, VC4_PACKET_CLEAR_COLORS);
348 rcl_u32(setup, args->clear_color[0]);
349 rcl_u32(setup, args->clear_color[1]);
350 rcl_u32(setup, args->clear_z);
351 rcl_u8(setup, args->clear_s);
352
353 vc4_tile_coordinates(setup, 0, 0);
354
355 rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
356 rcl_u16(setup, VC4_LOADSTORE_TILE_BUFFER_NONE);
357 rcl_u32(setup, 0); /* no address, since we're in None mode */
358 }
359
360 for (yi = 0; yi < ytiles; yi++) {
361 int y = positive_y ? min_y_tile + yi : max_y_tile - yi;
362 for (xi = 0; xi < xtiles; xi++) {
363 int x = positive_x ? min_x_tile + xi : max_x_tile - xi;
364 bool first = (xi == 0 && yi == 0);
365 bool last = (xi == xtiles - 1 && yi == ytiles - 1);
366
367 emit_tile(exec, setup, x, y, first, last);
368 }
369 }
370
371 BUG_ON(setup->next_offset != size);
372 exec->ct1ca = setup->rcl->paddr;
373 exec->ct1ea = setup->rcl->paddr + setup->next_offset;
374
375 return 0;
376 }
377
vc4_full_res_bounds_check(struct vc4_exec_info * exec,struct drm_gem_cma_object * obj,struct drm_vc4_submit_rcl_surface * surf)378 static int vc4_full_res_bounds_check(struct vc4_exec_info *exec,
379 struct drm_gem_cma_object *obj,
380 struct drm_vc4_submit_rcl_surface *surf)
381 {
382 struct drm_vc4_submit_cl *args = exec->args;
383 u32 render_tiles_stride = DIV_ROUND_UP(exec->args->width,
384 exec->tile_width);
385
386 if (surf->offset > obj->base.size) {
387 DRM_ERROR("surface offset %d > BO size %zd\n",
388 surf->offset, obj->base.size);
389 return -EINVAL;
390 }
391
392 if ((obj->base.size - surf->offset) / VC4_TILE_BUFFER_SIZE <
393 render_tiles_stride * args->max_y_tile + args->max_x_tile) {
394 DRM_ERROR("MSAA tile %d, %d out of bounds "
395 "(bo size %zd, offset %d).\n",
396 args->max_x_tile, args->max_y_tile,
397 obj->base.size,
398 surf->offset);
399 return -EINVAL;
400 }
401
402 return 0;
403 }
404
vc4_rcl_msaa_surface_setup(struct vc4_exec_info * exec,struct drm_gem_cma_object ** obj,struct drm_vc4_submit_rcl_surface * surf)405 static int vc4_rcl_msaa_surface_setup(struct vc4_exec_info *exec,
406 struct drm_gem_cma_object **obj,
407 struct drm_vc4_submit_rcl_surface *surf)
408 {
409 if (surf->flags != 0 || surf->bits != 0) {
410 DRM_ERROR("MSAA surface had nonzero flags/bits\n");
411 return -EINVAL;
412 }
413
414 if (surf->hindex == ~0)
415 return 0;
416
417 *obj = vc4_use_bo(exec, surf->hindex);
418 if (!*obj)
419 return -EINVAL;
420
421 if (surf->offset & 0xf) {
422 DRM_ERROR("MSAA write must be 16b aligned.\n");
423 return -EINVAL;
424 }
425
426 return vc4_full_res_bounds_check(exec, *obj, surf);
427 }
428
vc4_rcl_surface_setup(struct vc4_exec_info * exec,struct drm_gem_cma_object ** obj,struct drm_vc4_submit_rcl_surface * surf)429 static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
430 struct drm_gem_cma_object **obj,
431 struct drm_vc4_submit_rcl_surface *surf)
432 {
433 uint8_t tiling = VC4_GET_FIELD(surf->bits,
434 VC4_LOADSTORE_TILE_BUFFER_TILING);
435 uint8_t buffer = VC4_GET_FIELD(surf->bits,
436 VC4_LOADSTORE_TILE_BUFFER_BUFFER);
437 uint8_t format = VC4_GET_FIELD(surf->bits,
438 VC4_LOADSTORE_TILE_BUFFER_FORMAT);
439 int cpp;
440 int ret;
441
442 if (surf->flags & ~VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
443 DRM_ERROR("Extra flags set\n");
444 return -EINVAL;
445 }
446
447 if (surf->hindex == ~0)
448 return 0;
449
450 *obj = vc4_use_bo(exec, surf->hindex);
451 if (!*obj)
452 return -EINVAL;
453
454 if (surf->flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
455 if (surf == &exec->args->zs_write) {
456 DRM_ERROR("general zs write may not be a full-res.\n");
457 return -EINVAL;
458 }
459
460 if (surf->bits != 0) {
461 DRM_ERROR("load/store general bits set with "
462 "full res load/store.\n");
463 return -EINVAL;
464 }
465
466 ret = vc4_full_res_bounds_check(exec, *obj, surf);
467 if (!ret)
468 return ret;
469
470 return 0;
471 }
472
473 if (surf->bits & ~(VC4_LOADSTORE_TILE_BUFFER_TILING_MASK |
474 VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK |
475 VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK)) {
476 DRM_ERROR("Unknown bits in load/store: 0x%04x\n",
477 surf->bits);
478 return -EINVAL;
479 }
480
481 if (tiling > VC4_TILING_FORMAT_LT) {
482 DRM_ERROR("Bad tiling format\n");
483 return -EINVAL;
484 }
485
486 if (buffer == VC4_LOADSTORE_TILE_BUFFER_ZS) {
487 if (format != 0) {
488 DRM_ERROR("No color format should be set for ZS\n");
489 return -EINVAL;
490 }
491 cpp = 4;
492 } else if (buffer == VC4_LOADSTORE_TILE_BUFFER_COLOR) {
493 switch (format) {
494 case VC4_LOADSTORE_TILE_BUFFER_BGR565:
495 case VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER:
496 cpp = 2;
497 break;
498 case VC4_LOADSTORE_TILE_BUFFER_RGBA8888:
499 cpp = 4;
500 break;
501 default:
502 DRM_ERROR("Bad tile buffer format\n");
503 return -EINVAL;
504 }
505 } else {
506 DRM_ERROR("Bad load/store buffer %d.\n", buffer);
507 return -EINVAL;
508 }
509
510 if (surf->offset & 0xf) {
511 DRM_ERROR("load/store buffer must be 16b aligned.\n");
512 return -EINVAL;
513 }
514
515 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling,
516 exec->args->width, exec->args->height, cpp)) {
517 return -EINVAL;
518 }
519
520 return 0;
521 }
522
523 static int
vc4_rcl_render_config_surface_setup(struct vc4_exec_info * exec,struct vc4_rcl_setup * setup,struct drm_gem_cma_object ** obj,struct drm_vc4_submit_rcl_surface * surf)524 vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec,
525 struct vc4_rcl_setup *setup,
526 struct drm_gem_cma_object **obj,
527 struct drm_vc4_submit_rcl_surface *surf)
528 {
529 uint8_t tiling = VC4_GET_FIELD(surf->bits,
530 VC4_RENDER_CONFIG_MEMORY_FORMAT);
531 uint8_t format = VC4_GET_FIELD(surf->bits,
532 VC4_RENDER_CONFIG_FORMAT);
533 int cpp;
534
535 if (surf->flags != 0) {
536 DRM_ERROR("No flags supported on render config.\n");
537 return -EINVAL;
538 }
539
540 if (surf->bits & ~(VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK |
541 VC4_RENDER_CONFIG_FORMAT_MASK |
542 VC4_RENDER_CONFIG_MS_MODE_4X |
543 VC4_RENDER_CONFIG_DECIMATE_MODE_4X)) {
544 DRM_ERROR("Unknown bits in render config: 0x%04x\n",
545 surf->bits);
546 return -EINVAL;
547 }
548
549 if (surf->hindex == ~0)
550 return 0;
551
552 *obj = vc4_use_bo(exec, surf->hindex);
553 if (!*obj)
554 return -EINVAL;
555
556 if (tiling > VC4_TILING_FORMAT_LT) {
557 DRM_ERROR("Bad tiling format\n");
558 return -EINVAL;
559 }
560
561 switch (format) {
562 case VC4_RENDER_CONFIG_FORMAT_BGR565_DITHERED:
563 case VC4_RENDER_CONFIG_FORMAT_BGR565:
564 cpp = 2;
565 break;
566 case VC4_RENDER_CONFIG_FORMAT_RGBA8888:
567 cpp = 4;
568 break;
569 default:
570 DRM_ERROR("Bad tile buffer format\n");
571 return -EINVAL;
572 }
573
574 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling,
575 exec->args->width, exec->args->height, cpp)) {
576 return -EINVAL;
577 }
578
579 return 0;
580 }
581
vc4_get_rcl(struct drm_device * dev,struct vc4_exec_info * exec)582 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec)
583 {
584 struct vc4_rcl_setup setup = {0};
585 struct drm_vc4_submit_cl *args = exec->args;
586 bool has_bin = args->bin_cl_size != 0;
587 int ret;
588
589 if (args->min_x_tile > args->max_x_tile ||
590 args->min_y_tile > args->max_y_tile) {
591 DRM_ERROR("Bad render tile set (%d,%d)-(%d,%d)\n",
592 args->min_x_tile, args->min_y_tile,
593 args->max_x_tile, args->max_y_tile);
594 return -EINVAL;
595 }
596
597 if (has_bin &&
598 (args->max_x_tile > exec->bin_tiles_x ||
599 args->max_y_tile > exec->bin_tiles_y)) {
600 DRM_ERROR("Render tiles (%d,%d) outside of bin config "
601 "(%d,%d)\n",
602 args->max_x_tile, args->max_y_tile,
603 exec->bin_tiles_x, exec->bin_tiles_y);
604 return -EINVAL;
605 }
606
607 ret = vc4_rcl_render_config_surface_setup(exec, &setup,
608 &setup.color_write,
609 &args->color_write);
610 if (ret)
611 return ret;
612
613 ret = vc4_rcl_surface_setup(exec, &setup.color_read, &args->color_read);
614 if (ret)
615 return ret;
616
617 ret = vc4_rcl_surface_setup(exec, &setup.zs_read, &args->zs_read);
618 if (ret)
619 return ret;
620
621 ret = vc4_rcl_surface_setup(exec, &setup.zs_write, &args->zs_write);
622 if (ret)
623 return ret;
624
625 ret = vc4_rcl_msaa_surface_setup(exec, &setup.msaa_color_write,
626 &args->msaa_color_write);
627 if (ret)
628 return ret;
629
630 ret = vc4_rcl_msaa_surface_setup(exec, &setup.msaa_zs_write,
631 &args->msaa_zs_write);
632 if (ret)
633 return ret;
634
635 /* We shouldn't even have the job submitted to us if there's no
636 * surface to write out.
637 */
638 if (!setup.color_write && !setup.zs_write &&
639 !setup.msaa_color_write && !setup.msaa_zs_write) {
640 DRM_ERROR("RCL requires color or Z/S write\n");
641 return -EINVAL;
642 }
643
644 return vc4_create_rcl_bo(dev, exec, &setup);
645 }
646