1 /*
2 * Copyright (c) 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24
25 #include "intel_batchbuffer.h"
26 #include "intel_fbo.h"
27 #include "intel_mipmap_tree.h"
28
29 #include "brw_context.h"
30 #include "brw_state.h"
31 #include "brw_defines.h"
32
33 #include "main/mtypes.h"
34 #include "main/fbobject.h"
35 #include "main/glformats.h"
36
37 void
gen6_emit_depth_stencil_hiz(struct brw_context * brw,struct intel_mipmap_tree * depth_mt,uint32_t depth_offset,uint32_t depthbuffer_format,uint32_t depth_surface_type,struct intel_mipmap_tree * stencil_mt,bool hiz,bool separate_stencil,uint32_t width,uint32_t height,uint32_t tile_x,uint32_t tile_y)38 gen6_emit_depth_stencil_hiz(struct brw_context *brw,
39 struct intel_mipmap_tree *depth_mt,
40 uint32_t depth_offset, uint32_t depthbuffer_format,
41 uint32_t depth_surface_type,
42 struct intel_mipmap_tree *stencil_mt,
43 bool hiz, bool separate_stencil,
44 uint32_t width, uint32_t height,
45 uint32_t tile_x, uint32_t tile_y)
46 {
47 struct gl_context *ctx = &brw->ctx;
48 struct gl_framebuffer *fb = ctx->DrawBuffer;
49 uint32_t surftype;
50 unsigned int depth = 1;
51 GLenum gl_target = GL_TEXTURE_2D;
52 unsigned int lod;
53 const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
54 const struct intel_renderbuffer *irb = NULL;
55 const struct gl_renderbuffer *rb = NULL;
56
57 /* Enable the hiz bit if we're doing separate stencil, because it and the
58 * separate stencil bit must have the same value. From Section 2.11.5.6.1.1
59 * 3DSTATE_DEPTH_BUFFER, Bit 1.21 "Separate Stencil Enable":
60 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
61 * Enable must also be enabled.
62 *
63 * [DevGT]: This field must be set to the same value (enabled or
64 * disabled) as Hierarchical Depth Buffer Enable
65 */
66 bool enable_hiz_ss = hiz || separate_stencil;
67
68 brw_emit_depth_stall_flushes(brw);
69
70 irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
71 if (!irb)
72 irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
73 rb = (struct gl_renderbuffer*) irb;
74
75 if (rb) {
76 depth = MAX2(irb->layer_count, 1);
77 if (rb->TexImage)
78 gl_target = rb->TexImage->TexObject->Target;
79 }
80
81 switch (gl_target) {
82 case GL_TEXTURE_CUBE_MAP_ARRAY:
83 case GL_TEXTURE_CUBE_MAP:
84 /* The PRM claims that we should use BRW_SURFACE_CUBE for this
85 * situation, but experiments show that gl_Layer doesn't work when we do
86 * this. So we use BRW_SURFACE_2D, since for rendering purposes this is
87 * equivalent.
88 */
89 surftype = BRW_SURFACE_2D;
90 depth *= 6;
91 break;
92 case GL_TEXTURE_3D:
93 assert(mt);
94 depth = mt->surf.logical_level0_px.depth;
95 /* fallthrough */
96 default:
97 surftype = translate_tex_target(gl_target);
98 break;
99 }
100
101 const unsigned min_array_element = irb ? irb->mt_layer : 0;
102
103 lod = irb ? irb->mt_level - irb->mt->first_level : 0;
104
105 if (mt) {
106 width = mt->surf.logical_level0_px.width;
107 height = mt->surf.logical_level0_px.height;
108 }
109
110 BEGIN_BATCH(7);
111 /* 3DSTATE_DEPTH_BUFFER dw0 */
112 OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
113
114 /* 3DSTATE_DEPTH_BUFFER dw1 */
115 OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
116 (depthbuffer_format << 18) |
117 ((enable_hiz_ss ? 1 : 0) << 21) | /* separate stencil enable */
118 ((enable_hiz_ss ? 1 : 0) << 22) | /* hiz enable */
119 (BRW_TILEWALK_YMAJOR << 26) |
120 (1 << 27) |
121 (surftype << 29));
122
123 /* 3DSTATE_DEPTH_BUFFER dw2 */
124 if (depth_mt) {
125 OUT_RELOC(depth_mt->bo, RELOC_WRITE, 0);
126 } else {
127 OUT_BATCH(0);
128 }
129
130 /* 3DSTATE_DEPTH_BUFFER dw3 */
131 OUT_BATCH(((width - 1) << 6) |
132 ((height - 1) << 19) |
133 lod << 2);
134
135 /* 3DSTATE_DEPTH_BUFFER dw4 */
136 OUT_BATCH((depth - 1) << 21 |
137 min_array_element << 10 |
138 (depth - 1) << 1);
139
140 /* 3DSTATE_DEPTH_BUFFER dw5 */
141 OUT_BATCH(0);
142 assert(tile_x == 0 && tile_y == 0);
143
144 /* 3DSTATE_DEPTH_BUFFER dw6 */
145 OUT_BATCH(0);
146
147 ADVANCE_BATCH();
148
149 if (hiz || separate_stencil) {
150 /*
151 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
152 * stencil enable' and 'hiz enable' bits were set. Therefore we must
153 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
154 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
155 * failure to do so causes hangs on gen5 and a stall on gen6.
156 */
157
158 /* Emit hiz buffer. */
159 if (hiz) {
160 assert(depth_mt);
161
162 uint32_t offset;
163 isl_surf_get_image_offset_B_tile_sa(&depth_mt->hiz_buf->surf,
164 lod, 0, 0, &offset, NULL, NULL);
165
166 BEGIN_BATCH(3);
167 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
168 OUT_BATCH(depth_mt->hiz_buf->surf.row_pitch - 1);
169 OUT_RELOC(depth_mt->hiz_buf->bo, RELOC_WRITE, offset);
170 ADVANCE_BATCH();
171 } else {
172 BEGIN_BATCH(3);
173 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
174 OUT_BATCH(0);
175 OUT_BATCH(0);
176 ADVANCE_BATCH();
177 }
178
179 /* Emit stencil buffer. */
180 if (separate_stencil) {
181 assert(stencil_mt->format == MESA_FORMAT_S_UINT8);
182 assert(stencil_mt->surf.size > 0);
183
184 uint32_t offset;
185 isl_surf_get_image_offset_B_tile_sa(&stencil_mt->surf,
186 lod, 0, 0, &offset, NULL, NULL);
187
188 BEGIN_BATCH(3);
189 OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
190 OUT_BATCH(stencil_mt->surf.row_pitch - 1);
191 OUT_RELOC(stencil_mt->bo, RELOC_WRITE, offset);
192 ADVANCE_BATCH();
193 } else {
194 BEGIN_BATCH(3);
195 OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
196 OUT_BATCH(0);
197 OUT_BATCH(0);
198 ADVANCE_BATCH();
199 }
200 }
201
202 /*
203 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
204 * params must be emitted.
205 *
206 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
207 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
208 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
209 */
210 BEGIN_BATCH(2);
211 OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 |
212 GEN5_DEPTH_CLEAR_VALID |
213 (2 - 2));
214 if (depth_mt) {
215 OUT_BATCH(brw_convert_depth_value(depth_mt->format,
216 depth_mt->fast_clear_color.f32[0]));
217 } else {
218 OUT_BATCH(0);
219 }
220 ADVANCE_BATCH();
221 }
222