1=pod
2
3=head1 NAME
4
5llc - LLVM static compiler
6
7=head1 SYNOPSIS
8
9B<llc> [I<options>] [I<filename>]
10
11=head1 DESCRIPTION
12
13The B<llc> command compiles LLVM source inputs into assembly language for a
14specified architecture.  The assembly language output can then be passed through
15a native assembler and linker to generate a native executable.
16
17The choice of architecture for the output assembly code is automatically
18determined from the input file, unless the B<-march> option is used to override
19the default.
20
21=head1 OPTIONS
22
23If I<filename> is - or omitted, B<llc> reads from standard input.  Otherwise, it
24will from I<filename>.  Inputs can be in either the LLVM assembly language
25format (.ll) or the LLVM bitcode format (.bc).
26
27If the B<-o> option is omitted, then B<llc> will send its output to standard
28output if the input is from standard input.  If the B<-o> option specifies -,
29then the output will also be sent to standard output.
30
31If no B<-o> option is specified and an input file other than - is specified,
32then B<llc> creates the output filename by taking the input filename,
33removing any existing F<.bc> extension, and adding a F<.s> suffix.
34
35Other B<llc> options are as follows:
36
37=head2 End-user Options
38
39=over
40
41=item B<-help>
42
43Print a summary of command line options.
44
45=item B<-O>=I<uint>
46
47Generate code at different optimization levels. These correspond to the I<-O0>,
48I<-O1>, I<-O2>, I<-O3>, and I<-O4> optimization levels used by B<llvm-gcc> and
49B<clang>.
50
51=item B<-mtriple>=I<target triple>
52
53Override the target triple specified in the input file with the specified
54string.
55
56=item B<-march>=I<arch>
57
58Specify the architecture for which to generate assembly, overriding the target
59encoded in the input file.  See the output of B<llc -help> for a list of
60valid architectures.  By default this is inferred from the target triple or
61autodetected to the current architecture.
62
63=item B<-mcpu>=I<cpuname>
64
65Specify a specific chip in the current architecture to generate code for.
66By default this is inferred from the target triple and autodetected to
67the current architecture.  For a list of available CPUs, use:
68B<llvm-as E<lt> /dev/null | llc -march=xyz -mcpu=help>
69
70=item B<-mattr>=I<a1,+a2,-a3,...>
71
72Override or control specific attributes of the target, such as whether SIMD
73operations are enabled or not.  The default set of attributes is set by the
74current CPU.  For a list of available attributes, use:
75B<llvm-as E<lt> /dev/null | llc -march=xyz -mattr=help>
76
77=item B<--disable-fp-elim>
78
79Disable frame pointer elimination optimization.
80
81=item B<--disable-excess-fp-precision>
82
83Disable optimizations that may produce excess precision for floating point.
84Note that this option can dramatically slow down code on some systems
85(e.g. X86).
86
87=item B<--enable-no-infs-fp-math>
88
89Enable optimizations that assume no Inf values.
90
91=item B<--enable-no-nans-fp-math>
92
93Enable optimizations that assume no NAN values.
94
95=item B<--enable-unsafe-fp-math>
96
97Enable optimizations that make unsafe assumptions about IEEE math (e.g. that
98addition is associative) or may not work for all input ranges.  These
99optimizations allow the code generator to make use of some instructions which
100would otherwise not be usable (such as fsin on X86).
101
102=item B<--enable-correct-eh-support>
103
104Instruct the B<lowerinvoke> pass to insert code for correct exception handling
105support.  This is expensive and is by default omitted for efficiency.
106
107=item B<--stats>
108
109Print statistics recorded by code-generation passes.
110
111=item B<--time-passes>
112
113Record the amount of time needed for each pass and print a report to standard
114error.
115
116=item B<--load>=F<dso_path>
117
118Dynamically load F<dso_path> (a path to a dynamically shared object) that
119implements an LLVM target. This will permit the target name to be used with the
120B<-march> option so that code can be generated for that target.
121
122=back
123
124=head2 Tuning/Configuration Options
125
126=over
127
128=item B<--print-machineinstrs>
129
130Print generated machine code between compilation phases (useful for debugging).
131
132=item B<--regalloc>=I<allocator>
133
134Specify the register allocator to use. The default I<allocator> is I<local>.
135Valid register allocators are:
136
137=over
138
139=item I<simple>
140
141Very simple "always spill" register allocator
142
143=item I<local>
144
145Local register allocator
146
147=item I<linearscan>
148
149Linear scan global register allocator
150
151=item I<iterativescan>
152
153Iterative scan global register allocator
154
155=back
156
157=item B<--spiller>=I<spiller>
158
159Specify the spiller to use for register allocators that support it.  Currently
160this option is used only by the linear scan register allocator. The default
161I<spiller> is I<local>.  Valid spillers are:
162
163=over
164
165=item I<simple>
166
167Simple spiller
168
169=item I<local>
170
171Local spiller
172
173=back
174
175=back
176
177=head2 Intel IA-32-specific Options
178
179=over
180
181=item B<--x86-asm-syntax=att|intel>
182
183Specify whether to emit assembly code in AT&T syntax (the default) or intel
184syntax.
185
186=back
187
188=head1 EXIT STATUS
189
190If B<llc> succeeds, it will exit with 0.  Otherwise, if an error occurs,
191it will exit with a non-zero value.
192
193=head1 SEE ALSO
194
195L<lli|lli>
196
197=head1 AUTHORS
198
199Maintained by the LLVM Team (L<http://llvm.org/>).
200
201=cut
202