1
2=pod
3
4=head1 NAME
5
6tblgen - Target Description To C++ Code Generator
7
8=head1 SYNOPSIS
9
10B<tblgen> [I<options>] [I<filename>]
11
12=head1 DESCRIPTION
13
14B<tblgen> translates from target description (.td) files into C++ code that can
15be included in the definition of an LLVM target library. Most users of LLVM will
16not need to use this program. It is only for assisting with writing an LLVM
17target backend.
18
19The input and output of B<tblgen> is beyond the scope of this short
20introduction. Please see the I<CodeGeneration> page in the LLVM documentation.
21
22The F<filename> argument specifies the name of a Target Description (.td) file
23to read as input.
24
25=head1 OPTIONS
26
27=over
28
29=item B<-help>
30
31Print a summary of command line options.
32
33=item B<-o> F<filename>
34
35Specify the output file name.  If F<filename> is C<->, then B<tblgen>
36sends its output to standard output.
37
38=item B<-I> F<directory>
39
40Specify where to find other target description files for inclusion. The
41F<directory> value should be a full or partial path to a directory that contains
42target description files.
43
44=item B<-asmwriternum> F<N>
45
46Make -gen-asm-writer emit assembly writer number F<N>.
47
48=item B<-class> F<class Name>
49
50Print the enumeration list for this class.
51
52=item B<-print-records>
53
54Print all records to standard output (default).
55
56=item B<-print-enums>
57
58Print enumeration values for a class
59
60=item B<-gen-emitter>
61
62Generate machine code emitter.
63
64=item B<-gen-register-enums>
65
66Generate the enumeration values for all registers.
67
68=item B<-gen-register-desc>
69
70Generate a register info description for each register.
71
72=item B<-gen-register-desc-header>
73
74Generate a register info description header for each register.
75
76=item B<-gen-instr-enums>
77
78Generate enumeration values for instructions.
79
80=item B<-gen-instr-desc>
81
82Generate instruction descriptions.
83
84=item B<-gen-asm-writer>
85
86Generate the assembly writer.
87
88=item B<-gen-dag-isel>
89
90Generate a DAG (Directed Acycle Graph) instruction selector.
91
92=item B<-gen-subtarget>
93
94Generate subtarget enumerations.
95
96=item B<-gen-intrinsic>
97
98Generate intrinsic information.
99
100=item B<-version>
101
102Show the version number of this program.
103
104=back
105
106=head1 EXIT STATUS
107
108If B<tblgen> succeeds, it will exit with 0.  Otherwise, if an error
109occurs, it will exit with a non-zero value.
110
111=head1 AUTHORS
112
113Maintained by The LLVM Team (L<http://llvm.org/>).
114
115=cut
116