1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the ARM specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef ARMTARGETMACHINE_H
15 #define ARMTARGETMACHINE_H
16 
17 #include "ARMInstrInfo.h"
18 #include "ARMELFWriterInfo.h"
19 #include "ARMFrameLowering.h"
20 #include "ARMJITInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMISelLowering.h"
23 #include "ARMSelectionDAGInfo.h"
24 #include "Thumb1InstrInfo.h"
25 #include "Thumb1FrameLowering.h"
26 #include "Thumb2InstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetData.h"
29 #include "llvm/MC/MCStreamer.h"
30 #include "llvm/ADT/OwningPtr.h"
31 
32 namespace llvm {
33 
34 class ARMBaseTargetMachine : public LLVMTargetMachine {
35 protected:
36   ARMSubtarget        Subtarget;
37 private:
38   ARMJITInfo          JITInfo;
39   InstrItineraryData  InstrItins;
40 
41 public:
42   ARMBaseTargetMachine(const Target &T, StringRef TT,
43                        StringRef CPU, StringRef FS,
44                        Reloc::Model RM, CodeModel::Model CM);
45 
getJITInfo()46   virtual       ARMJITInfo       *getJITInfo()         { return &JITInfo; }
getSubtargetImpl()47   virtual const ARMSubtarget  *getSubtargetImpl() const { return &Subtarget; }
getInstrItineraryData()48   virtual const InstrItineraryData *getInstrItineraryData() const {
49     return &InstrItins;
50   }
51 
52   // Pass Pipeline Configuration
53   virtual bool addPreISel(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
54   virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
55   virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
56   virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
57   virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
58   virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
59                               JITCodeEmitter &MCE);
60 };
61 
62 /// ARMTargetMachine - ARM target machine.
63 ///
64 class ARMTargetMachine : public ARMBaseTargetMachine {
65   ARMInstrInfo        InstrInfo;
66   const TargetData    DataLayout;       // Calculates type size & alignment
67   ARMELFWriterInfo    ELFWriterInfo;
68   ARMTargetLowering   TLInfo;
69   ARMSelectionDAGInfo TSInfo;
70   ARMFrameLowering    FrameLowering;
71  public:
72   ARMTargetMachine(const Target &T, StringRef TT,
73                    StringRef CPU, StringRef FS,
74                    Reloc::Model RM, CodeModel::Model CM);
75 
getRegisterInfo()76   virtual const ARMRegisterInfo  *getRegisterInfo() const {
77     return &InstrInfo.getRegisterInfo();
78   }
79 
getTargetLowering()80   virtual const ARMTargetLowering *getTargetLowering() const {
81     return &TLInfo;
82   }
83 
getSelectionDAGInfo()84   virtual const ARMSelectionDAGInfo* getSelectionDAGInfo() const {
85     return &TSInfo;
86   }
getFrameLowering()87   virtual const ARMFrameLowering *getFrameLowering() const {
88     return &FrameLowering;
89   }
90 
getInstrInfo()91   virtual const ARMInstrInfo     *getInstrInfo() const { return &InstrInfo; }
getTargetData()92   virtual const TargetData       *getTargetData() const { return &DataLayout; }
getELFWriterInfo()93   virtual const ARMELFWriterInfo *getELFWriterInfo() const {
94     return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
95   }
96 };
97 
98 /// ThumbTargetMachine - Thumb target machine.
99 /// Due to the way architectures are handled, this represents both
100 ///   Thumb-1 and Thumb-2.
101 ///
102 class ThumbTargetMachine : public ARMBaseTargetMachine {
103   // Either Thumb1InstrInfo or Thumb2InstrInfo.
104   OwningPtr<ARMBaseInstrInfo> InstrInfo;
105   const TargetData    DataLayout;   // Calculates type size & alignment
106   ARMELFWriterInfo    ELFWriterInfo;
107   ARMTargetLowering   TLInfo;
108   ARMSelectionDAGInfo TSInfo;
109   // Either Thumb1FrameLowering or ARMFrameLowering.
110   OwningPtr<ARMFrameLowering> FrameLowering;
111 public:
112   ThumbTargetMachine(const Target &T, StringRef TT,
113                      StringRef CPU, StringRef FS,
114                      Reloc::Model RM, CodeModel::Model CM);
115 
116   /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
getRegisterInfo()117   virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
118     return &InstrInfo->getRegisterInfo();
119   }
120 
getTargetLowering()121   virtual const ARMTargetLowering *getTargetLowering() const {
122     return &TLInfo;
123   }
124 
getSelectionDAGInfo()125   virtual const ARMSelectionDAGInfo *getSelectionDAGInfo() const {
126     return &TSInfo;
127   }
128 
129   /// returns either Thumb1InstrInfo or Thumb2InstrInfo
getInstrInfo()130   virtual const ARMBaseInstrInfo *getInstrInfo() const {
131     return InstrInfo.get();
132   }
133   /// returns either Thumb1FrameLowering or ARMFrameLowering
getFrameLowering()134   virtual const ARMFrameLowering *getFrameLowering() const {
135     return FrameLowering.get();
136   }
getTargetData()137   virtual const TargetData       *getTargetData() const { return &DataLayout; }
getELFWriterInfo()138   virtual const ARMELFWriterInfo *getELFWriterInfo() const {
139     return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
140   }
141 };
142 
143 } // end namespace llvm
144 
145 #endif
146