1//===- MBlazeInstrFormats.td - MB Instruction defs ---------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10// Format specifies the encoding used by the instruction.  This is part of the
11// ad-hoc solution used to emit machine instruction encodings by our machine
12// code emitter.
13class Format<bits<6> val> {
14      bits<6> Value = val;
15}
16
17def FPseudo : Format<0>;
18def FRRR    : Format<1>;  // ADD, OR, etc.
19def FRRI    : Format<2>;  // ADDI, ORI, etc.
20def FCRR    : Format<3>;  // PUTD, WDC, WIC, BEQ, BNE, BGE, etc.
21def FCRI    : Format<4>;  // RTID, RTED, RTSD, BEQI, BNEI, BGEI, etc.
22def FRCR    : Format<5>;  // BRLD, BRALD, GETD
23def FRCI    : Format<6>;  // BRLID, BRALID, MSRCLR, MSRSET
24def FCCR    : Format<7>;  // BR, BRA, BRD, etc.
25def FCCI    : Format<8>;  // IMM, BRI, BRAI, BRID, etc.
26def FRRCI   : Format<9>;  // BSRLI, BSRAI, BSLLI
27def FRRC    : Format<10>; // SEXT8, SEXT16, SRA, SRC, SRL, FLT, FINT, FSQRT
28def FRCX    : Format<11>; // GET
29def FRCS    : Format<12>; // MFS
30def FCRCS   : Format<13>; // MTS
31def FCRCX   : Format<14>; // PUT
32def FCX     : Format<15>; // TPUT
33def FCR     : Format<16>; // TPUTD
34def FRIR    : Format<17>; // RSUBI
35def FRRRR   : Format<18>; // RSUB, FRSUB
36def FRI     : Format<19>; // RSUB, FRSUB
37def FC      : Format<20>; // NOP
38
39//===----------------------------------------------------------------------===//
40//  Describe MBlaze instructions format
41//
42//  CPU INSTRUCTION FORMATS
43//
44//  opcode  - operation code.
45//  rd      - dst reg.
46//  ra      - first src. reg.
47//  rb      - second src. reg.
48//  imm16   - 16-bit immediate value.
49//
50//===----------------------------------------------------------------------===//
51
52// Generic MBlaze Format
53class MBlazeInst<bits<6> op, Format form, dag outs, dag ins, string asmstr,
54                 list<dag> pattern, InstrItinClass itin> : Instruction {
55  let Namespace = "MBlaze";
56  field bits<32> Inst;
57
58  bits<6> opcode = op;
59  Format Form = form;
60  bits<6> FormBits = Form.Value;
61
62  // Top 6 bits are the 'opcode' field
63  let Inst{0-5} = opcode;
64
65  // If the instruction is marked as a pseudo, set isCodeGenOnly so that the
66  // assembler and disassmbler ignore it.
67  let isCodeGenOnly = !eq(!cast<string>(form), "FPseudo");
68
69  dag OutOperandList = outs;
70  dag InOperandList  = ins;
71
72  let AsmString   = asmstr;
73  let Pattern     = pattern;
74  let Itinerary   = itin;
75
76  // TSFlags layout should be kept in sync with MBlazeInstrInfo.h.
77  let TSFlags{5-0}   = FormBits;
78}
79
80//===----------------------------------------------------------------------===//
81// Pseudo instruction class
82//===----------------------------------------------------------------------===//
83class MBlazePseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
84      MBlazeInst<0x0, FPseudo, outs, ins, asmstr, pattern, IIC_Pseudo>;
85
86//===----------------------------------------------------------------------===//
87// Type A instruction class in MBlaze : <|opcode|rd|ra|rb|flags|>
88//===----------------------------------------------------------------------===//
89
90class TA<bits<6> op, bits<11> flags, dag outs, dag ins, string asmstr,
91         list<dag> pattern, InstrItinClass itin> :
92         MBlazeInst<op,FRRR,outs, ins, asmstr, pattern, itin>
93{
94  bits<5> rd;
95  bits<5> ra;
96  bits<5> rb;
97
98  let Inst{6-10}  = rd;
99  let Inst{11-15} = ra;
100  let Inst{16-20} = rb;
101  let Inst{21-31} = flags;
102}
103
104//===----------------------------------------------------------------------===//
105// Type B instruction class in MBlaze : <|opcode|rd|ra|immediate|>
106//===----------------------------------------------------------------------===//
107
108class TB<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
109         InstrItinClass itin> :
110         MBlazeInst<op, FRRI, outs, ins, asmstr, pattern, itin>
111{
112  bits<5>  rd;
113  bits<5>  ra;
114  bits<16> imm16;
115
116  let Inst{6-10}  = rd;
117  let Inst{11-15} = ra;
118  let Inst{16-31} = imm16;
119}
120
121//===----------------------------------------------------------------------===//
122// Type A instruction class in MBlaze but with the operands reversed
123// in the LLVM DAG : <|opcode|rd|ra|rb|flags|>
124//===----------------------------------------------------------------------===//
125
126class TAR<bits<6> op, bits<11> flags, dag outs, dag ins, string asmstr,
127          list<dag> pattern, InstrItinClass itin> :
128          TA<op, flags, outs, ins, asmstr, pattern, itin>
129{
130  bits<5> rrd;
131  bits<5> rrb;
132  bits<5> rra;
133
134  let Form = FRRRR;
135
136  let rd = rrd;
137  let ra = rra;
138  let rb = rrb;
139}
140
141//===----------------------------------------------------------------------===//
142// Type B instruction class in MBlaze but with the operands reversed in
143// the LLVM DAG : <|opcode|rd|ra|immediate|>
144//===----------------------------------------------------------------------===//
145class TBR<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
146         InstrItinClass itin> :
147         TB<op, outs, ins, asmstr, pattern, itin> {
148  bits<5>  rrd;
149  bits<16> rimm16;
150  bits<5>  rra;
151
152  let Form = FRIR;
153
154  let rd = rrd;
155  let ra = rra;
156  let imm16 = rimm16;
157}
158
159//===----------------------------------------------------------------------===//
160// Shift immediate instruction class in MBlaze : <|opcode|rd|ra|immediate|>
161//===----------------------------------------------------------------------===//
162class SHT<bits<6> op, bits<2> flags, dag outs, dag ins, string asmstr,
163          list<dag> pattern, InstrItinClass itin> :
164          MBlazeInst<op, FRRI, outs, ins, asmstr, pattern, itin> {
165  bits<5>  rd;
166  bits<5>  ra;
167  bits<5>  imm5;
168
169  let Inst{6-10}  = rd;
170  let Inst{11-15} = ra;
171  let Inst{16-20} = 0x0;
172  let Inst{21-22} = flags;
173  let Inst{23-26} = 0x0;
174  let Inst{27-31} = imm5;
175}
176
177//===----------------------------------------------------------------------===//
178// Special instruction class in MBlaze : <|opcode|rd|imm14|>
179//===----------------------------------------------------------------------===//
180class SPC<bits<6> op, bits<2> flags, dag outs, dag ins, string asmstr,
181          list<dag> pattern, InstrItinClass itin> :
182          MBlazeInst<op, FRI, outs, ins, asmstr, pattern, itin> {
183  bits<5>  rd;
184  bits<14> imm14;
185
186  let Inst{6-10}  = rd;
187  let Inst{11-15} = 0x0;
188  let Inst{16-17} = flags;
189  let Inst{18-31} = imm14;
190}
191
192//===----------------------------------------------------------------------===//
193// MSR instruction class in MBlaze : <|opcode|rd|imm15|>
194//===----------------------------------------------------------------------===//
195class MSR<bits<6> op, bits<6> flags, dag outs, dag ins, string asmstr,
196          list<dag> pattern, InstrItinClass itin> :
197          MBlazeInst<op, FRI, outs, ins, asmstr, pattern, itin> {
198  bits<5>  rd;
199  bits<15> imm15;
200
201  let Inst{6-10}  = rd;
202  let Inst{11-16} = flags;
203  let Inst{17-31} = imm15;
204}
205