1//===- MBlazeSchedule5.td - MBlaze Scheduling Definitions --*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// MBlaze instruction itineraries for the five stage pipeline.
12//===----------------------------------------------------------------------===//
13def MBlazePipe5Itineraries : ProcessorItineraries<
14  [IF,ID,EX,MA,WB], [], [
15
16  // ALU instruction with one destination register and either two register
17  // source operands or one register source operand and one immediate operand.
18  // The instruction takes one cycle to execute in each of the stages. The
19  // two source operands are read during the decode stage and the result is
20  // ready after the execute stage.
21  InstrItinData< IIC_ALU,
22               [ InstrStage<1,[IF]>   // one cycle in fetch stage
23               , InstrStage<1,[ID]>   // one cycle in decode stage
24               , InstrStage<1,[EX]>   // one cycle in execute stage
25               , InstrStage<1,[MA]>   // one cycle in memory access stage
26               , InstrStage<1,[WB]>], // one cycle in write back stage
27               [ 2                    // result ready after two cycles
28               , 1                    // first operand read after one cycle
29               , 1 ]>,                // second operand read after one cycle
30
31  // ALU multiply instruction with one destination register and either two
32  // register source operands or one register source operand and one immediate
33  // operand.  The instruction takes one cycle to execute in each of the
34  // pipeline stages. The two source operands are read during the decode stage
35  // and the result is ready after the execute stage.
36  InstrItinData< IIC_ALUm,
37               [ InstrStage<1,[IF]>   // one cycle in fetch stage
38               , InstrStage<1,[ID]>   // one cycle in decode stage
39               , InstrStage<1,[EX]>   // one cycle in execute stage
40               , InstrStage<1,[MA]>   // one cycle in memory access stage
41               , InstrStage<1,[WB]>], // one cycle in write back stage
42               [ 2                    // result ready after two cycles
43               , 1                    // first operand read after one cycle
44               , 1 ]>,                // second operand read after one cycle
45
46  // ALU divide instruction with one destination register two register source
47  // operands. The instruction takes one cycle to execute in each the pipeline
48  // stages except the memory access stage, which takes 31 cycles. The two
49  // source operands are read during the decode stage and the result is ready
50  // after the memory access stage.
51  InstrItinData< IIC_ALUd,
52               [ InstrStage<1,[IF]>   // one cycle in fetch stage
53               , InstrStage<1,[ID]>   // one cycle in decode stage
54               , InstrStage<1,[EX]>   // one cycle in execute stage
55               , InstrStage<31,[MA]>  // 31 cycles in memory access stage
56               , InstrStage<1,[WB]>], // one cycle in write back stage
57               [ 33                   // result ready after 33 cycles
58               , 1                    // first operand read after one cycle
59               , 1 ]>,                // second operand read after one cycle
60
61  // Shift instruction with one destination register and either two register
62  // source operands or one register source operand and one immediate operand.
63  // The instruction takes one cycle to execute in each of the pipeline stages.
64  // The two source operands are read during the decode stage and the result is
65  // ready after the memory access stage.
66  InstrItinData< IIC_SHT,
67               [ InstrStage<1,[IF]>   // one cycle in fetch stage
68               , InstrStage<1,[ID]>   // one cycle in decode stage
69               , InstrStage<1,[EX]>   // one cycle in execute stage
70               , InstrStage<1,[MA]>   // one cycle in memory access stage
71               , InstrStage<1,[WB]>], // one cycle in write back stage
72               [ 3                    // result ready after three cycles
73               , 1                    // first operand read after one cycle
74               , 1 ]>,                // second operand read after one cycle
75
76  // Branch instruction with one source operand register. The instruction takes
77  // one cycle to execute in each of the pipeline stages. The source operand is
78  // read during the decode stage.
79  InstrItinData< IIC_BR,
80               [ InstrStage<1,[IF]>   // one cycle in fetch stage
81               , InstrStage<1,[ID]>   // one cycle in decode stage
82               , InstrStage<1,[EX]>   // one cycle in execute stage
83               , InstrStage<1,[MA]>   // one cycle in memory access stage
84               , InstrStage<1,[WB]>], // one cycle in write back stage
85               [ 1 ]>,                // first operand read after one cycle
86
87  // Conditional branch instruction with two source operand registers. The
88  // instruction takes one cycle to execute in each of the pipeline stages. The
89  // two source operands are read during the decode stage.
90  InstrItinData< IIC_BRc,
91               [ InstrStage<1,[IF]>   // one cycle in fetch stage
92               , InstrStage<1,[ID]>   // one cycle in decode stage
93               , InstrStage<1,[EX]>   // one cycle in execute stage
94               , InstrStage<1,[MA]>   // one cycle in memory access stage
95               , InstrStage<1,[WB]>], // one cycle in write back stage
96               [ 1                    // first operand read after one cycle
97               , 1 ]>,                // second operand read after one cycle
98
99  // Branch and link instruction with one destination register and one source
100  // operand register. The instruction takes one cycle to execute in each of
101  // the pipeline stages. The source operand is read during the decode stage
102  // and the destination register is ready after the writeback stage.
103  InstrItinData< IIC_BRl,
104               [ InstrStage<1,[IF]>   // one cycle in fetch stage
105               , InstrStage<1,[ID]>   // one cycle in decode stage
106               , InstrStage<1,[EX]>   // one cycle in execute stage
107               , InstrStage<1,[MA]>   // one cycle in memory access stage
108               , InstrStage<1,[WB]>], // one cycle in write back stage
109               [ 4                    // result ready after four cycles
110               , 1 ]>,                // first operand read after one cycle
111
112  // Cache control instruction with two source operand registers. The
113  // instruction takes one cycle to execute in each of the pipeline stages
114  // except the memory access stage, which takes two cycles. The source
115  // operands are read during the decode stage.
116  InstrItinData< IIC_WDC,
117               [ InstrStage<1,[IF]>   // one cycle in fetch stage
118               , InstrStage<1,[ID]>   // one cycle in decode stage
119               , InstrStage<1,[EX]>   // one cycle in execute stage
120               , InstrStage<2,[MA]>   // two cycles in memory access stage
121               , InstrStage<1,[WB]>], // one cycle in write back stage
122               [ 1                    // first operand read after one cycle
123               , 1 ]>,                // second operand read after one cycle
124
125  // Floating point instruction with one destination register and two source
126  // operand registers. The instruction takes one cycle to execute in each of
127  // the pipeline stages except the memory access stage, which takes two
128  // cycles. The source operands are read during the decode stage and the
129  // results are ready after the writeback stage.
130  InstrItinData< IIC_FPU,
131               [ InstrStage<1,[IF]>   // one cycle in fetch stage
132               , InstrStage<1,[ID]>   // one cycle in decode stage
133               , InstrStage<1,[EX]>   // one cycle in execute stage
134               , InstrStage<2,[MA]>   // two cycles in memory access stage
135               , InstrStage<1,[WB]>], // one cycle in write back stage
136               [ 5                    // result ready after five cycles
137               , 1                    // first operand read after one cycle
138               , 1 ]>,                // second operand read after one cycle
139
140  // Floating point divide instruction with one destination register and two
141  // source operand registers. The instruction takes one cycle to execute in
142  // each of the pipeline stages except the memory access stage, which takes 26
143  // cycles. The source operands are read during the decode stage and the
144  // results are ready after the writeback stage.
145  InstrItinData< IIC_FPUd,
146               [ InstrStage<1,[IF]>   // one cycle in fetch stage
147               , InstrStage<1,[ID]>   // one cycle in decode stage
148               , InstrStage<1,[EX]>   // one cycle in execute stage
149               , InstrStage<26,[MA]>  // 26 cycles in memory access stage
150               , InstrStage<1,[WB]>], // one cycle in write back stage
151               [ 29                   // result ready after 29 cycles
152               , 1                    // first operand read after one cycle
153               , 1 ]>,                // second operand read after one cycle
154
155  // Convert floating point to integer instruction with one destination
156  // register and one source operand register. The instruction takes one cycle
157  // to execute in each of the pipeline stages except the memory access stage,
158  // which takes three cycles. The source operands are read during the decode
159  // stage and the results are ready after the writeback stage.
160  InstrItinData< IIC_FPUi,
161               [ InstrStage<1,[IF]>   // one cycle in fetch stage
162               , InstrStage<1,[ID]>   // one cycle in decode stage
163               , InstrStage<1,[EX]>   // one cycle in execute stage
164               , InstrStage<3,[MA]>   // three cycles in memory access stage
165               , InstrStage<1,[WB]>], // one cycle in write back stage
166               [ 6                   // result ready after six cycles
167               , 1 ]>,                // first operand read after one cycle
168
169  // Convert integer to floating point instruction with one destination
170  // register and one source operand register. The instruction takes one cycle
171  // to execute in each of the pipeline stages except the memory access stage,
172  // which takes two cycles. The source operands are read during the decode
173  // stage and the results are ready after the writeback stage.
174  InstrItinData< IIC_FPUf,
175               [ InstrStage<1,[IF]>   // one cycle in fetch stage
176               , InstrStage<1,[ID]>   // one cycle in decode stage
177               , InstrStage<1,[EX]>   // one cycle in execute stage
178               , InstrStage<2,[MA]>   // two cycles in memory access stage
179               , InstrStage<1,[WB]>], // one cycle in write back stage
180               [ 5                    // result ready after five cycles
181               , 1 ]>,                // first operand read after one cycle
182
183  // Floating point square root instruction with one destination register and
184  // one source operand register. The instruction takes one cycle to execute in
185  // each of the pipeline stages except the memory access stage, which takes 25
186  // cycles. The source operands are read during the decode stage and the
187  // results are ready after the writeback stage.
188  InstrItinData< IIC_FPUs,
189               [ InstrStage<1,[IF]>   // one cycle in fetch stage
190               , InstrStage<1,[ID]>   // one cycle in decode stage
191               , InstrStage<1,[EX]>   // one cycle in execute stage
192               , InstrStage<25,[MA]>  // 25 cycles in memory access stage
193               , InstrStage<1,[WB]>], // one cycle in write back stage
194               [ 28                   // result ready after 28 cycles
195               , 1 ]>,                // first operand read after one cycle
196
197  // Floating point comparison instruction with one destination register and
198  // two source operand registers. The instruction takes one cycle to execute
199  // in each of the pipeline stages. The source operands are read during the
200  // decode stage and the results are ready after the execute stage.
201  InstrItinData< IIC_FPUc,
202               [ InstrStage<1,[IF]>   // one cycle in fetch stage
203               , InstrStage<1,[ID]>   // one cycle in decode stage
204               , InstrStage<1,[EX]>   // one cycle in execute stage
205               , InstrStage<1,[MA]>   // one cycle in memory access stage
206               , InstrStage<1,[WB]>], // one cycle in write back stage
207               [ 2                    // result ready after two cycles
208               , 1                    // first operand read after one cycle
209               , 1 ]>,                // second operand read after one cycle
210
211  // FSL get instruction with one register or immediate source operand and one
212  // destination register. The instruction takes one cycle to execute in each
213  // of the pipeline stages. The one source operand is read during the decode
214  // stage and the result is ready after the execute stage.
215  InstrItinData< IIC_FSLg,
216               [ InstrStage<1,[IF]>   // one cycle in fetch stage
217               , InstrStage<1,[ID]>   // one cycle in decode stage
218               , InstrStage<1,[EX]>   // one cycle in execute stage
219               , InstrStage<1,[MA]>   // one cycle in memory access stage
220               , InstrStage<1,[WB]>], // one cycle in write back stage
221               [ 2                    // result ready after two cycles
222               , 1 ]>,                // first operand read after one cycle
223
224  // FSL put instruction with either two register source operands or one
225  // register source operand and one immediate operand. There is no result
226  // produced by the instruction. The instruction takes one cycle to execute in
227  // each of the pipeline stages. The two source operands are read during the
228  // decode stage.
229  InstrItinData< IIC_FSLp,
230               [ InstrStage<1,[IF]>   // one cycle in fetch stage
231               , InstrStage<1,[ID]>   // one cycle in decode stage
232               , InstrStage<1,[EX]>   // one cycle in execute stage
233               , InstrStage<1,[MA]>   // one cycle in memory access stage
234               , InstrStage<1,[WB]>], // one cycle in write back stage
235               [ 1                    // first operand read after one cycle
236               , 1 ]>,                // second operand read after one cycle
237
238  // Memory store instruction with either three register source operands or two
239  // register source operands and one immediate operand. There is no result
240  // produced by the instruction. The instruction takes one cycle to execute in
241  // each of the pipeline stages. All of the source operands are read during
242  // the decode stage.
243  InstrItinData< IIC_MEMs,
244               [ InstrStage<1,[IF]>   // one cycle in fetch stage
245               , InstrStage<1,[ID]>   // one cycle in decode stage
246               , InstrStage<1,[EX]>   // one cycle in execute stage
247               , InstrStage<1,[MA]>   // one cycle in memory access stage
248               , InstrStage<1,[WB]>], // one cycle in write back stage
249               [ 1                    // first operand read after one cycle
250               , 1                    // second operand read after one cycle
251               , 1 ]>,                // third operand read after one cycle
252
253  // Memory load instruction with one destination register and either two
254  // register source operands or one register source operand and one immediate
255  // operand. The instruction takes one cycle to execute in each of the
256  // pipeline stages. All of the source operands are read during the decode
257  // stage and the result is ready after the writeback stage.
258  InstrItinData< IIC_MEMl,
259               [ InstrStage<1,[IF]>   // one cycle in fetch stage
260               , InstrStage<1,[ID]>   // one cycle in decode stage
261               , InstrStage<1,[EX]>   // one cycle in execute stage
262               , InstrStage<1,[MA]>   // one cycle in memory access stage
263               , InstrStage<1,[WB]>], // one cycle in write back stage
264               [ 4                    // result ready after four cycles
265               , 1                    // second operand read after one cycle
266               , 1 ]>                 // third operand read after one cycle
267]>;
268