1//======- X86InstrFragmentsSIMD.td - x86 ISA -------------*- tablegen -*-=====// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file provides pattern fragments useful for SIMD instructions. 11// 12//===----------------------------------------------------------------------===// 13 14// MMX specific DAG Nodes. 15//===----------------------------------------------------------------------===// 16 17// Low word of MMX to GPR. 18def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1, 19 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>; 20 21// GPR to low word of MMX. 22def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1, 23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>; 24 25//===----------------------------------------------------------------------===// 26// MMX Pattern Fragments 27//===----------------------------------------------------------------------===// 28 29def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>; 30def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>; 31 32//===----------------------------------------------------------------------===// 33// SSE specific DAG Nodes. 34//===----------------------------------------------------------------------===// 35 36def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>, 37 SDTCisFP<0>, SDTCisInt<2> ]>; 38def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, 39 SDTCisFP<1>, SDTCisVT<3, i8>]>; 40 41def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>; 42def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>; 43def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, 44 [SDNPCommutative, SDNPAssociative]>; 45def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp, 46 [SDNPCommutative, SDNPAssociative]>; 47def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, 48 [SDNPCommutative, SDNPAssociative]>; 49def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>; 50def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>; 51def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>; 52def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>; 53def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>; 54def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>; 55def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>; 56def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>; 57def X86cmpss : SDNode<"X86ISD::FSETCCss", SDTX86Cmpss>; 58def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>; 59def X86pshufb : SDNode<"X86ISD::PSHUFB", 60 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, 61 SDTCisSameAs<0,2>]>>; 62def X86andnp : SDNode<"X86ISD::ANDNP", 63 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 64 SDTCisSameAs<0,2>]>>; 65def X86psignb : SDNode<"X86ISD::PSIGNB", 66 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, 67 SDTCisSameAs<0,2>]>>; 68def X86psignw : SDNode<"X86ISD::PSIGNW", 69 SDTypeProfile<1, 2, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>, 70 SDTCisSameAs<0,2>]>>; 71def X86psignd : SDNode<"X86ISD::PSIGND", 72 SDTypeProfile<1, 2, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>, 73 SDTCisSameAs<0,2>]>>; 74def X86pextrb : SDNode<"X86ISD::PEXTRB", 75 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>; 76def X86pextrw : SDNode<"X86ISD::PEXTRW", 77 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>; 78def X86pinsrb : SDNode<"X86ISD::PINSRB", 79 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, 80 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; 81def X86pinsrw : SDNode<"X86ISD::PINSRW", 82 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>, 83 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; 84def X86insrtps : SDNode<"X86ISD::INSERTPS", 85 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>, 86 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>; 87def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL", 88 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>; 89def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad, 90 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 91def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>; 92def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>; 93def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>; 94def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>; 95def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>; 96def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>; 97def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>; 98def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>; 99def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>; 100def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>; 101def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>; 102def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>; 103 104def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 105 SDTCisVec<1>, 106 SDTCisSameAs<2, 1>]>; 107def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>; 108def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>; 109 110// Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get 111// translated into one of the target nodes below during lowering. 112// Note: this is a work in progress... 113def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>; 114def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 115 SDTCisSameAs<0,2>]>; 116 117def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>, 118 SDTCisSameAs<0,1>, SDTCisInt<2>]>; 119def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 120 SDTCisSameAs<0,2>, SDTCisInt<3>]>; 121 122def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>; 123 124def X86PAlign : SDNode<"X86ISD::PALIGN", SDTShuff3OpI>; 125 126def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>; 127def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>; 128def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>; 129 130def X86Shufpd : SDNode<"X86ISD::SHUFPD", SDTShuff3OpI>; 131def X86Shufps : SDNode<"X86ISD::SHUFPS", SDTShuff3OpI>; 132 133def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>; 134def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>; 135def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>; 136 137def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>; 138def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>; 139 140def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>; 141def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>; 142def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>; 143def X86Movhlpd : SDNode<"X86ISD::MOVHLPD", SDTShuff2Op>; 144 145def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>; 146def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>; 147 148def X86Unpcklps : SDNode<"X86ISD::UNPCKLPS", SDTShuff2Op>; 149def X86Unpcklpd : SDNode<"X86ISD::UNPCKLPD", SDTShuff2Op>; 150def X86Unpcklpsy : SDNode<"X86ISD::VUNPCKLPSY", SDTShuff2Op>; 151def X86Unpcklpdy : SDNode<"X86ISD::VUNPCKLPDY", SDTShuff2Op>; 152 153def X86Unpckhps : SDNode<"X86ISD::UNPCKHPS", SDTShuff2Op>; 154def X86Unpckhpd : SDNode<"X86ISD::UNPCKHPD", SDTShuff2Op>; 155def X86Unpckhpsy : SDNode<"X86ISD::VUNPCKHPSY", SDTShuff2Op>; 156def X86Unpckhpdy : SDNode<"X86ISD::VUNPCKHPDY", SDTShuff2Op>; 157 158def X86Punpcklbw : SDNode<"X86ISD::PUNPCKLBW", SDTShuff2Op>; 159def X86Punpcklwd : SDNode<"X86ISD::PUNPCKLWD", SDTShuff2Op>; 160def X86Punpckldq : SDNode<"X86ISD::PUNPCKLDQ", SDTShuff2Op>; 161def X86Punpcklqdq : SDNode<"X86ISD::PUNPCKLQDQ", SDTShuff2Op>; 162 163def X86Punpckhbw : SDNode<"X86ISD::PUNPCKHBW", SDTShuff2Op>; 164def X86Punpckhwd : SDNode<"X86ISD::PUNPCKHWD", SDTShuff2Op>; 165def X86Punpckhdq : SDNode<"X86ISD::PUNPCKHDQ", SDTShuff2Op>; 166def X86Punpckhqdq : SDNode<"X86ISD::PUNPCKHQDQ", SDTShuff2Op>; 167 168def X86VPermilps : SDNode<"X86ISD::VPERMILPS", SDTShuff2OpI>; 169def X86VPermilpsy : SDNode<"X86ISD::VPERMILPSY", SDTShuff2OpI>; 170def X86VPermilpd : SDNode<"X86ISD::VPERMILPD", SDTShuff2OpI>; 171def X86VPermilpdy : SDNode<"X86ISD::VPERMILPDY", SDTShuff2OpI>; 172 173def X86VPerm2f128 : SDNode<"X86ISD::VPERM2F128", SDTShuff3OpI>; 174 175def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>; 176 177//===----------------------------------------------------------------------===// 178// SSE Complex Patterns 179//===----------------------------------------------------------------------===// 180 181// These are 'extloads' from a scalar to the low element of a vector, zeroing 182// the top elements. These are used for the SSE 'ss' and 'sd' instruction 183// forms. 184def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [], 185 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, 186 SDNPWantRoot]>; 187def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [], 188 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, 189 SDNPWantRoot]>; 190 191def ssmem : Operand<v4f32> { 192 let PrintMethod = "printf32mem"; 193 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 194 let ParserMatchClass = X86MemAsmOperand; 195 let OperandType = "OPERAND_MEMORY"; 196} 197def sdmem : Operand<v2f64> { 198 let PrintMethod = "printf64mem"; 199 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 200 let ParserMatchClass = X86MemAsmOperand; 201 let OperandType = "OPERAND_MEMORY"; 202} 203 204//===----------------------------------------------------------------------===// 205// SSE pattern fragments 206//===----------------------------------------------------------------------===// 207 208// 128-bit load pattern fragments 209def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>; 210def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>; 211def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>; 212def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>; 213 214// 256-bit load pattern fragments 215def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>; 216def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>; 217def loadv8i32 : PatFrag<(ops node:$ptr), (v8i32 (load node:$ptr))>; 218def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>; 219 220// Like 'store', but always requires 128-bit vector alignment. 221def alignedstore : PatFrag<(ops node:$val, node:$ptr), 222 (store node:$val, node:$ptr), [{ 223 return cast<StoreSDNode>(N)->getAlignment() >= 16; 224}]>; 225 226// Like 'store', but always requires 256-bit vector alignment. 227def alignedstore256 : PatFrag<(ops node:$val, node:$ptr), 228 (store node:$val, node:$ptr), [{ 229 return cast<StoreSDNode>(N)->getAlignment() >= 32; 230}]>; 231 232// Like 'load', but always requires 128-bit vector alignment. 233def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 234 return cast<LoadSDNode>(N)->getAlignment() >= 16; 235}]>; 236 237// Like 'load', but always requires 256-bit vector alignment. 238def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 239 return cast<LoadSDNode>(N)->getAlignment() >= 32; 240}]>; 241 242def alignedloadfsf32 : PatFrag<(ops node:$ptr), 243 (f32 (alignedload node:$ptr))>; 244def alignedloadfsf64 : PatFrag<(ops node:$ptr), 245 (f64 (alignedload node:$ptr))>; 246 247// 128-bit aligned load pattern fragments 248def alignedloadv4f32 : PatFrag<(ops node:$ptr), 249 (v4f32 (alignedload node:$ptr))>; 250def alignedloadv2f64 : PatFrag<(ops node:$ptr), 251 (v2f64 (alignedload node:$ptr))>; 252def alignedloadv4i32 : PatFrag<(ops node:$ptr), 253 (v4i32 (alignedload node:$ptr))>; 254def alignedloadv2i64 : PatFrag<(ops node:$ptr), 255 (v2i64 (alignedload node:$ptr))>; 256 257// 256-bit aligned load pattern fragments 258def alignedloadv8f32 : PatFrag<(ops node:$ptr), 259 (v8f32 (alignedload256 node:$ptr))>; 260def alignedloadv4f64 : PatFrag<(ops node:$ptr), 261 (v4f64 (alignedload256 node:$ptr))>; 262def alignedloadv8i32 : PatFrag<(ops node:$ptr), 263 (v8i32 (alignedload256 node:$ptr))>; 264def alignedloadv4i64 : PatFrag<(ops node:$ptr), 265 (v4i64 (alignedload256 node:$ptr))>; 266 267// Like 'load', but uses special alignment checks suitable for use in 268// memory operands in most SSE instructions, which are required to 269// be naturally aligned on some targets but not on others. If the subtarget 270// allows unaligned accesses, match any load, though this may require 271// setting a feature bit in the processor (on startup, for example). 272// Opteron 10h and later implement such a feature. 273def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 274 return Subtarget->hasVectorUAMem() 275 || cast<LoadSDNode>(N)->getAlignment() >= 16; 276}]>; 277 278def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>; 279def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>; 280 281// 128-bit memop pattern fragments 282def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>; 283def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>; 284def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>; 285def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>; 286def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop node:$ptr))>; 287def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>; 288 289// 256-bit memop pattern fragments 290def memopv32i8 : PatFrag<(ops node:$ptr), (v32i8 (memop node:$ptr))>; 291def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>; 292def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>; 293def memopv4i64 : PatFrag<(ops node:$ptr), (v4i64 (memop node:$ptr))>; 294def memopv8i32 : PatFrag<(ops node:$ptr), (v8i32 (memop node:$ptr))>; 295 296// SSSE3 uses MMX registers for some instructions. They aren't aligned on a 297// 16-byte boundary. 298// FIXME: 8 byte alignment for mmx reads is not required 299def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 300 return cast<LoadSDNode>(N)->getAlignment() >= 8; 301}]>; 302 303def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>; 304 305// MOVNT Support 306// Like 'store', but requires the non-temporal bit to be set 307def nontemporalstore : PatFrag<(ops node:$val, node:$ptr), 308 (st node:$val, node:$ptr), [{ 309 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) 310 return ST->isNonTemporal(); 311 return false; 312}]>; 313 314def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 315 (st node:$val, node:$ptr), [{ 316 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) 317 return ST->isNonTemporal() && !ST->isTruncatingStore() && 318 ST->getAddressingMode() == ISD::UNINDEXED && 319 ST->getAlignment() >= 16; 320 return false; 321}]>; 322 323def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 324 (st node:$val, node:$ptr), [{ 325 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) 326 return ST->isNonTemporal() && 327 ST->getAlignment() < 16; 328 return false; 329}]>; 330 331// 128-bit bitconvert pattern fragments 332def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>; 333def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>; 334def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>; 335def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>; 336def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>; 337def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>; 338 339// 256-bit bitconvert pattern fragments 340def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>; 341def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>; 342 343def vzmovl_v2i64 : PatFrag<(ops node:$src), 344 (bitconvert (v2i64 (X86vzmovl 345 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>; 346def vzmovl_v4i32 : PatFrag<(ops node:$src), 347 (bitconvert (v4i32 (X86vzmovl 348 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>; 349 350def vzload_v2i64 : PatFrag<(ops node:$src), 351 (bitconvert (v2i64 (X86vzload node:$src)))>; 352 353 354def fp32imm0 : PatLeaf<(f32 fpimm), [{ 355 return N->isExactlyValue(+0.0); 356}]>; 357 358// BYTE_imm - Transform bit immediates into byte immediates. 359def BYTE_imm : SDNodeXForm<imm, [{ 360 // Transformation function: imm >> 3 361 return getI32Imm(N->getZExtValue() >> 3); 362}]>; 363 364// SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*, 365// SHUFP* etc. imm. 366def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{ 367 return getI8Imm(X86::getShuffleSHUFImmediate(N)); 368}]>; 369 370// SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to 371// PSHUFHW imm. 372def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{ 373 return getI8Imm(X86::getShufflePSHUFHWImmediate(N)); 374}]>; 375 376// SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to 377// PSHUFLW imm. 378def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{ 379 return getI8Imm(X86::getShufflePSHUFLWImmediate(N)); 380}]>; 381 382// SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to 383// a PALIGNR imm. 384def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{ 385 return getI8Imm(X86::getShufflePALIGNRImmediate(N)); 386}]>; 387 388// EXTRACT_get_vextractf128_imm xform function: convert extract_subvector index 389// to VEXTRACTF128 imm. 390def EXTRACT_get_vextractf128_imm : SDNodeXForm<extract_subvector, [{ 391 return getI8Imm(X86::getExtractVEXTRACTF128Immediate(N)); 392}]>; 393 394// INSERT_get_vinsertf128_imm xform function: convert insert_subvector index to 395// VINSERTF128 imm. 396def INSERT_get_vinsertf128_imm : SDNodeXForm<insert_subvector, [{ 397 return getI8Imm(X86::getInsertVINSERTF128Immediate(N)); 398}]>; 399 400def splat_lo : PatFrag<(ops node:$lhs, node:$rhs), 401 (vector_shuffle node:$lhs, node:$rhs), [{ 402 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 403 return SVOp->isSplat() && SVOp->getSplatIndex() == 0; 404}]>; 405 406def movddup : PatFrag<(ops node:$lhs, node:$rhs), 407 (vector_shuffle node:$lhs, node:$rhs), [{ 408 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N)); 409}]>; 410 411def movhlps : PatFrag<(ops node:$lhs, node:$rhs), 412 (vector_shuffle node:$lhs, node:$rhs), [{ 413 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N)); 414}]>; 415 416def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs), 417 (vector_shuffle node:$lhs, node:$rhs), [{ 418 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N)); 419}]>; 420 421def movlhps : PatFrag<(ops node:$lhs, node:$rhs), 422 (vector_shuffle node:$lhs, node:$rhs), [{ 423 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N)); 424}]>; 425 426def movlp : PatFrag<(ops node:$lhs, node:$rhs), 427 (vector_shuffle node:$lhs, node:$rhs), [{ 428 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N)); 429}]>; 430 431def movl : PatFrag<(ops node:$lhs, node:$rhs), 432 (vector_shuffle node:$lhs, node:$rhs), [{ 433 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N)); 434}]>; 435 436def unpckl : PatFrag<(ops node:$lhs, node:$rhs), 437 (vector_shuffle node:$lhs, node:$rhs), [{ 438 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N)); 439}]>; 440 441def unpckh : PatFrag<(ops node:$lhs, node:$rhs), 442 (vector_shuffle node:$lhs, node:$rhs), [{ 443 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N)); 444}]>; 445 446def pshufd : PatFrag<(ops node:$lhs, node:$rhs), 447 (vector_shuffle node:$lhs, node:$rhs), [{ 448 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N)); 449}], SHUFFLE_get_shuf_imm>; 450 451def shufp : PatFrag<(ops node:$lhs, node:$rhs), 452 (vector_shuffle node:$lhs, node:$rhs), [{ 453 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N)); 454}], SHUFFLE_get_shuf_imm>; 455 456def pshufhw : PatFrag<(ops node:$lhs, node:$rhs), 457 (vector_shuffle node:$lhs, node:$rhs), [{ 458 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N)); 459}], SHUFFLE_get_pshufhw_imm>; 460 461def pshuflw : PatFrag<(ops node:$lhs, node:$rhs), 462 (vector_shuffle node:$lhs, node:$rhs), [{ 463 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N)); 464}], SHUFFLE_get_pshuflw_imm>; 465 466def vextractf128_extract : PatFrag<(ops node:$bigvec, node:$index), 467 (extract_subvector node:$bigvec, 468 node:$index), [{ 469 return X86::isVEXTRACTF128Index(N); 470}], EXTRACT_get_vextractf128_imm>; 471 472def vinsertf128_insert : PatFrag<(ops node:$bigvec, node:$smallvec, 473 node:$index), 474 (insert_subvector node:$bigvec, node:$smallvec, 475 node:$index), [{ 476 return X86::isVINSERTF128Index(N); 477}], INSERT_get_vinsertf128_imm>; 478 479