1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains code to lower X86 MachineInstrs to their corresponding
11 // MCInst records.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "InstPrinter/X86ATTInstPrinter.h"
16 #include "X86MCInstLower.h"
17 #include "X86AsmPrinter.h"
18 #include "X86COFFMachineModuleInfo.h"
19 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSymbol.h"
26 #include "llvm/Target/Mangler.h"
27 #include "llvm/Support/FormattedStream.h"
28 #include "llvm/ADT/SmallString.h"
29 #include "llvm/Type.h"
30 using namespace llvm;
31 
X86MCInstLower(Mangler * mang,const MachineFunction & mf,X86AsmPrinter & asmprinter)32 X86MCInstLower::X86MCInstLower(Mangler *mang, const MachineFunction &mf,
33                                X86AsmPrinter &asmprinter)
34 : Ctx(mf.getContext()), Mang(mang), MF(mf), TM(mf.getTarget()),
35   MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
36 
getMachOMMI() const37 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
38   return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
39 }
40 
41 
42 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
43 /// operand to an MCSymbol.
44 MCSymbol *X86MCInstLower::
GetSymbolFromOperand(const MachineOperand & MO) const45 GetSymbolFromOperand(const MachineOperand &MO) const {
46   assert((MO.isGlobal() || MO.isSymbol()) && "Isn't a symbol reference");
47 
48   SmallString<128> Name;
49 
50   if (!MO.isGlobal()) {
51     assert(MO.isSymbol());
52     Name += MAI.getGlobalPrefix();
53     Name += MO.getSymbolName();
54   } else {
55     const GlobalValue *GV = MO.getGlobal();
56     bool isImplicitlyPrivate = false;
57     if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB ||
58         MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
59         MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
60         MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
61       isImplicitlyPrivate = true;
62 
63     Mang->getNameWithPrefix(Name, GV, isImplicitlyPrivate);
64   }
65 
66   // If the target flags on the operand changes the name of the symbol, do that
67   // before we return the symbol.
68   switch (MO.getTargetFlags()) {
69   default: break;
70   case X86II::MO_DLLIMPORT: {
71     // Handle dllimport linkage.
72     const char *Prefix = "__imp_";
73     Name.insert(Name.begin(), Prefix, Prefix+strlen(Prefix));
74     break;
75   }
76   case X86II::MO_DARWIN_NONLAZY:
77   case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
78     Name += "$non_lazy_ptr";
79     MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
80 
81     MachineModuleInfoImpl::StubValueTy &StubSym =
82       getMachOMMI().getGVStubEntry(Sym);
83     if (StubSym.getPointer() == 0) {
84       assert(MO.isGlobal() && "Extern symbol not handled yet");
85       StubSym =
86         MachineModuleInfoImpl::
87         StubValueTy(Mang->getSymbol(MO.getGlobal()),
88                     !MO.getGlobal()->hasInternalLinkage());
89     }
90     return Sym;
91   }
92   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
93     Name += "$non_lazy_ptr";
94     MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
95     MachineModuleInfoImpl::StubValueTy &StubSym =
96       getMachOMMI().getHiddenGVStubEntry(Sym);
97     if (StubSym.getPointer() == 0) {
98       assert(MO.isGlobal() && "Extern symbol not handled yet");
99       StubSym =
100         MachineModuleInfoImpl::
101         StubValueTy(Mang->getSymbol(MO.getGlobal()),
102                     !MO.getGlobal()->hasInternalLinkage());
103     }
104     return Sym;
105   }
106   case X86II::MO_DARWIN_STUB: {
107     Name += "$stub";
108     MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
109     MachineModuleInfoImpl::StubValueTy &StubSym =
110       getMachOMMI().getFnStubEntry(Sym);
111     if (StubSym.getPointer())
112       return Sym;
113 
114     if (MO.isGlobal()) {
115       StubSym =
116         MachineModuleInfoImpl::
117         StubValueTy(Mang->getSymbol(MO.getGlobal()),
118                     !MO.getGlobal()->hasInternalLinkage());
119     } else {
120       Name.erase(Name.end()-5, Name.end());
121       StubSym =
122         MachineModuleInfoImpl::
123         StubValueTy(Ctx.GetOrCreateSymbol(Name.str()), false);
124     }
125     return Sym;
126   }
127   }
128 
129   return Ctx.GetOrCreateSymbol(Name.str());
130 }
131 
LowerSymbolOperand(const MachineOperand & MO,MCSymbol * Sym) const132 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
133                                              MCSymbol *Sym) const {
134   // FIXME: We would like an efficient form for this, so we don't have to do a
135   // lot of extra uniquing.
136   const MCExpr *Expr = 0;
137   MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
138 
139   switch (MO.getTargetFlags()) {
140   default: llvm_unreachable("Unknown target flag on GV operand");
141   case X86II::MO_NO_FLAG:    // No flag.
142   // These affect the name of the symbol, not any suffix.
143   case X86II::MO_DARWIN_NONLAZY:
144   case X86II::MO_DLLIMPORT:
145   case X86II::MO_DARWIN_STUB:
146     break;
147 
148   case X86II::MO_TLVP:      RefKind = MCSymbolRefExpr::VK_TLVP; break;
149   case X86II::MO_TLVP_PIC_BASE:
150     Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
151     // Subtract the pic base.
152     Expr = MCBinaryExpr::CreateSub(Expr,
153                                   MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
154                                                            Ctx),
155                                    Ctx);
156     break;
157   case X86II::MO_TLSGD:     RefKind = MCSymbolRefExpr::VK_TLSGD; break;
158   case X86II::MO_GOTTPOFF:  RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
159   case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
160   case X86II::MO_TPOFF:     RefKind = MCSymbolRefExpr::VK_TPOFF; break;
161   case X86II::MO_NTPOFF:    RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
162   case X86II::MO_GOTPCREL:  RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
163   case X86II::MO_GOT:       RefKind = MCSymbolRefExpr::VK_GOT; break;
164   case X86II::MO_GOTOFF:    RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
165   case X86II::MO_PLT:       RefKind = MCSymbolRefExpr::VK_PLT; break;
166   case X86II::MO_PIC_BASE_OFFSET:
167   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
168   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
169     Expr = MCSymbolRefExpr::Create(Sym, Ctx);
170     // Subtract the pic base.
171     Expr = MCBinaryExpr::CreateSub(Expr,
172                             MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
173                                    Ctx);
174     if (MO.isJTI() && MAI.hasSetDirective()) {
175       // If .set directive is supported, use it to reduce the number of
176       // relocations the assembler will generate for differences between
177       // local labels. This is only safe when the symbols are in the same
178       // section so we are restricting it to jumptable references.
179       MCSymbol *Label = Ctx.CreateTempSymbol();
180       AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
181       Expr = MCSymbolRefExpr::Create(Label, Ctx);
182     }
183     break;
184   }
185 
186   if (Expr == 0)
187     Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
188 
189   if (!MO.isJTI() && MO.getOffset())
190     Expr = MCBinaryExpr::CreateAdd(Expr,
191                                    MCConstantExpr::Create(MO.getOffset(), Ctx),
192                                    Ctx);
193   return MCOperand::CreateExpr(Expr);
194 }
195 
196 
197 
lower_subreg32(MCInst * MI,unsigned OpNo)198 static void lower_subreg32(MCInst *MI, unsigned OpNo) {
199   // Convert registers in the addr mode according to subreg32.
200   unsigned Reg = MI->getOperand(OpNo).getReg();
201   if (Reg != 0)
202     MI->getOperand(OpNo).setReg(getX86SubSuperRegister(Reg, MVT::i32));
203 }
204 
lower_lea64_32mem(MCInst * MI,unsigned OpNo)205 static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) {
206   // Convert registers in the addr mode according to subreg64.
207   for (unsigned i = 0; i != 4; ++i) {
208     if (!MI->getOperand(OpNo+i).isReg()) continue;
209 
210     unsigned Reg = MI->getOperand(OpNo+i).getReg();
211     if (Reg == 0) continue;
212 
213     MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
214   }
215 }
216 
217 /// LowerSubReg32_Op0 - Things like MOVZX16rr8 -> MOVZX32rr8.
LowerSubReg32_Op0(MCInst & OutMI,unsigned NewOpc)218 static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) {
219   OutMI.setOpcode(NewOpc);
220   lower_subreg32(&OutMI, 0);
221 }
222 /// LowerUnaryToTwoAddr - R = setb   -> R = sbb R, R
LowerUnaryToTwoAddr(MCInst & OutMI,unsigned NewOpc)223 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) {
224   OutMI.setOpcode(NewOpc);
225   OutMI.addOperand(OutMI.getOperand(0));
226   OutMI.addOperand(OutMI.getOperand(0));
227 }
228 
229 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
230 /// a short fixed-register form.
SimplifyShortImmForm(MCInst & Inst,unsigned Opcode)231 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
232   unsigned ImmOp = Inst.getNumOperands() - 1;
233   assert(Inst.getOperand(0).isReg() && Inst.getOperand(ImmOp).isImm() &&
234          ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
235            Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
236           Inst.getNumOperands() == 2) && "Unexpected instruction!");
237 
238   // Check whether the destination register can be fixed.
239   unsigned Reg = Inst.getOperand(0).getReg();
240   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
241     return;
242 
243   // If so, rewrite the instruction.
244   MCOperand Saved = Inst.getOperand(ImmOp);
245   Inst = MCInst();
246   Inst.setOpcode(Opcode);
247   Inst.addOperand(Saved);
248 }
249 
250 /// \brief Simplify things like MOV32rm to MOV32o32a.
SimplifyShortMoveForm(X86AsmPrinter & Printer,MCInst & Inst,unsigned Opcode)251 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
252                                   unsigned Opcode) {
253   // Don't make these simplifications in 64-bit mode; other assemblers don't
254   // perform them because they make the code larger.
255   if (Printer.getSubtarget().is64Bit())
256     return;
257 
258   bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
259   unsigned AddrBase = IsStore;
260   unsigned RegOp = IsStore ? 0 : 5;
261   unsigned AddrOp = AddrBase + 3;
262   assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
263          Inst.getOperand(AddrBase + 0).isReg() && // base
264          Inst.getOperand(AddrBase + 1).isImm() && // scale
265          Inst.getOperand(AddrBase + 2).isReg() && // index register
266          (Inst.getOperand(AddrOp).isExpr() ||     // address
267           Inst.getOperand(AddrOp).isImm())&&
268          Inst.getOperand(AddrBase + 4).isReg() && // segment
269          "Unexpected instruction!");
270 
271   // Check whether the destination register can be fixed.
272   unsigned Reg = Inst.getOperand(RegOp).getReg();
273   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
274     return;
275 
276   // Check whether this is an absolute address.
277   // FIXME: We know TLVP symbol refs aren't, but there should be a better way
278   // to do this here.
279   bool Absolute = true;
280   if (Inst.getOperand(AddrOp).isExpr()) {
281     const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
282     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
283       if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
284         Absolute = false;
285   }
286 
287   if (Absolute &&
288       (Inst.getOperand(AddrBase + 0).getReg() != 0 ||
289        Inst.getOperand(AddrBase + 2).getReg() != 0 ||
290        Inst.getOperand(AddrBase + 4).getReg() != 0 ||
291        Inst.getOperand(AddrBase + 1).getImm() != 1))
292     return;
293 
294   // If so, rewrite the instruction.
295   MCOperand Saved = Inst.getOperand(AddrOp);
296   Inst = MCInst();
297   Inst.setOpcode(Opcode);
298   Inst.addOperand(Saved);
299 }
300 
Lower(const MachineInstr * MI,MCInst & OutMI) const301 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
302   OutMI.setOpcode(MI->getOpcode());
303 
304   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
305     const MachineOperand &MO = MI->getOperand(i);
306 
307     MCOperand MCOp;
308     switch (MO.getType()) {
309     default:
310       MI->dump();
311       llvm_unreachable("unknown operand type");
312     case MachineOperand::MO_Register:
313       // Ignore all implicit register operands.
314       if (MO.isImplicit()) continue;
315       MCOp = MCOperand::CreateReg(MO.getReg());
316       break;
317     case MachineOperand::MO_Immediate:
318       MCOp = MCOperand::CreateImm(MO.getImm());
319       break;
320     case MachineOperand::MO_MachineBasicBlock:
321       MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
322                        MO.getMBB()->getSymbol(), Ctx));
323       break;
324     case MachineOperand::MO_GlobalAddress:
325     case MachineOperand::MO_ExternalSymbol:
326       MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
327       break;
328     case MachineOperand::MO_JumpTableIndex:
329       MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
330       break;
331     case MachineOperand::MO_ConstantPoolIndex:
332       MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
333       break;
334     case MachineOperand::MO_BlockAddress:
335       MCOp = LowerSymbolOperand(MO,
336                      AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
337       break;
338     }
339 
340     OutMI.addOperand(MCOp);
341   }
342 
343   // Handle a few special cases to eliminate operand modifiers.
344 ReSimplify:
345   switch (OutMI.getOpcode()) {
346   case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand.
347     lower_lea64_32mem(&OutMI, 1);
348     // FALL THROUGH.
349   case X86::LEA64r:
350   case X86::LEA16r:
351   case X86::LEA32r:
352     // LEA should have a segment register, but it must be empty.
353     assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
354            "Unexpected # of LEA operands");
355     assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
356            "LEA has segment specified!");
357     break;
358   case X86::MOVZX64rr32:  LowerSubReg32_Op0(OutMI, X86::MOV32rr); break;
359   case X86::MOVZX64rm32:  LowerSubReg32_Op0(OutMI, X86::MOV32rm); break;
360   case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break;
361   case X86::MOVZX64rr8:   LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
362   case X86::MOVZX64rm8:   LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
363   case X86::MOVZX64rr16:  LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break;
364   case X86::MOVZX64rm16:  LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break;
365   case X86::SETB_C8r:     LowerUnaryToTwoAddr(OutMI, X86::SBB8rr); break;
366   case X86::SETB_C16r:    LowerUnaryToTwoAddr(OutMI, X86::SBB16rr); break;
367   case X86::SETB_C32r:    LowerUnaryToTwoAddr(OutMI, X86::SBB32rr); break;
368   case X86::SETB_C64r:    LowerUnaryToTwoAddr(OutMI, X86::SBB64rr); break;
369   case X86::MOV8r0:       LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break;
370   case X86::MOV32r0:      LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
371   case X86::FsFLD0SS:      LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
372   case X86::FsFLD0SD:      LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
373   case X86::VFsFLD0SS:     LowerUnaryToTwoAddr(OutMI, X86::VPXORrr); break;
374   case X86::VFsFLD0SD:     LowerUnaryToTwoAddr(OutMI, X86::VPXORrr); break;
375   case X86::V_SETALLONES:  LowerUnaryToTwoAddr(OutMI, X86::PCMPEQDrr); break;
376   case X86::AVX_SET0PSY:   LowerUnaryToTwoAddr(OutMI, X86::VXORPSYrr); break;
377   case X86::AVX_SET0PDY:   LowerUnaryToTwoAddr(OutMI, X86::VXORPDYrr); break;
378   case X86::AVX_SETALLONES:  LowerUnaryToTwoAddr(OutMI, X86::VPCMPEQDrr); break;
379 
380   case X86::MOV16r0:
381     LowerSubReg32_Op0(OutMI, X86::MOV32r0);   // MOV16r0 -> MOV32r0
382     LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
383     break;
384   case X86::MOV64r0:
385     LowerSubReg32_Op0(OutMI, X86::MOV32r0);   // MOV64r0 -> MOV32r0
386     LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
387     break;
388 
389   // TAILJMPr64, [WIN]CALL64r, [WIN]CALL64pcrel32 - These instructions have
390   // register inputs modeled as normal uses instead of implicit uses.  As such,
391   // truncate off all but the first operand (the callee).  FIXME: Change isel.
392   case X86::TAILJMPr64:
393   case X86::CALL64r:
394   case X86::CALL64pcrel32:
395   case X86::WINCALL64r:
396   case X86::WINCALL64pcrel32: {
397     unsigned Opcode = OutMI.getOpcode();
398     MCOperand Saved = OutMI.getOperand(0);
399     OutMI = MCInst();
400     OutMI.setOpcode(Opcode);
401     OutMI.addOperand(Saved);
402     break;
403   }
404 
405   case X86::EH_RETURN:
406   case X86::EH_RETURN64: {
407     OutMI = MCInst();
408     OutMI.setOpcode(X86::RET);
409     break;
410   }
411 
412   // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
413   case X86::TAILJMPr:
414   case X86::TAILJMPd:
415   case X86::TAILJMPd64: {
416     unsigned Opcode;
417     switch (OutMI.getOpcode()) {
418     default: assert(0 && "Invalid opcode");
419     case X86::TAILJMPr: Opcode = X86::JMP32r; break;
420     case X86::TAILJMPd:
421     case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
422     }
423 
424     MCOperand Saved = OutMI.getOperand(0);
425     OutMI = MCInst();
426     OutMI.setOpcode(Opcode);
427     OutMI.addOperand(Saved);
428     break;
429   }
430 
431   // These are pseudo-ops for OR to help with the OR->ADD transformation.  We do
432   // this with an ugly goto in case the resultant OR uses EAX and needs the
433   // short form.
434   case X86::ADD16rr_DB:   OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
435   case X86::ADD32rr_DB:   OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
436   case X86::ADD64rr_DB:   OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
437   case X86::ADD16ri_DB:   OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
438   case X86::ADD32ri_DB:   OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
439   case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
440   case X86::ADD16ri8_DB:  OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
441   case X86::ADD32ri8_DB:  OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
442   case X86::ADD64ri8_DB:  OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
443 
444   // The assembler backend wants to see branches in their small form and relax
445   // them to their large form.  The JIT can only handle the large form because
446   // it does not do relaxation.  For now, translate the large form to the
447   // small one here.
448   case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
449   case X86::JO_4:  OutMI.setOpcode(X86::JO_1); break;
450   case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
451   case X86::JB_4:  OutMI.setOpcode(X86::JB_1); break;
452   case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
453   case X86::JE_4:  OutMI.setOpcode(X86::JE_1); break;
454   case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
455   case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
456   case X86::JA_4:  OutMI.setOpcode(X86::JA_1); break;
457   case X86::JS_4:  OutMI.setOpcode(X86::JS_1); break;
458   case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
459   case X86::JP_4:  OutMI.setOpcode(X86::JP_1); break;
460   case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
461   case X86::JL_4:  OutMI.setOpcode(X86::JL_1); break;
462   case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
463   case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
464   case X86::JG_4:  OutMI.setOpcode(X86::JG_1); break;
465 
466   // Atomic load and store require a separate pseudo-inst because Acquire
467   // implies mayStore and Release implies mayLoad; fix these to regular MOV
468   // instructions here
469   case X86::ACQUIRE_MOV8rm:  OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
470   case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
471   case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
472   case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
473   case X86::RELEASE_MOV8mr:  OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
474   case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
475   case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
476   case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
477 
478   // We don't currently select the correct instruction form for instructions
479   // which have a short %eax, etc. form. Handle this by custom lowering, for
480   // now.
481   //
482   // Note, we are currently not handling the following instructions:
483   // MOV64ao8, MOV64o8a
484   // XCHG16ar, XCHG32ar, XCHG64ar
485   case X86::MOV8mr_NOREX:
486   case X86::MOV8mr:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
487   case X86::MOV8rm_NOREX:
488   case X86::MOV8rm:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
489   case X86::MOV16mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
490   case X86::MOV16rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
491   case X86::MOV32mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
492   case X86::MOV32rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
493 
494   case X86::ADC8ri:     SimplifyShortImmForm(OutMI, X86::ADC8i8);    break;
495   case X86::ADC16ri:    SimplifyShortImmForm(OutMI, X86::ADC16i16);  break;
496   case X86::ADC32ri:    SimplifyShortImmForm(OutMI, X86::ADC32i32);  break;
497   case X86::ADC64ri32:  SimplifyShortImmForm(OutMI, X86::ADC64i32);  break;
498   case X86::ADD8ri:     SimplifyShortImmForm(OutMI, X86::ADD8i8);    break;
499   case X86::ADD16ri:    SimplifyShortImmForm(OutMI, X86::ADD16i16);  break;
500   case X86::ADD32ri:    SimplifyShortImmForm(OutMI, X86::ADD32i32);  break;
501   case X86::ADD64ri32:  SimplifyShortImmForm(OutMI, X86::ADD64i32);  break;
502   case X86::AND8ri:     SimplifyShortImmForm(OutMI, X86::AND8i8);    break;
503   case X86::AND16ri:    SimplifyShortImmForm(OutMI, X86::AND16i16);  break;
504   case X86::AND32ri:    SimplifyShortImmForm(OutMI, X86::AND32i32);  break;
505   case X86::AND64ri32:  SimplifyShortImmForm(OutMI, X86::AND64i32);  break;
506   case X86::CMP8ri:     SimplifyShortImmForm(OutMI, X86::CMP8i8);    break;
507   case X86::CMP16ri:    SimplifyShortImmForm(OutMI, X86::CMP16i16);  break;
508   case X86::CMP32ri:    SimplifyShortImmForm(OutMI, X86::CMP32i32);  break;
509   case X86::CMP64ri32:  SimplifyShortImmForm(OutMI, X86::CMP64i32);  break;
510   case X86::OR8ri:      SimplifyShortImmForm(OutMI, X86::OR8i8);     break;
511   case X86::OR16ri:     SimplifyShortImmForm(OutMI, X86::OR16i16);   break;
512   case X86::OR32ri:     SimplifyShortImmForm(OutMI, X86::OR32i32);   break;
513   case X86::OR64ri32:   SimplifyShortImmForm(OutMI, X86::OR64i32);   break;
514   case X86::SBB8ri:     SimplifyShortImmForm(OutMI, X86::SBB8i8);    break;
515   case X86::SBB16ri:    SimplifyShortImmForm(OutMI, X86::SBB16i16);  break;
516   case X86::SBB32ri:    SimplifyShortImmForm(OutMI, X86::SBB32i32);  break;
517   case X86::SBB64ri32:  SimplifyShortImmForm(OutMI, X86::SBB64i32);  break;
518   case X86::SUB8ri:     SimplifyShortImmForm(OutMI, X86::SUB8i8);    break;
519   case X86::SUB16ri:    SimplifyShortImmForm(OutMI, X86::SUB16i16);  break;
520   case X86::SUB32ri:    SimplifyShortImmForm(OutMI, X86::SUB32i32);  break;
521   case X86::SUB64ri32:  SimplifyShortImmForm(OutMI, X86::SUB64i32);  break;
522   case X86::TEST8ri:    SimplifyShortImmForm(OutMI, X86::TEST8i8);   break;
523   case X86::TEST16ri:   SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
524   case X86::TEST32ri:   SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
525   case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
526   case X86::XOR8ri:     SimplifyShortImmForm(OutMI, X86::XOR8i8);    break;
527   case X86::XOR16ri:    SimplifyShortImmForm(OutMI, X86::XOR16i16);  break;
528   case X86::XOR32ri:    SimplifyShortImmForm(OutMI, X86::XOR32i32);  break;
529   case X86::XOR64ri32:  SimplifyShortImmForm(OutMI, X86::XOR64i32);  break;
530   }
531 }
532 
LowerTlsAddr(MCStreamer & OutStreamer,X86MCInstLower & MCInstLowering,const MachineInstr & MI)533 static void LowerTlsAddr(MCStreamer &OutStreamer,
534                          X86MCInstLower &MCInstLowering,
535                          const MachineInstr &MI) {
536   bool is64Bits = MI.getOpcode() == X86::TLS_addr64;
537   MCContext &context = OutStreamer.getContext();
538 
539   if (is64Bits) {
540     MCInst prefix;
541     prefix.setOpcode(X86::DATA16_PREFIX);
542     OutStreamer.EmitInstruction(prefix);
543   }
544   MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
545   const MCSymbolRefExpr *symRef =
546     MCSymbolRefExpr::Create(sym, MCSymbolRefExpr::VK_TLSGD, context);
547 
548   MCInst LEA;
549   if (is64Bits) {
550     LEA.setOpcode(X86::LEA64r);
551     LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
552     LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
553     LEA.addOperand(MCOperand::CreateImm(1));        // scale
554     LEA.addOperand(MCOperand::CreateReg(0));        // index
555     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
556     LEA.addOperand(MCOperand::CreateReg(0));        // seg
557   } else {
558     LEA.setOpcode(X86::LEA32r);
559     LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
560     LEA.addOperand(MCOperand::CreateReg(0));        // base
561     LEA.addOperand(MCOperand::CreateImm(1));        // scale
562     LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
563     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
564     LEA.addOperand(MCOperand::CreateReg(0));        // seg
565   }
566   OutStreamer.EmitInstruction(LEA);
567 
568   if (is64Bits) {
569     MCInst prefix;
570     prefix.setOpcode(X86::DATA16_PREFIX);
571     OutStreamer.EmitInstruction(prefix);
572     prefix.setOpcode(X86::DATA16_PREFIX);
573     OutStreamer.EmitInstruction(prefix);
574     prefix.setOpcode(X86::REX64_PREFIX);
575     OutStreamer.EmitInstruction(prefix);
576   }
577 
578   MCInst call;
579   if (is64Bits)
580     call.setOpcode(X86::CALL64pcrel32);
581   else
582     call.setOpcode(X86::CALLpcrel32);
583   StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
584   MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
585   const MCSymbolRefExpr *tlsRef =
586     MCSymbolRefExpr::Create(tlsGetAddr,
587                             MCSymbolRefExpr::VK_PLT,
588                             context);
589 
590   call.addOperand(MCOperand::CreateExpr(tlsRef));
591   OutStreamer.EmitInstruction(call);
592 }
593 
EmitInstruction(const MachineInstr * MI)594 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
595   OutStreamer.EmitCodeRegion();
596 
597   X86MCInstLower MCInstLowering(Mang, *MF, *this);
598   switch (MI->getOpcode()) {
599   case TargetOpcode::DBG_VALUE:
600     if (isVerbose() && OutStreamer.hasRawTextSupport()) {
601       std::string TmpStr;
602       raw_string_ostream OS(TmpStr);
603       PrintDebugValueComment(MI, OS);
604       OutStreamer.EmitRawText(StringRef(OS.str()));
605     }
606     return;
607 
608   // Emit nothing here but a comment if we can.
609   case X86::Int_MemBarrier:
610     if (OutStreamer.hasRawTextSupport())
611       OutStreamer.EmitRawText(StringRef("\t#MEMBARRIER"));
612     return;
613 
614 
615   case X86::EH_RETURN:
616   case X86::EH_RETURN64: {
617     // Lower these as normal, but add some comments.
618     unsigned Reg = MI->getOperand(0).getReg();
619     OutStreamer.AddComment(StringRef("eh_return, addr: %") +
620                            X86ATTInstPrinter::getRegisterName(Reg));
621     break;
622   }
623   case X86::TAILJMPr:
624   case X86::TAILJMPd:
625   case X86::TAILJMPd64:
626     // Lower these as normal, but add some comments.
627     OutStreamer.AddComment("TAILCALL");
628     break;
629 
630   case X86::TLS_addr32:
631   case X86::TLS_addr64:
632     return LowerTlsAddr(OutStreamer, MCInstLowering, *MI);
633 
634   case X86::MOVPC32r: {
635     MCInst TmpInst;
636     // This is a pseudo op for a two instruction sequence with a label, which
637     // looks like:
638     //     call "L1$pb"
639     // "L1$pb":
640     //     popl %esi
641 
642     // Emit the call.
643     MCSymbol *PICBase = MF->getPICBaseSymbol();
644     TmpInst.setOpcode(X86::CALLpcrel32);
645     // FIXME: We would like an efficient form for this, so we don't have to do a
646     // lot of extra uniquing.
647     TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(PICBase,
648                                                                  OutContext)));
649     OutStreamer.EmitInstruction(TmpInst);
650 
651     // Emit the label.
652     OutStreamer.EmitLabel(PICBase);
653 
654     // popl $reg
655     TmpInst.setOpcode(X86::POP32r);
656     TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg());
657     OutStreamer.EmitInstruction(TmpInst);
658     return;
659   }
660 
661   case X86::ADD32ri: {
662     // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
663     if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
664       break;
665 
666     // Okay, we have something like:
667     //  EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
668 
669     // For this, we want to print something like:
670     //   MYGLOBAL + (. - PICBASE)
671     // However, we can't generate a ".", so just emit a new label here and refer
672     // to it.
673     MCSymbol *DotSym = OutContext.CreateTempSymbol();
674     OutStreamer.EmitLabel(DotSym);
675 
676     // Now that we have emitted the label, lower the complex operand expression.
677     MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
678 
679     const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
680     const MCExpr *PICBase =
681       MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
682     DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
683 
684     DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
685                                       DotExpr, OutContext);
686 
687     MCInst TmpInst;
688     TmpInst.setOpcode(X86::ADD32ri);
689     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
690     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
691     TmpInst.addOperand(MCOperand::CreateExpr(DotExpr));
692     OutStreamer.EmitInstruction(TmpInst);
693     return;
694   }
695   }
696 
697   MCInst TmpInst;
698   MCInstLowering.Lower(MI, TmpInst);
699   OutStreamer.EmitInstruction(TmpInst);
700 }
701 
702