1; RUN: llc < %s -verify-machineinstrs -spiller=standard
2; RUN: llc < %s -verify-machineinstrs -spiller=inline
3; PR8612
4;
5; This test has an inline asm with early-clobber arguments.
6; It is big enough that one of the early clobber registers is spilled.
7;
8; All the spillers would get the live ranges wrong when spilling an early
9; clobber, allowing the undef register to be allocated to the same register as
10; the early clobber.
11;
12target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32"
13target triple = "armv7-eabi"
14
15%0 = type { i32, i32 }
16
17define void @foo(i32* %in) nounwind {
18entry:
19  br label %bb.i
20
21bb.i:                                             ; preds = %bb.i, %entry
22  br i1 undef, label %bb10.preheader.i, label %bb.i
23
24bb10.preheader.i:                                 ; preds = %bb.i
25  br label %bb10.i
26
27bb10.i:                                           ; preds = %bb10.i, %bb10.preheader.i
28  br i1 undef, label %bb27.i, label %bb10.i
29
30bb27.i:                                           ; preds = %bb10.i
31  br label %bb28.i
32
33bb28.i:                                           ; preds = %bb28.i, %bb27.i
34  br i1 undef, label %presymmetry.exit, label %bb28.i
35
36presymmetry.exit:                                 ; preds = %bb28.i
37  %tmp175387 = or i32 undef, 12
38  %scevgep101.i = getelementptr i32* %in, i32 undef
39  %tmp189401 = or i32 undef, 7
40  %scevgep97.i = getelementptr i32* %in, i32 undef
41  %tmp198410 = or i32 undef, 1
42  %scevgep.i48 = getelementptr i32* %in, i32 undef
43  %0 = load i32* %scevgep.i48, align 4
44  %1 = add nsw i32 %0, 0
45  store i32 %1, i32* undef, align 4
46  %asmtmp.i.i33.i.i.i = tail call %0 asm "smull\09$0, $1, $2, $3", "=&r,=&r,%r,r,~{cc}"(i32 undef, i32 1518500250) nounwind
47  %asmresult1.i.i34.i.i.i = extractvalue %0 %asmtmp.i.i33.i.i.i, 1
48  %2 = shl i32 %asmresult1.i.i34.i.i.i, 1
49  %3 = load i32* null, align 4
50  %4 = load i32* undef, align 4
51  %5 = sub nsw i32 %3, %4
52  %6 = load i32* undef, align 4
53  %7 = load i32* null, align 4
54  %8 = sub nsw i32 %6, %7
55  %9 = load i32* %scevgep97.i, align 4
56  %10 = load i32* undef, align 4
57  %11 = sub nsw i32 %9, %10
58  %12 = load i32* null, align 4
59  %13 = load i32* %scevgep101.i, align 4
60  %14 = sub nsw i32 %12, %13
61  %15 = load i32* %scevgep.i48, align 4
62  %16 = load i32* null, align 4
63  %17 = add nsw i32 %16, %15
64  %18 = sub nsw i32 %15, %16
65  %19 = load i32* undef, align 4
66  %20 = add nsw i32 %19, %2
67  %21 = sub nsw i32 %19, %2
68  %22 = add nsw i32 %14, %5
69  %23 = sub nsw i32 %5, %14
70  %24 = add nsw i32 %11, %8
71  %25 = sub nsw i32 %8, %11
72  %26 = add nsw i32 %21, %23
73  store i32 %26, i32* %scevgep.i48, align 4
74  %27 = sub nsw i32 %25, %18
75  store i32 %27, i32* null, align 4
76  %28 = sub nsw i32 %23, %21
77  store i32 %28, i32* undef, align 4
78  %29 = add nsw i32 %18, %25
79  store i32 %29, i32* undef, align 4
80  %30 = add nsw i32 %17, %22
81  store i32 %30, i32* %scevgep101.i, align 4
82  %31 = add nsw i32 %20, %24
83  store i32 %31, i32* null, align 4
84  unreachable
85}
86