1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Target Register Enum Values                                                *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass ARMMCRegisterClasses[];
17
18namespace ARM {
19enum {
20  NoRegister,
21  APSR = 1,
22  APSR_NZCV = 2,
23  CPSR = 3,
24  FPEXC = 4,
25  FPINST = 5,
26  FPSCR = 6,
27  FPSCR_NZCV = 7,
28  FPSID = 8,
29  ITSTATE = 9,
30  LR = 10,
31  PC = 11,
32  SP = 12,
33  SPSR = 13,
34  D0 = 14,
35  D1 = 15,
36  D2 = 16,
37  D3 = 17,
38  D4 = 18,
39  D5 = 19,
40  D6 = 20,
41  D7 = 21,
42  D8 = 22,
43  D9 = 23,
44  D10 = 24,
45  D11 = 25,
46  D12 = 26,
47  D13 = 27,
48  D14 = 28,
49  D15 = 29,
50  D16 = 30,
51  D17 = 31,
52  D18 = 32,
53  D19 = 33,
54  D20 = 34,
55  D21 = 35,
56  D22 = 36,
57  D23 = 37,
58  D24 = 38,
59  D25 = 39,
60  D26 = 40,
61  D27 = 41,
62  D28 = 42,
63  D29 = 43,
64  D30 = 44,
65  D31 = 45,
66  FPINST2 = 46,
67  MVFR0 = 47,
68  MVFR1 = 48,
69  MVFR2 = 49,
70  Q0 = 50,
71  Q1 = 51,
72  Q2 = 52,
73  Q3 = 53,
74  Q4 = 54,
75  Q5 = 55,
76  Q6 = 56,
77  Q7 = 57,
78  Q8 = 58,
79  Q9 = 59,
80  Q10 = 60,
81  Q11 = 61,
82  Q12 = 62,
83  Q13 = 63,
84  Q14 = 64,
85  Q15 = 65,
86  R0 = 66,
87  R1 = 67,
88  R2 = 68,
89  R3 = 69,
90  R4 = 70,
91  R5 = 71,
92  R6 = 72,
93  R7 = 73,
94  R8 = 74,
95  R9 = 75,
96  R10 = 76,
97  R11 = 77,
98  R12 = 78,
99  S0 = 79,
100  S1 = 80,
101  S2 = 81,
102  S3 = 82,
103  S4 = 83,
104  S5 = 84,
105  S6 = 85,
106  S7 = 86,
107  S8 = 87,
108  S9 = 88,
109  S10 = 89,
110  S11 = 90,
111  S12 = 91,
112  S13 = 92,
113  S14 = 93,
114  S15 = 94,
115  S16 = 95,
116  S17 = 96,
117  S18 = 97,
118  S19 = 98,
119  S20 = 99,
120  S21 = 100,
121  S22 = 101,
122  S23 = 102,
123  S24 = 103,
124  S25 = 104,
125  S26 = 105,
126  S27 = 106,
127  S28 = 107,
128  S29 = 108,
129  S30 = 109,
130  S31 = 110,
131  D0_D2 = 111,
132  D1_D3 = 112,
133  D2_D4 = 113,
134  D3_D5 = 114,
135  D4_D6 = 115,
136  D5_D7 = 116,
137  D6_D8 = 117,
138  D7_D9 = 118,
139  D8_D10 = 119,
140  D9_D11 = 120,
141  D10_D12 = 121,
142  D11_D13 = 122,
143  D12_D14 = 123,
144  D13_D15 = 124,
145  D14_D16 = 125,
146  D15_D17 = 126,
147  D16_D18 = 127,
148  D17_D19 = 128,
149  D18_D20 = 129,
150  D19_D21 = 130,
151  D20_D22 = 131,
152  D21_D23 = 132,
153  D22_D24 = 133,
154  D23_D25 = 134,
155  D24_D26 = 135,
156  D25_D27 = 136,
157  D26_D28 = 137,
158  D27_D29 = 138,
159  D28_D30 = 139,
160  D29_D31 = 140,
161  Q0_Q1 = 141,
162  Q1_Q2 = 142,
163  Q2_Q3 = 143,
164  Q3_Q4 = 144,
165  Q4_Q5 = 145,
166  Q5_Q6 = 146,
167  Q6_Q7 = 147,
168  Q7_Q8 = 148,
169  Q8_Q9 = 149,
170  Q9_Q10 = 150,
171  Q10_Q11 = 151,
172  Q11_Q12 = 152,
173  Q12_Q13 = 153,
174  Q13_Q14 = 154,
175  Q14_Q15 = 155,
176  Q0_Q1_Q2_Q3 = 156,
177  Q1_Q2_Q3_Q4 = 157,
178  Q2_Q3_Q4_Q5 = 158,
179  Q3_Q4_Q5_Q6 = 159,
180  Q4_Q5_Q6_Q7 = 160,
181  Q5_Q6_Q7_Q8 = 161,
182  Q6_Q7_Q8_Q9 = 162,
183  Q7_Q8_Q9_Q10 = 163,
184  Q8_Q9_Q10_Q11 = 164,
185  Q9_Q10_Q11_Q12 = 165,
186  Q10_Q11_Q12_Q13 = 166,
187  Q11_Q12_Q13_Q14 = 167,
188  Q12_Q13_Q14_Q15 = 168,
189  R12_SP = 169,
190  R0_R1 = 170,
191  R2_R3 = 171,
192  R4_R5 = 172,
193  R6_R7 = 173,
194  R8_R9 = 174,
195  R10_R11 = 175,
196  D0_D1_D2 = 176,
197  D1_D2_D3 = 177,
198  D2_D3_D4 = 178,
199  D3_D4_D5 = 179,
200  D4_D5_D6 = 180,
201  D5_D6_D7 = 181,
202  D6_D7_D8 = 182,
203  D7_D8_D9 = 183,
204  D8_D9_D10 = 184,
205  D9_D10_D11 = 185,
206  D10_D11_D12 = 186,
207  D11_D12_D13 = 187,
208  D12_D13_D14 = 188,
209  D13_D14_D15 = 189,
210  D14_D15_D16 = 190,
211  D15_D16_D17 = 191,
212  D16_D17_D18 = 192,
213  D17_D18_D19 = 193,
214  D18_D19_D20 = 194,
215  D19_D20_D21 = 195,
216  D20_D21_D22 = 196,
217  D21_D22_D23 = 197,
218  D22_D23_D24 = 198,
219  D23_D24_D25 = 199,
220  D24_D25_D26 = 200,
221  D25_D26_D27 = 201,
222  D26_D27_D28 = 202,
223  D27_D28_D29 = 203,
224  D28_D29_D30 = 204,
225  D29_D30_D31 = 205,
226  D0_D2_D4 = 206,
227  D1_D3_D5 = 207,
228  D2_D4_D6 = 208,
229  D3_D5_D7 = 209,
230  D4_D6_D8 = 210,
231  D5_D7_D9 = 211,
232  D6_D8_D10 = 212,
233  D7_D9_D11 = 213,
234  D8_D10_D12 = 214,
235  D9_D11_D13 = 215,
236  D10_D12_D14 = 216,
237  D11_D13_D15 = 217,
238  D12_D14_D16 = 218,
239  D13_D15_D17 = 219,
240  D14_D16_D18 = 220,
241  D15_D17_D19 = 221,
242  D16_D18_D20 = 222,
243  D17_D19_D21 = 223,
244  D18_D20_D22 = 224,
245  D19_D21_D23 = 225,
246  D20_D22_D24 = 226,
247  D21_D23_D25 = 227,
248  D22_D24_D26 = 228,
249  D23_D25_D27 = 229,
250  D24_D26_D28 = 230,
251  D25_D27_D29 = 231,
252  D26_D28_D30 = 232,
253  D27_D29_D31 = 233,
254  D0_D2_D4_D6 = 234,
255  D1_D3_D5_D7 = 235,
256  D2_D4_D6_D8 = 236,
257  D3_D5_D7_D9 = 237,
258  D4_D6_D8_D10 = 238,
259  D5_D7_D9_D11 = 239,
260  D6_D8_D10_D12 = 240,
261  D7_D9_D11_D13 = 241,
262  D8_D10_D12_D14 = 242,
263  D9_D11_D13_D15 = 243,
264  D10_D12_D14_D16 = 244,
265  D11_D13_D15_D17 = 245,
266  D12_D14_D16_D18 = 246,
267  D13_D15_D17_D19 = 247,
268  D14_D16_D18_D20 = 248,
269  D15_D17_D19_D21 = 249,
270  D16_D18_D20_D22 = 250,
271  D17_D19_D21_D23 = 251,
272  D18_D20_D22_D24 = 252,
273  D19_D21_D23_D25 = 253,
274  D20_D22_D24_D26 = 254,
275  D21_D23_D25_D27 = 255,
276  D22_D24_D26_D28 = 256,
277  D23_D25_D27_D29 = 257,
278  D24_D26_D28_D30 = 258,
279  D25_D27_D29_D31 = 259,
280  D1_D2 = 260,
281  D3_D4 = 261,
282  D5_D6 = 262,
283  D7_D8 = 263,
284  D9_D10 = 264,
285  D11_D12 = 265,
286  D13_D14 = 266,
287  D15_D16 = 267,
288  D17_D18 = 268,
289  D19_D20 = 269,
290  D21_D22 = 270,
291  D23_D24 = 271,
292  D25_D26 = 272,
293  D27_D28 = 273,
294  D29_D30 = 274,
295  D1_D2_D3_D4 = 275,
296  D3_D4_D5_D6 = 276,
297  D5_D6_D7_D8 = 277,
298  D7_D8_D9_D10 = 278,
299  D9_D10_D11_D12 = 279,
300  D11_D12_D13_D14 = 280,
301  D13_D14_D15_D16 = 281,
302  D15_D16_D17_D18 = 282,
303  D17_D18_D19_D20 = 283,
304  D19_D20_D21_D22 = 284,
305  D21_D22_D23_D24 = 285,
306  D23_D24_D25_D26 = 286,
307  D25_D26_D27_D28 = 287,
308  D27_D28_D29_D30 = 288,
309  NUM_TARGET_REGS 	// 289
310};
311} // end namespace ARM
312
313// Register classes
314
315namespace ARM {
316enum {
317  HPRRegClassID = 0,
318  SPRRegClassID = 1,
319  GPRRegClassID = 2,
320  GPRwithAPSRRegClassID = 3,
321  SPR_8RegClassID = 4,
322  GPRnopcRegClassID = 5,
323  rGPRRegClassID = 6,
324  tGPRwithpcRegClassID = 7,
325  hGPRRegClassID = 8,
326  tGPRRegClassID = 9,
327  GPRnopc_and_hGPRRegClassID = 10,
328  hGPR_and_rGPRRegClassID = 11,
329  tcGPRRegClassID = 12,
330  tGPR_and_tcGPRRegClassID = 13,
331  CCRRegClassID = 14,
332  GPRspRegClassID = 15,
333  hGPR_and_tGPRwithpcRegClassID = 16,
334  hGPR_and_tcGPRRegClassID = 17,
335  DPRRegClassID = 18,
336  DPR_VFP2RegClassID = 19,
337  DPR_8RegClassID = 20,
338  GPRPairRegClassID = 21,
339  GPRPair_with_gsub_1_in_rGPRRegClassID = 22,
340  GPRPair_with_gsub_0_in_tGPRRegClassID = 23,
341  GPRPair_with_gsub_0_in_hGPRRegClassID = 24,
342  GPRPair_with_gsub_0_in_tcGPRRegClassID = 25,
343  GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID = 26,
344  GPRPair_with_gsub_1_in_tcGPRRegClassID = 27,
345  GPRPair_with_gsub_1_in_GPRspRegClassID = 28,
346  DPairSpcRegClassID = 29,
347  DPairSpc_with_ssub_0RegClassID = 30,
348  DPairSpc_with_ssub_4RegClassID = 31,
349  DPairSpc_with_dsub_0_in_DPR_8RegClassID = 32,
350  DPairSpc_with_dsub_2_in_DPR_8RegClassID = 33,
351  DPairRegClassID = 34,
352  DPair_with_ssub_0RegClassID = 35,
353  QPRRegClassID = 36,
354  DPair_with_ssub_2RegClassID = 37,
355  DPair_with_dsub_0_in_DPR_8RegClassID = 38,
356  QPR_VFP2RegClassID = 39,
357  DPair_with_dsub_1_in_DPR_8RegClassID = 40,
358  QPR_8RegClassID = 41,
359  DTripleRegClassID = 42,
360  DTripleSpcRegClassID = 43,
361  DTripleSpc_with_ssub_0RegClassID = 44,
362  DTriple_with_ssub_0RegClassID = 45,
363  DTriple_with_qsub_0_in_QPRRegClassID = 46,
364  DTriple_with_ssub_2RegClassID = 47,
365  DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 48,
366  DTripleSpc_with_ssub_4RegClassID = 49,
367  DTriple_with_ssub_4RegClassID = 50,
368  DTripleSpc_with_ssub_8RegClassID = 51,
369  DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 52,
370  DTriple_with_dsub_0_in_DPR_8RegClassID = 53,
371  DTriple_with_qsub_0_in_QPR_VFP2RegClassID = 54,
372  DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 55,
373  DTriple_with_dsub_1_in_DPR_8RegClassID = 56,
374  DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID = 57,
375  DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClassID = 58,
376  DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 59,
377  DTriple_with_dsub_2_in_DPR_8RegClassID = 60,
378  DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 61,
379  DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 62,
380  DTriple_with_qsub_0_in_QPR_8RegClassID = 63,
381  DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID = 64,
382  DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 65,
383  DQuadSpcRegClassID = 66,
384  DQuadSpc_with_ssub_0RegClassID = 67,
385  DQuadSpc_with_ssub_4RegClassID = 68,
386  DQuadSpc_with_ssub_8RegClassID = 69,
387  DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 70,
388  DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 71,
389  DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 72,
390  DQuadRegClassID = 73,
391  DQuad_with_ssub_0RegClassID = 74,
392  DQuad_with_ssub_2RegClassID = 75,
393  QQPRRegClassID = 76,
394  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 77,
395  DQuad_with_ssub_4RegClassID = 78,
396  DQuad_with_ssub_6RegClassID = 79,
397  DQuad_with_dsub_0_in_DPR_8RegClassID = 80,
398  DQuad_with_qsub_0_in_QPR_VFP2RegClassID = 81,
399  DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 82,
400  DQuad_with_dsub_1_in_DPR_8RegClassID = 83,
401  DQuad_with_qsub_1_in_QPR_VFP2RegClassID = 84,
402  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID = 85,
403  DQuad_with_dsub_2_in_DPR_8RegClassID = 86,
404  DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 87,
405  DQuad_with_dsub_3_in_DPR_8RegClassID = 88,
406  DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 89,
407  DQuad_with_qsub_0_in_QPR_8RegClassID = 90,
408  DQuad_with_qsub_1_in_QPR_8RegClassID = 91,
409  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 92,
410  DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 93,
411  QQQQPRRegClassID = 94,
412  QQQQPR_with_ssub_0RegClassID = 95,
413  QQQQPR_with_ssub_4RegClassID = 96,
414  QQQQPR_with_ssub_8RegClassID = 97,
415  QQQQPR_with_ssub_12RegClassID = 98,
416  QQQQPR_with_dsub_0_in_DPR_8RegClassID = 99,
417  QQQQPR_with_dsub_2_in_DPR_8RegClassID = 100,
418  QQQQPR_with_dsub_4_in_DPR_8RegClassID = 101,
419  QQQQPR_with_dsub_6_in_DPR_8RegClassID = 102,
420
421  };
422} // end namespace ARM
423
424
425// Subregister indices
426
427namespace ARM {
428enum {
429  NoSubRegister,
430  dsub_0,	// 1
431  dsub_1,	// 2
432  dsub_2,	// 3
433  dsub_3,	// 4
434  dsub_4,	// 5
435  dsub_5,	// 6
436  dsub_6,	// 7
437  dsub_7,	// 8
438  gsub_0,	// 9
439  gsub_1,	// 10
440  qqsub_0,	// 11
441  qqsub_1,	// 12
442  qsub_0,	// 13
443  qsub_1,	// 14
444  qsub_2,	// 15
445  qsub_3,	// 16
446  ssub_0,	// 17
447  ssub_1,	// 18
448  ssub_2,	// 19
449  ssub_3,	// 20
450  ssub_4,	// 21
451  ssub_5,	// 22
452  ssub_6,	// 23
453  ssub_7,	// 24
454  ssub_8,	// 25
455  ssub_9,	// 26
456  ssub_10,	// 27
457  ssub_11,	// 28
458  ssub_12,	// 29
459  ssub_13,	// 30
460  dsub_7_then_ssub_0,	// 31
461  dsub_7_then_ssub_1,	// 32
462  ssub_0_ssub_1_ssub_4_ssub_5,	// 33
463  ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5,	// 34
464  ssub_2_ssub_3_ssub_6_ssub_7,	// 35
465  ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7,	// 36
466  ssub_2_ssub_3_ssub_4_ssub_5,	// 37
467  ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9,	// 38
468  ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13,	// 39
469  ssub_2_ssub_3_ssub_6_ssub_7_dsub_5,	// 40
470  ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7,	// 41
471  ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9,	// 42
472  ssub_4_ssub_5_ssub_8_ssub_9,	// 43
473  ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9,	// 44
474  ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13,	// 45
475  ssub_6_ssub_7_dsub_5,	// 46
476  ssub_6_ssub_7_ssub_8_ssub_9_dsub_5,	// 47
477  ssub_6_ssub_7_dsub_5_dsub_7,	// 48
478  ssub_6_ssub_7_ssub_8_ssub_9,	// 49
479  ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13,	// 50
480  ssub_8_ssub_9_ssub_12_ssub_13,	// 51
481  ssub_8_ssub_9_dsub_5_ssub_12_ssub_13,	// 52
482  dsub_5_dsub_7,	// 53
483  dsub_5_ssub_12_ssub_13_dsub_7,	// 54
484  dsub_5_ssub_12_ssub_13,	// 55
485  ssub_4_ssub_5_ssub_6_ssub_7_qsub_2,	// 56
486  NUM_TARGET_SUBREGS
487};
488} // end namespace ARM
489
490} // end namespace llvm
491
492#endif // GET_REGINFO_ENUM
493
494/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
495|*                                                                            *|
496|* MC Register Information                                                    *|
497|*                                                                            *|
498|* Automatically generated file, do not edit!                                 *|
499|*                                                                            *|
500\*===----------------------------------------------------------------------===*/
501
502
503#ifdef GET_REGINFO_MC_DESC
504#undef GET_REGINFO_MC_DESC
505
506namespace llvm {
507
508extern const MCPhysReg ARMRegDiffLists[] = {
509  /* 0 */ 64924, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
510  /* 17 */ 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
511  /* 32 */ 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
512  /* 45 */ 40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
513  /* 56 */ 64450, 1, 1, 1, 1, 1, 1, 1, 0,
514  /* 65 */ 64984, 1, 1, 1, 1, 1, 1, 1, 0,
515  /* 74 */ 65252, 1, 1, 1, 1, 1, 1, 1, 0,
516  /* 83 */ 38, 1, 1, 1, 1, 1, 1, 0,
517  /* 91 */ 40, 1, 1, 1, 1, 1, 0,
518  /* 98 */ 65196, 1, 1, 1, 1, 1, 0,
519  /* 105 */ 40, 1, 1, 1, 1, 0,
520  /* 111 */ 42, 1, 1, 1, 1, 0,
521  /* 117 */ 42, 1, 1, 1, 0,
522  /* 122 */ 64510, 1, 1, 1, 0,
523  /* 127 */ 65015, 1, 1, 1, 0,
524  /* 132 */ 65282, 1, 1, 1, 0,
525  /* 137 */ 65348, 1, 1, 1, 0,
526  /* 142 */ 13, 1, 1, 0,
527  /* 146 */ 42, 1, 1, 0,
528  /* 150 */ 65388, 1, 1, 0,
529  /* 154 */ 137, 65489, 48, 65489, 12, 121, 65416, 1, 1, 0,
530  /* 164 */ 136, 65490, 47, 65490, 12, 121, 65416, 1, 1, 0,
531  /* 174 */ 135, 65491, 46, 65491, 12, 121, 65416, 1, 1, 0,
532  /* 184 */ 134, 65492, 45, 65492, 12, 121, 65416, 1, 1, 0,
533  /* 194 */ 133, 65493, 44, 65493, 12, 121, 65416, 1, 1, 0,
534  /* 204 */ 132, 65494, 43, 65494, 12, 121, 65416, 1, 1, 0,
535  /* 214 */ 131, 65495, 42, 65495, 12, 121, 65416, 1, 1, 0,
536  /* 224 */ 130, 65496, 41, 65496, 12, 121, 65416, 1, 1, 0,
537  /* 234 */ 129, 65497, 40, 65497, 12, 121, 65416, 1, 1, 0,
538  /* 244 */ 128, 65498, 39, 65498, 12, 121, 65416, 1, 1, 0,
539  /* 254 */ 65489, 133, 65416, 1, 1, 0,
540  /* 260 */ 65490, 133, 65416, 1, 1, 0,
541  /* 266 */ 65491, 133, 65416, 1, 1, 0,
542  /* 272 */ 65492, 133, 65416, 1, 1, 0,
543  /* 278 */ 65493, 133, 65416, 1, 1, 0,
544  /* 284 */ 65494, 133, 65416, 1, 1, 0,
545  /* 290 */ 65495, 133, 65416, 1, 1, 0,
546  /* 296 */ 65496, 133, 65416, 1, 1, 0,
547  /* 302 */ 65497, 133, 65416, 1, 1, 0,
548  /* 308 */ 65498, 133, 65416, 1, 1, 0,
549  /* 314 */ 127, 65499, 38, 65499, 133, 65416, 1, 1, 0,
550  /* 323 */ 65080, 1, 3, 1, 3, 1, 3, 1, 0,
551  /* 332 */ 65136, 1, 3, 1, 3, 1, 0,
552  /* 339 */ 65326, 1, 3, 1, 0,
553  /* 344 */ 13, 1, 0,
554  /* 347 */ 14, 1, 0,
555  /* 350 */ 65, 1, 0,
556  /* 353 */ 65500, 65, 1, 65471, 66, 1, 0,
557  /* 360 */ 65291, 66, 1, 65470, 67, 1, 0,
558  /* 367 */ 65439, 65, 1, 65472, 67, 1, 0,
559  /* 374 */ 65501, 67, 1, 65469, 68, 1, 0,
560  /* 381 */ 65439, 66, 1, 65471, 68, 1, 0,
561  /* 388 */ 65292, 68, 1, 65468, 69, 1, 0,
562  /* 395 */ 65439, 67, 1, 65470, 69, 1, 0,
563  /* 402 */ 65502, 69, 1, 65467, 70, 1, 0,
564  /* 409 */ 65439, 68, 1, 65469, 70, 1, 0,
565  /* 416 */ 65293, 70, 1, 65466, 71, 1, 0,
566  /* 423 */ 65439, 69, 1, 65468, 71, 1, 0,
567  /* 430 */ 65503, 71, 1, 65465, 72, 1, 0,
568  /* 437 */ 65439, 70, 1, 65467, 72, 1, 0,
569  /* 444 */ 65294, 72, 1, 65464, 73, 1, 0,
570  /* 451 */ 65439, 71, 1, 65466, 73, 1, 0,
571  /* 458 */ 65504, 73, 1, 65463, 74, 1, 0,
572  /* 465 */ 65439, 72, 1, 65465, 74, 1, 0,
573  /* 472 */ 65295, 74, 1, 65462, 75, 1, 0,
574  /* 479 */ 65439, 73, 1, 65464, 75, 1, 0,
575  /* 486 */ 65505, 75, 1, 65461, 76, 1, 0,
576  /* 493 */ 65439, 74, 1, 65463, 76, 1, 0,
577  /* 500 */ 65296, 76, 1, 65460, 77, 1, 0,
578  /* 507 */ 65439, 75, 1, 65462, 77, 1, 0,
579  /* 514 */ 65506, 77, 1, 65459, 78, 1, 0,
580  /* 521 */ 65439, 76, 1, 65461, 78, 1, 0,
581  /* 528 */ 65297, 78, 1, 65458, 79, 1, 0,
582  /* 535 */ 65439, 77, 1, 65460, 79, 1, 0,
583  /* 542 */ 65507, 79, 1, 65457, 80, 1, 0,
584  /* 549 */ 65439, 78, 1, 65459, 80, 1, 0,
585  /* 556 */ 65045, 1, 0,
586  /* 559 */ 65260, 1, 0,
587  /* 562 */ 65299, 1, 0,
588  /* 565 */ 65300, 1, 0,
589  /* 568 */ 65301, 1, 0,
590  /* 571 */ 65302, 1, 0,
591  /* 574 */ 65303, 1, 0,
592  /* 577 */ 65304, 1, 0,
593  /* 580 */ 65305, 1, 0,
594  /* 583 */ 65453, 1, 65499, 133, 1, 65416, 1, 0,
595  /* 591 */ 138, 65488, 49, 65488, 12, 121, 65416, 1, 0,
596  /* 600 */ 65488, 13, 121, 65416, 1, 0,
597  /* 606 */ 65489, 13, 121, 65416, 1, 0,
598  /* 612 */ 65490, 13, 121, 65416, 1, 0,
599  /* 618 */ 65491, 13, 121, 65416, 1, 0,
600  /* 624 */ 65492, 13, 121, 65416, 1, 0,
601  /* 630 */ 65493, 13, 121, 65416, 1, 0,
602  /* 636 */ 65494, 13, 121, 65416, 1, 0,
603  /* 642 */ 65495, 13, 121, 65416, 1, 0,
604  /* 648 */ 65496, 13, 121, 65416, 1, 0,
605  /* 654 */ 65497, 13, 121, 65416, 1, 0,
606  /* 660 */ 65498, 13, 121, 65416, 1, 0,
607  /* 666 */ 65464, 1, 65488, 133, 65416, 121, 65416, 1, 0,
608  /* 675 */ 65463, 1, 65489, 133, 65416, 121, 65416, 1, 0,
609  /* 684 */ 65462, 1, 65490, 133, 65416, 121, 65416, 1, 0,
610  /* 693 */ 65461, 1, 65491, 133, 65416, 121, 65416, 1, 0,
611  /* 702 */ 65460, 1, 65492, 133, 65416, 121, 65416, 1, 0,
612  /* 711 */ 65459, 1, 65493, 133, 65416, 121, 65416, 1, 0,
613  /* 720 */ 65458, 1, 65494, 133, 65416, 121, 65416, 1, 0,
614  /* 729 */ 65457, 1, 65495, 133, 65416, 121, 65416, 1, 0,
615  /* 738 */ 65456, 1, 65496, 133, 65416, 121, 65416, 1, 0,
616  /* 747 */ 65455, 1, 65497, 133, 65416, 121, 65416, 1, 0,
617  /* 756 */ 65454, 1, 65498, 133, 65416, 121, 65416, 1, 0,
618  /* 765 */ 65488, 133, 65416, 1, 0,
619  /* 770 */ 65499, 134, 65416, 1, 0,
620  /* 775 */ 126, 65500, 37, 65500, 133, 65417, 1, 0,
621  /* 783 */ 65432, 1, 0,
622  /* 786 */ 65433, 1, 0,
623  /* 789 */ 65434, 1, 0,
624  /* 792 */ 65435, 1, 0,
625  /* 795 */ 65436, 1, 0,
626  /* 798 */ 65437, 1, 0,
627  /* 801 */ 65464, 1, 0,
628  /* 804 */ 65508, 1, 0,
629  /* 807 */ 65509, 1, 0,
630  /* 810 */ 65510, 1, 0,
631  /* 813 */ 65511, 1, 0,
632  /* 816 */ 65512, 1, 0,
633  /* 819 */ 65513, 1, 0,
634  /* 822 */ 65514, 1, 0,
635  /* 825 */ 65515, 1, 0,
636  /* 828 */ 65520, 1, 0,
637  /* 831 */ 65080, 1, 3, 1, 3, 1, 2, 0,
638  /* 839 */ 65136, 1, 3, 1, 2, 0,
639  /* 845 */ 65326, 1, 2, 0,
640  /* 849 */ 65080, 1, 3, 1, 2, 2, 0,
641  /* 856 */ 65136, 1, 2, 2, 0,
642  /* 861 */ 65080, 1, 2, 2, 2, 0,
643  /* 867 */ 65330, 2, 2, 2, 0,
644  /* 872 */ 65080, 1, 3, 2, 2, 0,
645  /* 878 */ 65358, 2, 2, 0,
646  /* 882 */ 65080, 1, 3, 1, 3, 2, 0,
647  /* 889 */ 65136, 1, 3, 2, 0,
648  /* 894 */ 65344, 76, 1, 65461, 78, 1, 65459, 80, 1, 12, 2, 0,
649  /* 906 */ 65344, 75, 1, 65462, 77, 1, 65460, 79, 1, 13, 2, 0,
650  /* 918 */ 65344, 74, 1, 65463, 76, 1, 65461, 78, 1, 14, 2, 0,
651  /* 930 */ 65344, 73, 1, 65464, 75, 1, 65462, 77, 1, 15, 2, 0,
652  /* 942 */ 65344, 72, 1, 65465, 74, 1, 65463, 76, 1, 16, 2, 0,
653  /* 954 */ 65344, 71, 1, 65466, 73, 1, 65464, 75, 1, 17, 2, 0,
654  /* 966 */ 65344, 70, 1, 65467, 72, 1, 65465, 74, 1, 18, 2, 0,
655  /* 978 */ 65344, 69, 1, 65468, 71, 1, 65466, 73, 1, 19, 2, 0,
656  /* 990 */ 65344, 68, 1, 65469, 70, 1, 65467, 72, 1, 20, 2, 0,
657  /* 1002 */ 65344, 67, 1, 65470, 69, 1, 65468, 71, 1, 21, 2, 0,
658  /* 1014 */ 65344, 66, 1, 65471, 68, 1, 65469, 70, 1, 22, 2, 0,
659  /* 1026 */ 65344, 65, 1, 65472, 67, 1, 65470, 69, 1, 23, 2, 0,
660  /* 1038 */ 65344, 2, 2, 93, 2, 0,
661  /* 1044 */ 65344, 80, 1, 65457, 2, 93, 2, 0,
662  /* 1052 */ 65344, 79, 1, 65458, 2, 93, 2, 0,
663  /* 1060 */ 65344, 78, 1, 65459, 80, 1, 65457, 93, 2, 0,
664  /* 1070 */ 65344, 77, 1, 65460, 79, 1, 65458, 93, 2, 0,
665  /* 1080 */ 65439, 2, 0,
666  /* 1083 */ 65453, 2, 0,
667  /* 1086 */ 65080, 1, 3, 1, 3, 1, 3, 0,
668  /* 1094 */ 65136, 1, 3, 1, 3, 0,
669  /* 1100 */ 65326, 1, 3, 0,
670  /* 1104 */ 5, 0,
671  /* 1106 */ 140, 65486, 13, 0,
672  /* 1110 */ 14, 0,
673  /* 1112 */ 126, 65501, 15, 0,
674  /* 1116 */ 10, 66, 0,
675  /* 1119 */ 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 0,
676  /* 1131 */ 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 0,
677  /* 1143 */ 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 0,
678  /* 1155 */ 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 0,
679  /* 1167 */ 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 0,
680  /* 1179 */ 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 0,
681  /* 1191 */ 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 0,
682  /* 1203 */ 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 0,
683  /* 1219 */ 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 0,
684  /* 1239 */ 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 0,
685  /* 1259 */ 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 0,
686  /* 1279 */ 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 0,
687  /* 1299 */ 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 0,
688  /* 1319 */ 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 0,
689  /* 1339 */ 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 0,
690  /* 1359 */ 91, 0,
691  /* 1361 */ 98, 0,
692  /* 1363 */ 99, 0,
693  /* 1365 */ 100, 0,
694  /* 1367 */ 101, 0,
695  /* 1369 */ 102, 0,
696  /* 1371 */ 103, 0,
697  /* 1373 */ 104, 0,
698  /* 1375 */ 65374, 1, 1, 20, 75, 135, 0,
699  /* 1382 */ 65374, 1, 1, 21, 74, 136, 0,
700  /* 1389 */ 65374, 1, 1, 22, 73, 137, 0,
701  /* 1396 */ 65374, 1, 1, 23, 72, 138, 0,
702  /* 1403 */ 65374, 1, 1, 24, 71, 139, 0,
703  /* 1410 */ 65374, 1, 1, 25, 70, 140, 0,
704  /* 1417 */ 65374, 1, 1, 26, 69, 141, 0,
705  /* 1424 */ 65374, 79, 1, 65457, 80, 1, 65456, 27, 68, 142, 0,
706  /* 1435 */ 65374, 77, 1, 65459, 78, 1, 65458, 79, 1, 65484, 67, 143, 0,
707  /* 1448 */ 65374, 75, 1, 65461, 76, 1, 65460, 77, 1, 65487, 66, 144, 0,
708  /* 1461 */ 65374, 73, 1, 65463, 74, 1, 65462, 75, 1, 65490, 65, 145, 0,
709  /* 1474 */ 65374, 71, 1, 65465, 72, 1, 65464, 73, 1, 65493, 64, 146, 0,
710  /* 1487 */ 65374, 69, 1, 65467, 70, 1, 65466, 71, 1, 65496, 63, 147, 0,
711  /* 1500 */ 65374, 67, 1, 65469, 68, 1, 65468, 69, 1, 65499, 62, 148, 0,
712  /* 1513 */ 65374, 65, 1, 65471, 66, 1, 65470, 67, 1, 65502, 61, 149, 0,
713  /* 1526 */ 157, 0,
714  /* 1528 */ 65289, 1, 1, 1, 229, 1, 65400, 65, 65472, 65, 65396, 0,
715  /* 1540 */ 65288, 1, 1, 1, 230, 1, 65399, 65, 65472, 65, 65397, 0,
716  /* 1552 */ 65287, 1, 1, 1, 231, 1, 65398, 65, 65472, 65, 65398, 0,
717  /* 1564 */ 65286, 1, 1, 1, 232, 1, 65397, 65, 65472, 65, 65399, 0,
718  /* 1576 */ 65285, 1, 1, 1, 233, 1, 65396, 65, 65472, 65, 65400, 0,
719  /* 1588 */ 65284, 1, 1, 1, 234, 1, 65395, 65, 65472, 65, 65401, 0,
720  /* 1600 */ 65521, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65419, 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 65492, 28, 65509, 28, 28, 65386, 65, 30, 65442, 65, 30, 40, 15, 65402, 0,
721  /* 1639 */ 65521, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65419, 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 65491, 28, 65509, 28, 29, 65385, 65, 30, 65442, 65, 30, 41, 15, 65402, 0,
722  /* 1678 */ 65521, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65419, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65490, 28, 65509, 28, 30, 65384, 65, 30, 65442, 65, 30, 42, 15, 65402, 0,
723  /* 1717 */ 65521, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65419, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65489, 28, 65509, 28, 31, 65383, 65, 30, 65442, 65, 30, 43, 15, 65402, 0,
724  /* 1756 */ 65521, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65419, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65488, 28, 65509, 28, 32, 65382, 65, 30, 65442, 65, 30, 44, 15, 65402, 0,
725  /* 1795 */ 65521, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65419, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65487, 28, 65509, 28, 33, 65381, 65, 30, 65442, 65, 30, 45, 15, 65402, 0,
726  /* 1838 */ 65521, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65419, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65486, 28, 65509, 28, 34, 65380, 65, 30, 65442, 65, 30, 46, 15, 65402, 0,
727  /* 1885 */ 65521, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65419, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65485, 28, 65509, 28, 35, 65379, 65, 30, 65442, 65, 30, 47, 15, 65402, 0,
728  /* 1936 */ 65521, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65419, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65484, 28, 65509, 28, 36, 65378, 65, 30, 65442, 65, 30, 48, 15, 65402, 0,
729  /* 1991 */ 65521, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65419, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65483, 28, 65509, 28, 37, 65377, 65, 30, 65442, 65, 30, 49, 15, 65402, 0,
730  /* 2046 */ 65521, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65419, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65482, 28, 65509, 28, 38, 65376, 65, 30, 65442, 65, 30, 50, 15, 65402, 0,
731  /* 2101 */ 65521, 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 65419, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65481, 28, 65509, 28, 39, 65375, 65, 30, 65442, 65, 30, 51, 15, 65402, 0,
732  /* 2156 */ 65521, 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 65419, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65480, 28, 65509, 28, 40, 65374, 65, 30, 65442, 65, 30, 52, 15, 65402, 0,
733  /* 2211 */ 65283, 80, 1, 65456, 1, 1, 235, 1, 65394, 65, 65472, 65, 65402, 0,
734  /* 2225 */ 65282, 78, 1, 65458, 79, 1, 65457, 80, 1, 65456, 236, 1, 65393, 65, 65472, 65, 65403, 0,
735  /* 2243 */ 65281, 76, 1, 65460, 77, 1, 65459, 78, 1, 65458, 79, 1, 157, 1, 65392, 65, 65472, 65, 65404, 0,
736  /* 2263 */ 65280, 74, 1, 65462, 75, 1, 65461, 76, 1, 65460, 77, 1, 160, 1, 65391, 65, 65472, 65, 65405, 0,
737  /* 2283 */ 65279, 72, 1, 65464, 73, 1, 65463, 74, 1, 65462, 75, 1, 163, 1, 65390, 65, 65472, 65, 65406, 0,
738  /* 2303 */ 65278, 70, 1, 65466, 71, 1, 65465, 72, 1, 65464, 73, 1, 166, 1, 65389, 65, 65472, 65, 65407, 0,
739  /* 2323 */ 65277, 68, 1, 65468, 69, 1, 65467, 70, 1, 65466, 71, 1, 169, 1, 65388, 65, 65472, 65, 65408, 0,
740  /* 2343 */ 65276, 66, 1, 65470, 67, 1, 65469, 68, 1, 65468, 69, 1, 172, 1, 65387, 65, 65472, 65, 65409, 0,
741  /* 2363 */ 22, 73, 2, 63, 65488, 120, 65465, 1, 65487, 75, 26, 65447, 65, 26, 30, 65416, 66, 26, 29, 65416, 0,
742  /* 2384 */ 21, 74, 2, 63, 65487, 120, 65466, 1, 65486, 76, 26, 65446, 66, 26, 29, 65416, 0,
743  /* 2401 */ 65, 65487, 77, 26, 65446, 66, 26, 29, 65416, 0,
744  /* 2411 */ 22, 73, 2, 134, 65465, 1, 65487, 50, 65487, 75, 26, 31, 65416, 65, 26, 30, 65416, 0,
745  /* 2429 */ 21, 74, 135, 65466, 1, 65486, 77, 26, 30, 65416, 0,
746  /* 2440 */ 65, 65487, 77, 26, 30, 65416, 0,
747  /* 2447 */ 139, 65487, 50, 65487, 12, 121, 65416, 0,
748  /* 2455 */ 65487, 13, 121, 65416, 0,
749  /* 2460 */ 65465, 1, 65487, 133, 65416, 121, 65416, 0,
750  /* 2468 */ 65466, 1, 65486, 133, 65416, 0,
751  /* 2474 */ 65487, 133, 65416, 0,
752  /* 2478 */ 65469, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0,
753  /* 2490 */ 65470, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0,
754  /* 2502 */ 65, 65500, 66, 28, 40, 65417, 0,
755  /* 2509 */ 65452, 1, 65500, 134, 65417, 0,
756  /* 2515 */ 65316, 74, 1, 65463, 76, 1, 65461, 78, 1, 65459, 80, 1, 10, 95, 65443, 95, 65443, 0,
757  /* 2533 */ 65316, 73, 1, 65464, 75, 1, 65462, 77, 1, 65460, 79, 1, 11, 95, 65443, 95, 65443, 0,
758  /* 2551 */ 65316, 72, 1, 65465, 74, 1, 65463, 76, 1, 65461, 78, 1, 12, 95, 65443, 95, 65443, 0,
759  /* 2569 */ 65316, 71, 1, 65466, 73, 1, 65464, 75, 1, 65462, 77, 1, 13, 95, 65443, 95, 65443, 0,
760  /* 2587 */ 65316, 70, 1, 65467, 72, 1, 65465, 74, 1, 65463, 76, 1, 14, 95, 65443, 95, 65443, 0,
761  /* 2605 */ 65316, 69, 1, 65468, 71, 1, 65466, 73, 1, 65464, 75, 1, 15, 95, 65443, 95, 65443, 0,
762  /* 2623 */ 65316, 68, 1, 65469, 70, 1, 65467, 72, 1, 65465, 74, 1, 16, 95, 65443, 95, 65443, 0,
763  /* 2641 */ 65316, 67, 1, 65470, 69, 1, 65468, 71, 1, 65466, 73, 1, 17, 95, 65443, 95, 65443, 0,
764  /* 2659 */ 65316, 66, 1, 65471, 68, 1, 65469, 70, 1, 65467, 72, 1, 18, 95, 65443, 95, 65443, 0,
765  /* 2677 */ 65316, 65, 1, 65472, 67, 1, 65470, 69, 1, 65468, 71, 1, 19, 95, 65443, 95, 65443, 0,
766  /* 2695 */ 65316, 2, 2, 2, 91, 95, 65443, 95, 65443, 0,
767  /* 2705 */ 65316, 80, 1, 65457, 2, 2, 91, 95, 65443, 95, 65443, 0,
768  /* 2717 */ 65316, 79, 1, 65458, 2, 2, 91, 95, 65443, 95, 65443, 0,
769  /* 2729 */ 65316, 78, 1, 65459, 80, 1, 65457, 2, 91, 95, 65443, 95, 65443, 0,
770  /* 2743 */ 65316, 77, 1, 65460, 79, 1, 65458, 2, 91, 95, 65443, 95, 65443, 0,
771  /* 2757 */ 65316, 76, 1, 65461, 78, 1, 65459, 80, 1, 65457, 91, 95, 65443, 95, 65443, 0,
772  /* 2773 */ 65316, 75, 1, 65462, 77, 1, 65460, 79, 1, 65458, 91, 95, 65443, 95, 65443, 0,
773  /* 2789 */ 20, 75, 65, 65486, 78, 26, 65445, 0,
774  /* 2797 */ 23, 72, 2, 63, 65489, 120, 65464, 1, 65488, 74, 26, 65448, 64, 26, 31, 65416, 65, 26, 30, 65416, 92, 65445, 0,
775  /* 2820 */ 65, 65488, 76, 26, 65447, 65, 26, 30, 65416, 92, 65445, 0,
776  /* 2832 */ 26, 65446, 92, 65445, 0,
777  /* 2837 */ 23, 72, 2, 135, 65464, 1, 65488, 49, 65488, 74, 26, 32, 65416, 64, 26, 31, 65416, 65, 26, 65446, 0,
778  /* 2858 */ 65, 65488, 76, 26, 31, 65416, 65, 26, 65446, 0,
779  /* 2868 */ 24, 71, 2, 63, 65490, 120, 65463, 1, 65489, 73, 26, 65449, 63, 26, 32, 65416, 64, 26, 31, 65416, 91, 65446, 0,
780  /* 2891 */ 65, 65489, 75, 26, 65448, 64, 26, 31, 65416, 91, 65446, 0,
781  /* 2903 */ 24, 71, 2, 136, 65463, 1, 65489, 48, 65489, 73, 26, 33, 65416, 63, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0,
782  /* 2926 */ 65, 65489, 75, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0,
783  /* 2938 */ 25, 70, 2, 63, 65491, 120, 65462, 1, 65490, 72, 26, 65450, 62, 26, 33, 65416, 63, 26, 32, 65416, 90, 65447, 0,
784  /* 2961 */ 65, 65490, 74, 26, 65449, 63, 26, 32, 65416, 90, 65447, 0,
785  /* 2973 */ 25, 70, 2, 137, 65462, 1, 65490, 47, 65490, 72, 26, 34, 65416, 62, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0,
786  /* 2996 */ 65, 65490, 74, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0,
787  /* 3008 */ 26, 69, 2, 63, 65492, 120, 65461, 1, 65491, 71, 26, 65451, 61, 26, 34, 65416, 62, 26, 33, 65416, 89, 65448, 0,
788  /* 3031 */ 65, 65491, 73, 26, 65450, 62, 26, 33, 65416, 89, 65448, 0,
789  /* 3043 */ 26, 69, 2, 138, 65461, 1, 65491, 46, 65491, 71, 26, 35, 65416, 61, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0,
790  /* 3066 */ 65, 65491, 73, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0,
791  /* 3078 */ 27, 68, 2, 63, 65493, 120, 65460, 1, 65492, 70, 26, 65452, 60, 26, 35, 65416, 61, 26, 34, 65416, 88, 65449, 0,
792  /* 3101 */ 65, 65492, 72, 26, 65451, 61, 26, 34, 65416, 88, 65449, 0,
793  /* 3113 */ 27, 68, 2, 139, 65460, 1, 65492, 45, 65492, 70, 26, 36, 65416, 60, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0,
794  /* 3136 */ 65, 65492, 72, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0,
795  /* 3148 */ 65455, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0,
796  /* 3172 */ 65456, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0,
797  /* 3196 */ 65, 65493, 71, 26, 65452, 60, 26, 35, 65416, 87, 65450, 0,
798  /* 3208 */ 28, 67, 2, 140, 65459, 1, 65493, 44, 65493, 69, 26, 37, 65416, 59, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0,
799  /* 3231 */ 65, 65493, 71, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0,
800  /* 3243 */ 65457, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0,
801  /* 3267 */ 65458, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0,
802  /* 3291 */ 65, 65494, 70, 26, 65453, 59, 26, 36, 65416, 86, 65451, 0,
803  /* 3303 */ 65456, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
804  /* 3327 */ 65457, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
805  /* 3351 */ 65, 65494, 70, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
806  /* 3363 */ 65459, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0,
807  /* 3387 */ 65460, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0,
808  /* 3411 */ 65, 65495, 69, 26, 65454, 58, 26, 37, 65416, 85, 65452, 0,
809  /* 3423 */ 65458, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
810  /* 3447 */ 65459, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
811  /* 3471 */ 65, 65495, 69, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
812  /* 3483 */ 65461, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0,
813  /* 3507 */ 65462, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0,
814  /* 3531 */ 65, 65496, 68, 26, 65455, 57, 26, 38, 65416, 84, 65453, 0,
815  /* 3543 */ 65460, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
816  /* 3567 */ 65461, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
817  /* 3591 */ 65, 65496, 68, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
818  /* 3603 */ 65463, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0,
819  /* 3627 */ 65464, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0,
820  /* 3651 */ 65, 65497, 67, 26, 65456, 56, 26, 39, 65416, 83, 65454, 0,
821  /* 3663 */ 65462, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
822  /* 3687 */ 65463, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
823  /* 3711 */ 65, 65497, 67, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
824  /* 3723 */ 65465, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0,
825  /* 3745 */ 65466, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0,
826  /* 3767 */ 65, 65498, 66, 26, 65457, 55, 26, 40, 65416, 82, 65455, 0,
827  /* 3779 */ 65464, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
828  /* 3803 */ 65465, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
829  /* 3827 */ 65, 65498, 66, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
830  /* 3839 */ 65298, 80, 1, 65456, 0,
831  /* 3844 */ 65467, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0,
832  /* 3863 */ 65468, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0,
833  /* 3882 */ 65, 65499, 65, 2, 26, 41, 65416, 81, 65456, 0,
834  /* 3892 */ 65466, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0,
835  /* 3914 */ 65467, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0,
836  /* 3936 */ 65, 65499, 65, 26, 42, 65416, 54, 26, 65457, 81, 65456, 0,
837  /* 3948 */ 65439, 80, 1, 65457, 0,
838  /* 3953 */ 28, 65457, 0,
839  /* 3956 */ 65468, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
840  /* 3974 */ 65469, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
841  /* 3992 */ 65, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
842  /* 4002 */ 26, 65458, 80, 65457, 0,
843  /* 4007 */ 65439, 79, 1, 65458, 0,
844  /* 4012 */ 65470, 36, 61, 65, 65501, 65, 28, 65458, 0,
845  /* 4021 */ 65471, 36, 61, 65, 65501, 65, 28, 65458, 0,
846  /* 4030 */ 65374, 1, 1, 229, 65402, 65461, 0,
847  /* 4037 */ 65374, 1, 1, 230, 65401, 65462, 0,
848  /* 4044 */ 65374, 1, 1, 231, 65400, 65463, 0,
849  /* 4051 */ 65374, 1, 1, 232, 65399, 65464, 0,
850  /* 4058 */ 65374, 1, 1, 233, 65398, 65465, 0,
851  /* 4065 */ 65374, 1, 1, 234, 65397, 65466, 0,
852  /* 4072 */ 65374, 1, 1, 235, 65396, 65467, 0,
853  /* 4079 */ 65374, 80, 1, 65456, 1, 236, 65395, 65468, 0,
854  /* 4088 */ 65374, 78, 1, 65458, 79, 1, 65457, 80, 1, 156, 65394, 65469, 0,
855  /* 4101 */ 65374, 76, 1, 65460, 77, 1, 65459, 78, 1, 159, 65393, 65470, 0,
856  /* 4114 */ 65445, 65470, 0,
857  /* 4117 */ 65374, 74, 1, 65462, 75, 1, 65461, 76, 1, 162, 65392, 65471, 0,
858  /* 4130 */ 65374, 72, 1, 65464, 73, 1, 65463, 74, 1, 165, 65391, 65472, 0,
859  /* 4143 */ 65374, 70, 1, 65466, 71, 1, 65465, 72, 1, 168, 65390, 65473, 0,
860  /* 4156 */ 65374, 68, 1, 65468, 69, 1, 65467, 70, 1, 171, 65389, 65474, 0,
861  /* 4169 */ 65374, 66, 1, 65470, 67, 1, 65469, 68, 1, 174, 65388, 65475, 0,
862  /* 4182 */ 65534, 0,
863  /* 4184 */ 65535, 0,
864};
865
866extern const LaneBitmask ARMLaneMaskLists[] = {
867  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
868  /* 2 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask::getAll(),
869  /* 5 */ LaneBitmask(0x00000001), LaneBitmask(0x00000002), LaneBitmask::getAll(),
870  /* 8 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask::getAll(),
871  /* 11 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(),
872  /* 16 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask::getAll(),
873  /* 20 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask::getAll(),
874  /* 23 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask::getAll(),
875  /* 28 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask::getAll(),
876  /* 35 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
877  /* 39 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
878  /* 42 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
879  /* 48 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
880  /* 53 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
881  /* 57 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask::getAll(),
882  /* 66 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000300), LaneBitmask::getAll(),
883  /* 74 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(),
884  /* 81 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(),
885  /* 87 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(),
886  /* 92 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask::getAll(),
887  /* 99 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000C00), LaneBitmask::getAll(),
888  /* 105 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask::getAll(),
889  /* 110 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask::getAll(),
890  /* 114 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00004000), LaneBitmask(0x00008000), LaneBitmask::getAll(),
891  /* 123 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
892  /* 131 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
893  /* 138 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
894  /* 144 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
895  /* 149 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00001000), LaneBitmask(0x00002000), LaneBitmask(0x00004000), LaneBitmask(0x00008000), LaneBitmask(0x00010000), LaneBitmask(0x00020000), LaneBitmask::getAll(),
896  /* 166 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00001000), LaneBitmask(0x00002000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
897  /* 181 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
898  /* 194 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
899  /* 205 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
900};
901
902extern const uint16_t ARMSubRegIdxLists[] = {
903  /* 0 */ 1, 2, 0,
904  /* 3 */ 1, 17, 18, 2, 0,
905  /* 8 */ 1, 3, 0,
906  /* 11 */ 1, 17, 18, 3, 0,
907  /* 16 */ 9, 10, 0,
908  /* 19 */ 17, 18, 0,
909  /* 22 */ 1, 17, 18, 2, 19, 20, 0,
910  /* 29 */ 1, 17, 18, 3, 21, 22, 0,
911  /* 36 */ 1, 2, 3, 13, 33, 37, 0,
912  /* 43 */ 1, 17, 18, 2, 3, 13, 33, 37, 0,
913  /* 52 */ 1, 17, 18, 2, 19, 20, 3, 13, 33, 37, 0,
914  /* 63 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 13, 33, 37, 0,
915  /* 76 */ 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 0,
916  /* 88 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 0,
917  /* 104 */ 1, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0,
918  /* 116 */ 1, 17, 18, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0,
919  /* 130 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 13, 14, 33, 34, 35, 36, 37, 0,
920  /* 148 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 23, 24, 13, 14, 33, 34, 35, 36, 37, 0,
921  /* 168 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 0,
922  /* 188 */ 1, 3, 5, 33, 43, 0,
923  /* 194 */ 1, 17, 18, 3, 5, 33, 43, 0,
924  /* 202 */ 1, 17, 18, 3, 21, 22, 5, 33, 43, 0,
925  /* 212 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 33, 43, 0,
926  /* 224 */ 1, 3, 5, 7, 33, 38, 43, 45, 51, 0,
927  /* 234 */ 1, 17, 18, 3, 5, 7, 33, 38, 43, 45, 51, 0,
928  /* 246 */ 1, 17, 18, 3, 21, 22, 5, 7, 33, 38, 43, 45, 51, 0,
929  /* 260 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 33, 38, 43, 45, 51, 0,
930  /* 276 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 29, 30, 33, 38, 43, 45, 51, 0,
931  /* 294 */ 11, 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
932  /* 333 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
933  /* 376 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
934  /* 423 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
935  /* 474 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 29, 30, 8, 31, 32, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
936};
937
938extern const MCRegisterInfo::SubRegCoveredBits ARMSubRegIdxRanges[] = {
939  { 65535, 65535 },
940  { 0, 64 },	// dsub_0
941  { 64, 64 },	// dsub_1
942  { 128, 64 },	// dsub_2
943  { 192, 64 },	// dsub_3
944  { 256, 64 },	// dsub_4
945  { 320, 64 },	// dsub_5
946  { 384, 64 },	// dsub_6
947  { 448, 64 },	// dsub_7
948  { 0, 32 },	// gsub_0
949  { 32, 32 },	// gsub_1
950  { 0, 256 },	// qqsub_0
951  { 256, 256 },	// qqsub_1
952  { 0, 128 },	// qsub_0
953  { 128, 128 },	// qsub_1
954  { 256, 128 },	// qsub_2
955  { 384, 128 },	// qsub_3
956  { 0, 32 },	// ssub_0
957  { 32, 32 },	// ssub_1
958  { 64, 32 },	// ssub_2
959  { 96, 32 },	// ssub_3
960  { 128, 32 },	// ssub_4
961  { 160, 32 },	// ssub_5
962  { 192, 32 },	// ssub_6
963  { 224, 32 },	// ssub_7
964  { 256, 32 },	// ssub_8
965  { 288, 32 },	// ssub_9
966  { 320, 32 },	// ssub_10
967  { 352, 32 },	// ssub_11
968  { 384, 32 },	// ssub_12
969  { 416, 32 },	// ssub_13
970  { 448, 32 },	// dsub_7_then_ssub_0
971  { 480, 32 },	// dsub_7_then_ssub_1
972  { 65535, 128 },	// ssub_0_ssub_1_ssub_4_ssub_5
973  { 0, 192 },	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
974  { 65535, 128 },	// ssub_2_ssub_3_ssub_6_ssub_7
975  { 64, 192 },	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
976  { 64, 128 },	// ssub_2_ssub_3_ssub_4_ssub_5
977  { 65535, 192 },	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
978  { 65535, 256 },	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
979  { 65535, 192 },	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
980  { 65535, 256 },	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
981  { 64, 256 },	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
982  { 65535, 128 },	// ssub_4_ssub_5_ssub_8_ssub_9
983  { 128, 192 },	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
984  { 65535, 192 },	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
985  { 65535, 128 },	// ssub_6_ssub_7_dsub_5
986  { 192, 192 },	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
987  { 65535, 192 },	// ssub_6_ssub_7_dsub_5_dsub_7
988  { 192, 128 },	// ssub_6_ssub_7_ssub_8_ssub_9
989  { 192, 256 },	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
990  { 65535, 128 },	// ssub_8_ssub_9_ssub_12_ssub_13
991  { 256, 192 },	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
992  { 65535, 128 },	// dsub_5_dsub_7
993  { 320, 192 },	// dsub_5_ssub_12_ssub_13_dsub_7
994  { 320, 128 },	// dsub_5_ssub_12_ssub_13
995  { 128, 256 },	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
996};
997
998extern const char ARMRegStrings[] = {
999  /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0,
1000  /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
1001  /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
1002  /* 39 */ 'R', '1', '0', 0,
1003  /* 43 */ 'S', '1', '0', 0,
1004  /* 47 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0,
1005  /* 63 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
1006  /* 79 */ 'S', '2', '0', 0,
1007  /* 83 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0,
1008  /* 99 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
1009  /* 115 */ 'S', '3', '0', 0,
1010  /* 119 */ 'D', '0', 0,
1011  /* 122 */ 'Q', '0', 0,
1012  /* 125 */ 'M', 'V', 'F', 'R', '0', 0,
1013  /* 131 */ 'S', '0', 0,
1014  /* 134 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
1015  /* 145 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0,
1016  /* 158 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
1017  /* 172 */ 'R', '1', '0', '_', 'R', '1', '1', 0,
1018  /* 180 */ 'S', '1', '1', 0,
1019  /* 184 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
1020  /* 196 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0,
1021  /* 212 */ 'S', '2', '1', 0,
1022  /* 216 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
1023  /* 228 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0,
1024  /* 244 */ 'S', '3', '1', 0,
1025  /* 248 */ 'D', '1', 0,
1026  /* 251 */ 'Q', '0', '_', 'Q', '1', 0,
1027  /* 257 */ 'M', 'V', 'F', 'R', '1', 0,
1028  /* 263 */ 'R', '0', '_', 'R', '1', 0,
1029  /* 269 */ 'S', '1', 0,
1030  /* 272 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0,
1031  /* 286 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
1032  /* 301 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
1033  /* 316 */ 'R', '1', '2', 0,
1034  /* 320 */ 'S', '1', '2', 0,
1035  /* 324 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0,
1036  /* 340 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
1037  /* 356 */ 'S', '2', '2', 0,
1038  /* 360 */ 'D', '0', '_', 'D', '2', 0,
1039  /* 366 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
1040  /* 375 */ 'Q', '1', '_', 'Q', '2', 0,
1041  /* 381 */ 'M', 'V', 'F', 'R', '2', 0,
1042  /* 387 */ 'S', '2', 0,
1043  /* 390 */ 'F', 'P', 'I', 'N', 'S', 'T', '2', 0,
1044  /* 398 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0,
1045  /* 412 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
1046  /* 424 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
1047  /* 440 */ 'S', '1', '3', 0,
1048  /* 444 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0,
1049  /* 460 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
1050  /* 472 */ 'S', '2', '3', 0,
1051  /* 476 */ 'D', '1', '_', 'D', '3', 0,
1052  /* 482 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
1053  /* 491 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
1054  /* 503 */ 'R', '2', '_', 'R', '3', 0,
1055  /* 509 */ 'S', '3', 0,
1056  /* 512 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0,
1057  /* 527 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
1058  /* 543 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
1059  /* 559 */ 'S', '1', '4', 0,
1060  /* 563 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0,
1061  /* 579 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
1062  /* 595 */ 'S', '2', '4', 0,
1063  /* 599 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0,
1064  /* 608 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
1065  /* 620 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
1066  /* 632 */ 'R', '4', 0,
1067  /* 635 */ 'S', '4', 0,
1068  /* 638 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0,
1069  /* 653 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
1070  /* 665 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
1071  /* 681 */ 'S', '1', '5', 0,
1072  /* 685 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0,
1073  /* 701 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
1074  /* 713 */ 'S', '2', '5', 0,
1075  /* 717 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0,
1076  /* 726 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
1077  /* 735 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
1078  /* 747 */ 'R', '4', '_', 'R', '5', 0,
1079  /* 753 */ 'S', '5', 0,
1080  /* 756 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0,
1081  /* 772 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
1082  /* 788 */ 'S', '1', '6', 0,
1083  /* 792 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0,
1084  /* 808 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
1085  /* 824 */ 'S', '2', '6', 0,
1086  /* 828 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0,
1087  /* 840 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
1088  /* 852 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
1089  /* 864 */ 'R', '6', 0,
1090  /* 867 */ 'S', '6', 0,
1091  /* 870 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0,
1092  /* 886 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
1093  /* 898 */ 'S', '1', '7', 0,
1094  /* 902 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0,
1095  /* 918 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
1096  /* 930 */ 'S', '2', '7', 0,
1097  /* 934 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0,
1098  /* 946 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
1099  /* 955 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
1100  /* 967 */ 'R', '6', '_', 'R', '7', 0,
1101  /* 973 */ 'S', '7', 0,
1102  /* 976 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0,
1103  /* 992 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
1104  /* 1008 */ 'S', '1', '8', 0,
1105  /* 1012 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0,
1106  /* 1028 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
1107  /* 1044 */ 'S', '2', '8', 0,
1108  /* 1048 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0,
1109  /* 1060 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
1110  /* 1072 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
1111  /* 1084 */ 'R', '8', 0,
1112  /* 1087 */ 'S', '8', 0,
1113  /* 1090 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0,
1114  /* 1106 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
1115  /* 1118 */ 'S', '1', '9', 0,
1116  /* 1122 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0,
1117  /* 1138 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
1118  /* 1150 */ 'S', '2', '9', 0,
1119  /* 1154 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0,
1120  /* 1166 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
1121  /* 1175 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
1122  /* 1187 */ 'R', '8', '_', 'R', '9', 0,
1123  /* 1193 */ 'S', '9', 0,
1124  /* 1196 */ 'P', 'C', 0,
1125  /* 1199 */ 'F', 'P', 'E', 'X', 'C', 0,
1126  /* 1205 */ 'F', 'P', 'S', 'I', 'D', 0,
1127  /* 1211 */ 'I', 'T', 'S', 'T', 'A', 'T', 'E', 0,
1128  /* 1219 */ 'R', '1', '2', '_', 'S', 'P', 0,
1129  /* 1226 */ 'F', 'P', 'S', 'C', 'R', 0,
1130  /* 1232 */ 'L', 'R', 0,
1131  /* 1235 */ 'A', 'P', 'S', 'R', 0,
1132  /* 1240 */ 'C', 'P', 'S', 'R', 0,
1133  /* 1245 */ 'S', 'P', 'S', 'R', 0,
1134  /* 1250 */ 'F', 'P', 'I', 'N', 'S', 'T', 0,
1135  /* 1257 */ 'F', 'P', 'S', 'C', 'R', '_', 'N', 'Z', 'C', 'V', 0,
1136  /* 1268 */ 'A', 'P', 'S', 'R', '_', 'N', 'Z', 'C', 'V', 0,
1137};
1138
1139extern const MCRegisterDesc ARMRegDesc[] = { // Descriptors
1140  { 12, 0, 0, 0, 0, 0 },
1141  { 1235, 16, 16, 2, 66945, 0 },
1142  { 1268, 16, 16, 2, 66945, 0 },
1143  { 1240, 16, 16, 2, 66945, 0 },
1144  { 1199, 16, 16, 2, 66945, 0 },
1145  { 1250, 16, 16, 2, 66945, 0 },
1146  { 1226, 16, 16, 2, 17664, 0 },
1147  { 1257, 16, 16, 2, 17664, 0 },
1148  { 1205, 16, 16, 2, 66913, 0 },
1149  { 1211, 16, 16, 2, 66913, 0 },
1150  { 1232, 16, 16, 2, 66913, 0 },
1151  { 1196, 16, 16, 2, 66913, 0 },
1152  { 1223, 16, 1526, 2, 66913, 0 },
1153  { 1245, 16, 16, 2, 66913, 0 },
1154  { 119, 350, 4013, 19, 13250, 8 },
1155  { 248, 357, 2479, 19, 13250, 8 },
1156  { 363, 364, 3957, 19, 13250, 8 },
1157  { 479, 378, 3845, 19, 13250, 8 },
1158  { 605, 392, 3893, 19, 13250, 8 },
1159  { 723, 406, 3724, 19, 13250, 8 },
1160  { 837, 420, 3780, 19, 13250, 8 },
1161  { 943, 434, 3604, 19, 13250, 8 },
1162  { 1057, 448, 3664, 19, 13250, 8 },
1163  { 1163, 462, 3484, 19, 13250, 8 },
1164  { 9, 476, 3544, 19, 13250, 8 },
1165  { 141, 490, 3364, 19, 13250, 8 },
1166  { 282, 504, 3424, 19, 13250, 8 },
1167  { 408, 518, 3244, 19, 13250, 8 },
1168  { 523, 532, 3304, 19, 13250, 8 },
1169  { 649, 546, 3149, 19, 13250, 8 },
1170  { 768, 16, 3208, 2, 17761, 0 },
1171  { 882, 16, 3078, 2, 17761, 0 },
1172  { 988, 16, 3113, 2, 17761, 0 },
1173  { 1102, 16, 3008, 2, 17761, 0 },
1174  { 59, 16, 3043, 2, 17761, 0 },
1175  { 192, 16, 2938, 2, 17761, 0 },
1176  { 336, 16, 2973, 2, 17761, 0 },
1177  { 456, 16, 2868, 2, 17761, 0 },
1178  { 575, 16, 2903, 2, 17761, 0 },
1179  { 697, 16, 2797, 2, 17761, 0 },
1180  { 804, 16, 2837, 2, 17761, 0 },
1181  { 914, 16, 2363, 2, 17761, 0 },
1182  { 1024, 16, 2411, 2, 17761, 0 },
1183  { 1134, 16, 2384, 2, 17761, 0 },
1184  { 95, 16, 2429, 2, 17761, 0 },
1185  { 224, 16, 2789, 2, 17761, 0 },
1186  { 390, 16, 16, 2, 17761, 0 },
1187  { 125, 16, 16, 2, 17761, 0 },
1188  { 257, 16, 16, 2, 17761, 0 },
1189  { 381, 16, 16, 2, 17761, 0 },
1190  { 122, 353, 1112, 22, 2196, 11 },
1191  { 254, 374, 775, 22, 2196, 11 },
1192  { 378, 402, 314, 22, 2196, 11 },
1193  { 500, 430, 244, 22, 2196, 11 },
1194  { 629, 458, 234, 22, 2196, 11 },
1195  { 744, 486, 224, 22, 2196, 11 },
1196  { 861, 514, 214, 22, 2196, 11 },
1197  { 964, 542, 204, 22, 2196, 11 },
1198  { 1081, 804, 194, 0, 12818, 20 },
1199  { 1184, 807, 184, 0, 12818, 20 },
1200  { 35, 810, 174, 0, 12818, 20 },
1201  { 168, 813, 164, 0, 12818, 20 },
1202  { 312, 816, 154, 0, 12818, 20 },
1203  { 436, 819, 591, 0, 12818, 20 },
1204  { 555, 822, 2447, 0, 12818, 20 },
1205  { 677, 825, 1106, 0, 12818, 20 },
1206  { 128, 16, 1373, 2, 66913, 0 },
1207  { 260, 16, 1371, 2, 66913, 0 },
1208  { 384, 16, 1371, 2, 66913, 0 },
1209  { 506, 16, 1369, 2, 66913, 0 },
1210  { 632, 16, 1369, 2, 66913, 0 },
1211  { 750, 16, 1367, 2, 66913, 0 },
1212  { 864, 16, 1367, 2, 66913, 0 },
1213  { 970, 16, 1365, 2, 66913, 0 },
1214  { 1084, 16, 1365, 2, 66913, 0 },
1215  { 1190, 16, 1363, 2, 66913, 0 },
1216  { 39, 16, 1363, 2, 66913, 0 },
1217  { 176, 16, 1361, 2, 66913, 0 },
1218  { 316, 16, 1359, 2, 66913, 0 },
1219  { 131, 16, 4021, 2, 65585, 0 },
1220  { 269, 16, 4012, 2, 65585, 0 },
1221  { 387, 16, 2490, 2, 65585, 0 },
1222  { 509, 16, 2478, 2, 65585, 0 },
1223  { 635, 16, 3974, 2, 65585, 0 },
1224  { 753, 16, 3956, 2, 65585, 0 },
1225  { 867, 16, 3863, 2, 65585, 0 },
1226  { 973, 16, 3844, 2, 65585, 0 },
1227  { 1087, 16, 3914, 2, 65585, 0 },
1228  { 1193, 16, 3892, 2, 65585, 0 },
1229  { 43, 16, 3745, 2, 65585, 0 },
1230  { 180, 16, 3723, 2, 65585, 0 },
1231  { 320, 16, 3803, 2, 65585, 0 },
1232  { 440, 16, 3779, 2, 65585, 0 },
1233  { 559, 16, 3627, 2, 65585, 0 },
1234  { 681, 16, 3603, 2, 65585, 0 },
1235  { 788, 16, 3687, 2, 65585, 0 },
1236  { 898, 16, 3663, 2, 65585, 0 },
1237  { 1008, 16, 3507, 2, 65585, 0 },
1238  { 1118, 16, 3483, 2, 65585, 0 },
1239  { 79, 16, 3567, 2, 65585, 0 },
1240  { 212, 16, 3543, 2, 65585, 0 },
1241  { 356, 16, 3387, 2, 65585, 0 },
1242  { 472, 16, 3363, 2, 65585, 0 },
1243  { 595, 16, 3447, 2, 65585, 0 },
1244  { 713, 16, 3423, 2, 65585, 0 },
1245  { 824, 16, 3267, 2, 65585, 0 },
1246  { 930, 16, 3243, 2, 65585, 0 },
1247  { 1044, 16, 3327, 2, 65585, 0 },
1248  { 1150, 16, 3303, 2, 65585, 0 },
1249  { 115, 16, 3172, 2, 65585, 0 },
1250  { 244, 16, 3148, 2, 65585, 0 },
1251  { 360, 367, 4015, 29, 5426, 23 },
1252  { 476, 381, 2502, 29, 5426, 23 },
1253  { 602, 395, 3992, 29, 5426, 23 },
1254  { 720, 409, 3882, 29, 5426, 23 },
1255  { 834, 423, 3936, 29, 5426, 23 },
1256  { 940, 437, 3767, 29, 5426, 23 },
1257  { 1054, 451, 3827, 29, 5426, 23 },
1258  { 1160, 465, 3651, 29, 5426, 23 },
1259  { 6, 479, 3711, 29, 5426, 23 },
1260  { 151, 493, 3531, 29, 5426, 23 },
1261  { 278, 507, 3591, 29, 5426, 23 },
1262  { 404, 521, 3411, 29, 5426, 23 },
1263  { 519, 535, 3471, 29, 5426, 23 },
1264  { 645, 549, 3291, 29, 5426, 23 },
1265  { 764, 4007, 3351, 11, 17602, 35 },
1266  { 878, 3948, 3196, 11, 13522, 35 },
1267  { 984, 1080, 3231, 8, 17329, 39 },
1268  { 1098, 1080, 3101, 8, 17329, 39 },
1269  { 55, 1080, 3136, 8, 17329, 39 },
1270  { 204, 1080, 3031, 8, 17329, 39 },
1271  { 332, 1080, 3066, 8, 17329, 39 },
1272  { 452, 1080, 2961, 8, 17329, 39 },
1273  { 571, 1080, 2996, 8, 17329, 39 },
1274  { 693, 1080, 2891, 8, 17329, 39 },
1275  { 800, 1080, 2926, 8, 17329, 39 },
1276  { 910, 1080, 2820, 8, 17329, 39 },
1277  { 1020, 1080, 2858, 8, 17329, 39 },
1278  { 1130, 1080, 2401, 8, 17329, 39 },
1279  { 91, 1080, 2440, 8, 17329, 39 },
1280  { 236, 1080, 2791, 8, 17329, 39 },
1281  { 251, 1339, 1114, 168, 1044, 57 },
1282  { 375, 1319, 347, 168, 1044, 57 },
1283  { 497, 1299, 142, 168, 1044, 57 },
1284  { 626, 1279, 142, 168, 1044, 57 },
1285  { 741, 1259, 142, 168, 1044, 57 },
1286  { 858, 1239, 142, 168, 1044, 57 },
1287  { 961, 1219, 142, 168, 1044, 57 },
1288  { 1078, 1203, 142, 88, 1456, 74 },
1289  { 1181, 1191, 142, 76, 2114, 87 },
1290  { 32, 1179, 142, 76, 2114, 87 },
1291  { 164, 1167, 142, 76, 2114, 87 },
1292  { 308, 1155, 142, 76, 2114, 87 },
1293  { 432, 1143, 142, 76, 2114, 87 },
1294  { 551, 1131, 344, 76, 2114, 87 },
1295  { 673, 1119, 1108, 76, 2114, 87 },
1296  { 491, 2156, 16, 474, 4, 149 },
1297  { 620, 2101, 16, 474, 4, 149 },
1298  { 735, 2046, 16, 474, 4, 149 },
1299  { 852, 1991, 16, 474, 4, 149 },
1300  { 955, 1936, 16, 474, 4, 149 },
1301  { 1072, 1885, 16, 423, 272, 166 },
1302  { 1175, 1838, 16, 376, 512, 181 },
1303  { 26, 1795, 16, 333, 720, 194 },
1304  { 158, 1756, 16, 294, 1186, 205 },
1305  { 301, 1717, 16, 294, 1186, 205 },
1306  { 424, 1678, 16, 294, 1186, 205 },
1307  { 543, 1639, 16, 294, 1186, 205 },
1308  { 665, 1600, 16, 294, 1186, 205 },
1309  { 1219, 4114, 16, 16, 17856, 2 },
1310  { 263, 783, 16, 16, 8946, 5 },
1311  { 503, 786, 16, 16, 8946, 5 },
1312  { 747, 789, 16, 16, 8946, 5 },
1313  { 967, 792, 16, 16, 8946, 5 },
1314  { 1187, 795, 16, 16, 8946, 5 },
1315  { 172, 798, 16, 16, 8946, 5 },
1316  { 366, 1513, 1113, 63, 1570, 28 },
1317  { 482, 4169, 2511, 63, 1570, 28 },
1318  { 611, 1500, 778, 63, 1570, 28 },
1319  { 726, 4156, 770, 63, 1570, 28 },
1320  { 843, 1487, 317, 63, 1570, 28 },
1321  { 946, 4143, 660, 63, 1570, 28 },
1322  { 1063, 1474, 308, 63, 1570, 28 },
1323  { 1166, 4130, 654, 63, 1570, 28 },
1324  { 16, 1461, 302, 63, 1570, 28 },
1325  { 134, 4117, 648, 63, 1570, 28 },
1326  { 289, 1448, 296, 63, 1570, 28 },
1327  { 412, 4101, 642, 63, 1570, 28 },
1328  { 531, 1435, 290, 63, 1570, 28 },
1329  { 653, 4088, 636, 63, 1570, 28 },
1330  { 776, 1424, 284, 52, 1680, 42 },
1331  { 886, 4079, 630, 43, 1872, 48 },
1332  { 996, 1417, 278, 36, 2401, 53 },
1333  { 1106, 4072, 624, 36, 2401, 53 },
1334  { 67, 1410, 272, 36, 2401, 53 },
1335  { 184, 4065, 618, 36, 2401, 53 },
1336  { 344, 1403, 266, 36, 2401, 53 },
1337  { 460, 4058, 612, 36, 2401, 53 },
1338  { 583, 1396, 260, 36, 2401, 53 },
1339  { 701, 4051, 606, 36, 2401, 53 },
1340  { 812, 1389, 254, 36, 2401, 53 },
1341  { 918, 4044, 600, 36, 2401, 53 },
1342  { 1032, 1382, 765, 36, 2401, 53 },
1343  { 1138, 4037, 2455, 36, 2401, 53 },
1344  { 103, 1375, 2474, 36, 2401, 53 },
1345  { 216, 4030, 1107, 36, 2401, 53 },
1346  { 599, 1026, 4018, 212, 5314, 92 },
1347  { 717, 1014, 3953, 212, 5314, 92 },
1348  { 831, 1002, 4002, 212, 5314, 92 },
1349  { 937, 990, 3909, 212, 5314, 92 },
1350  { 1051, 978, 3909, 212, 5314, 92 },
1351  { 1157, 966, 3798, 212, 5314, 92 },
1352  { 3, 954, 3798, 212, 5314, 92 },
1353  { 148, 942, 3682, 212, 5314, 92 },
1354  { 275, 930, 3682, 212, 5314, 92 },
1355  { 401, 918, 3562, 212, 5314, 92 },
1356  { 515, 906, 3562, 212, 5314, 92 },
1357  { 641, 894, 3442, 212, 5314, 92 },
1358  { 760, 1070, 3442, 202, 17506, 99 },
1359  { 874, 1060, 3322, 202, 13426, 99 },
1360  { 980, 1052, 3322, 194, 14226, 105 },
1361  { 1094, 1044, 3226, 194, 13698, 105 },
1362  { 51, 1038, 3226, 188, 14049, 110 },
1363  { 200, 1038, 3131, 188, 14049, 110 },
1364  { 328, 1038, 3131, 188, 14049, 110 },
1365  { 448, 1038, 3061, 188, 14049, 110 },
1366  { 567, 1038, 3061, 188, 14049, 110 },
1367  { 689, 1038, 2991, 188, 14049, 110 },
1368  { 796, 1038, 2991, 188, 14049, 110 },
1369  { 906, 1038, 2921, 188, 14049, 110 },
1370  { 1016, 1038, 2921, 188, 14049, 110 },
1371  { 1126, 1038, 2832, 188, 14049, 110 },
1372  { 87, 1038, 2855, 188, 14049, 110 },
1373  { 232, 1038, 2794, 188, 14049, 110 },
1374  { 828, 2677, 4010, 276, 5170, 114 },
1375  { 934, 2659, 3951, 276, 5170, 114 },
1376  { 1048, 2641, 3951, 276, 5170, 114 },
1377  { 1154, 2623, 3842, 276, 5170, 114 },
1378  { 0, 2605, 3842, 276, 5170, 114 },
1379  { 145, 2587, 3743, 276, 5170, 114 },
1380  { 272, 2569, 3743, 276, 5170, 114 },
1381  { 398, 2551, 3625, 276, 5170, 114 },
1382  { 512, 2533, 3625, 276, 5170, 114 },
1383  { 638, 2515, 3505, 276, 5170, 114 },
1384  { 756, 2773, 3505, 260, 17378, 123 },
1385  { 870, 2757, 3385, 260, 13298, 123 },
1386  { 976, 2743, 3385, 246, 14114, 131 },
1387  { 1090, 2729, 3265, 246, 13586, 131 },
1388  { 47, 2717, 3265, 234, 13954, 138 },
1389  { 196, 2705, 3170, 234, 13778, 138 },
1390  { 324, 2695, 3170, 224, 13873, 144 },
1391  { 444, 2695, 3099, 224, 13873, 144 },
1392  { 563, 2695, 3099, 224, 13873, 144 },
1393  { 685, 2695, 3029, 224, 13873, 144 },
1394  { 792, 2695, 3029, 224, 13873, 144 },
1395  { 902, 2695, 2959, 224, 13873, 144 },
1396  { 1012, 2695, 2959, 224, 13873, 144 },
1397  { 1122, 2695, 2856, 224, 13873, 144 },
1398  { 83, 2695, 2856, 224, 13873, 144 },
1399  { 228, 2695, 2795, 224, 13873, 144 },
1400  { 369, 360, 2509, 22, 1956, 11 },
1401  { 614, 388, 583, 22, 1956, 11 },
1402  { 846, 416, 756, 22, 1956, 11 },
1403  { 1066, 444, 747, 22, 1956, 11 },
1404  { 19, 472, 738, 22, 1956, 11 },
1405  { 293, 500, 729, 22, 1956, 11 },
1406  { 535, 528, 720, 22, 1956, 11 },
1407  { 780, 3839, 711, 3, 2336, 16 },
1408  { 1000, 562, 702, 0, 8898, 20 },
1409  { 71, 565, 693, 0, 8898, 20 },
1410  { 348, 568, 684, 0, 8898, 20 },
1411  { 587, 571, 675, 0, 8898, 20 },
1412  { 816, 574, 666, 0, 8898, 20 },
1413  { 1036, 577, 2460, 0, 8898, 20 },
1414  { 107, 580, 2468, 0, 8898, 20 },
1415  { 608, 2343, 2488, 148, 900, 57 },
1416  { 840, 2323, 588, 148, 900, 57 },
1417  { 1060, 2303, 588, 148, 900, 57 },
1418  { 13, 2283, 588, 148, 900, 57 },
1419  { 286, 2263, 588, 148, 900, 57 },
1420  { 527, 2243, 588, 148, 900, 57 },
1421  { 772, 2225, 588, 130, 1328, 66 },
1422  { 992, 2211, 588, 116, 1776, 81 },
1423  { 63, 1588, 588, 104, 2034, 87 },
1424  { 340, 1576, 588, 104, 2034, 87 },
1425  { 579, 1564, 588, 104, 2034, 87 },
1426  { 808, 1552, 588, 104, 2034, 87 },
1427  { 1028, 1540, 588, 104, 2034, 87 },
1428  { 99, 1528, 2382, 104, 2034, 87 },
1429};
1430
1431extern const MCPhysReg ARMRegUnitRoots[][2] = {
1432  { ARM::APSR },
1433  { ARM::APSR_NZCV },
1434  { ARM::CPSR },
1435  { ARM::FPEXC },
1436  { ARM::FPINST },
1437  { ARM::FPSCR, ARM::FPSCR_NZCV },
1438  { ARM::FPSID },
1439  { ARM::ITSTATE },
1440  { ARM::LR },
1441  { ARM::PC },
1442  { ARM::SP },
1443  { ARM::SPSR },
1444  { ARM::S0 },
1445  { ARM::S1 },
1446  { ARM::S2 },
1447  { ARM::S3 },
1448  { ARM::S4 },
1449  { ARM::S5 },
1450  { ARM::S6 },
1451  { ARM::S7 },
1452  { ARM::S8 },
1453  { ARM::S9 },
1454  { ARM::S10 },
1455  { ARM::S11 },
1456  { ARM::S12 },
1457  { ARM::S13 },
1458  { ARM::S14 },
1459  { ARM::S15 },
1460  { ARM::S16 },
1461  { ARM::S17 },
1462  { ARM::S18 },
1463  { ARM::S19 },
1464  { ARM::S20 },
1465  { ARM::S21 },
1466  { ARM::S22 },
1467  { ARM::S23 },
1468  { ARM::S24 },
1469  { ARM::S25 },
1470  { ARM::S26 },
1471  { ARM::S27 },
1472  { ARM::S28 },
1473  { ARM::S29 },
1474  { ARM::S30 },
1475  { ARM::S31 },
1476  { ARM::D16 },
1477  { ARM::D17 },
1478  { ARM::D18 },
1479  { ARM::D19 },
1480  { ARM::D20 },
1481  { ARM::D21 },
1482  { ARM::D22 },
1483  { ARM::D23 },
1484  { ARM::D24 },
1485  { ARM::D25 },
1486  { ARM::D26 },
1487  { ARM::D27 },
1488  { ARM::D28 },
1489  { ARM::D29 },
1490  { ARM::D30 },
1491  { ARM::D31 },
1492  { ARM::FPINST2 },
1493  { ARM::MVFR0 },
1494  { ARM::MVFR1 },
1495  { ARM::MVFR2 },
1496  { ARM::R0 },
1497  { ARM::R1 },
1498  { ARM::R2 },
1499  { ARM::R3 },
1500  { ARM::R4 },
1501  { ARM::R5 },
1502  { ARM::R6 },
1503  { ARM::R7 },
1504  { ARM::R8 },
1505  { ARM::R9 },
1506  { ARM::R10 },
1507  { ARM::R11 },
1508  { ARM::R12 },
1509};
1510
1511namespace {     // Register classes...
1512  // HPR Register Class...
1513  const MCPhysReg HPR[] = {
1514    ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31,
1515  };
1516
1517  // HPR Bit set.
1518  const uint8_t HPRBits[] = {
1519    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
1520  };
1521
1522  // SPR Register Class...
1523  const MCPhysReg SPR[] = {
1524    ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31,
1525  };
1526
1527  // SPR Bit set.
1528  const uint8_t SPRBits[] = {
1529    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
1530  };
1531
1532  // GPR Register Class...
1533  const MCPhysReg GPR[] = {
1534    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC,
1535  };
1536
1537  // GPR Bit set.
1538  const uint8_t GPRBits[] = {
1539    0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1540  };
1541
1542  // GPRwithAPSR Register Class...
1543  const MCPhysReg GPRwithAPSR[] = {
1544    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::APSR_NZCV,
1545  };
1546
1547  // GPRwithAPSR Bit set.
1548  const uint8_t GPRwithAPSRBits[] = {
1549    0x04, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1550  };
1551
1552  // SPR_8 Register Class...
1553  const MCPhysReg SPR_8[] = {
1554    ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1555  };
1556
1557  // SPR_8 Bit set.
1558  const uint8_t SPR_8Bits[] = {
1559    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1560  };
1561
1562  // GPRnopc Register Class...
1563  const MCPhysReg GPRnopc[] = {
1564    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR,
1565  };
1566
1567  // GPRnopc Bit set.
1568  const uint8_t GPRnopcBits[] = {
1569    0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1570  };
1571
1572  // rGPR Register Class...
1573  const MCPhysReg rGPR[] = {
1574    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR,
1575  };
1576
1577  // rGPR Bit set.
1578  const uint8_t rGPRBits[] = {
1579    0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1580  };
1581
1582  // tGPRwithpc Register Class...
1583  const MCPhysReg tGPRwithpc[] = {
1584    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::PC,
1585  };
1586
1587  // tGPRwithpc Bit set.
1588  const uint8_t tGPRwithpcBits[] = {
1589    0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
1590  };
1591
1592  // hGPR Register Class...
1593  const MCPhysReg hGPR[] = {
1594    ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC,
1595  };
1596
1597  // hGPR Bit set.
1598  const uint8_t hGPRBits[] = {
1599    0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
1600  };
1601
1602  // tGPR Register Class...
1603  const MCPhysReg tGPR[] = {
1604    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1605  };
1606
1607  // tGPR Bit set.
1608  const uint8_t tGPRBits[] = {
1609    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
1610  };
1611
1612  // GPRnopc_and_hGPR Register Class...
1613  const MCPhysReg GPRnopc_and_hGPR[] = {
1614    ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR,
1615  };
1616
1617  // GPRnopc_and_hGPR Bit set.
1618  const uint8_t GPRnopc_and_hGPRBits[] = {
1619    0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
1620  };
1621
1622  // hGPR_and_rGPR Register Class...
1623  const MCPhysReg hGPR_and_rGPR[] = {
1624    ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR,
1625  };
1626
1627  // hGPR_and_rGPR Bit set.
1628  const uint8_t hGPR_and_rGPRBits[] = {
1629    0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
1630  };
1631
1632  // tcGPR Register Class...
1633  const MCPhysReg tcGPR[] = {
1634    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12,
1635  };
1636
1637  // tcGPR Bit set.
1638  const uint8_t tcGPRBits[] = {
1639    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x40,
1640  };
1641
1642  // tGPR_and_tcGPR Register Class...
1643  const MCPhysReg tGPR_and_tcGPR[] = {
1644    ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1645  };
1646
1647  // tGPR_and_tcGPR Bit set.
1648  const uint8_t tGPR_and_tcGPRBits[] = {
1649    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1650  };
1651
1652  // CCR Register Class...
1653  const MCPhysReg CCR[] = {
1654    ARM::CPSR,
1655  };
1656
1657  // CCR Bit set.
1658  const uint8_t CCRBits[] = {
1659    0x08,
1660  };
1661
1662  // GPRsp Register Class...
1663  const MCPhysReg GPRsp[] = {
1664    ARM::SP,
1665  };
1666
1667  // GPRsp Bit set.
1668  const uint8_t GPRspBits[] = {
1669    0x00, 0x10,
1670  };
1671
1672  // hGPR_and_tGPRwithpc Register Class...
1673  const MCPhysReg hGPR_and_tGPRwithpc[] = {
1674    ARM::PC,
1675  };
1676
1677  // hGPR_and_tGPRwithpc Bit set.
1678  const uint8_t hGPR_and_tGPRwithpcBits[] = {
1679    0x00, 0x08,
1680  };
1681
1682  // hGPR_and_tcGPR Register Class...
1683  const MCPhysReg hGPR_and_tcGPR[] = {
1684    ARM::R12,
1685  };
1686
1687  // hGPR_and_tcGPR Bit set.
1688  const uint8_t hGPR_and_tcGPRBits[] = {
1689    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
1690  };
1691
1692  // DPR Register Class...
1693  const MCPhysReg DPR[] = {
1694    ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31,
1695  };
1696
1697  // DPR Bit set.
1698  const uint8_t DPRBits[] = {
1699    0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
1700  };
1701
1702  // DPR_VFP2 Register Class...
1703  const MCPhysReg DPR_VFP2[] = {
1704    ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1705  };
1706
1707  // DPR_VFP2 Bit set.
1708  const uint8_t DPR_VFP2Bits[] = {
1709    0x00, 0xc0, 0xff, 0x3f,
1710  };
1711
1712  // DPR_8 Register Class...
1713  const MCPhysReg DPR_8[] = {
1714    ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1715  };
1716
1717  // DPR_8 Bit set.
1718  const uint8_t DPR_8Bits[] = {
1719    0x00, 0xc0, 0x3f,
1720  };
1721
1722  // GPRPair Register Class...
1723  const MCPhysReg GPRPair[] = {
1724    ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, ARM::R12_SP,
1725  };
1726
1727  // GPRPair Bit set.
1728  const uint8_t GPRPairBits[] = {
1729    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
1730  };
1731
1732  // GPRPair_with_gsub_1_in_rGPR Register Class...
1733  const MCPhysReg GPRPair_with_gsub_1_in_rGPR[] = {
1734    ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11,
1735  };
1736
1737  // GPRPair_with_gsub_1_in_rGPR Bit set.
1738  const uint8_t GPRPair_with_gsub_1_in_rGPRBits[] = {
1739    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc,
1740  };
1741
1742  // GPRPair_with_gsub_0_in_tGPR Register Class...
1743  const MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = {
1744    ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1745  };
1746
1747  // GPRPair_with_gsub_0_in_tGPR Bit set.
1748  const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = {
1749    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1750  };
1751
1752  // GPRPair_with_gsub_0_in_hGPR Register Class...
1753  const MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = {
1754    ARM::R8_R9, ARM::R10_R11, ARM::R12_SP,
1755  };
1756
1757  // GPRPair_with_gsub_0_in_hGPR Bit set.
1758  const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = {
1759    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2,
1760  };
1761
1762  // GPRPair_with_gsub_0_in_tcGPR Register Class...
1763  const MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = {
1764    ARM::R0_R1, ARM::R2_R3, ARM::R12_SP,
1765  };
1766
1767  // GPRPair_with_gsub_0_in_tcGPR Bit set.
1768  const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = {
1769    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e,
1770  };
1771
1772  // GPRPair_with_gsub_1_in_hGPR_and_rGPR Register Class...
1773  const MCPhysReg GPRPair_with_gsub_1_in_hGPR_and_rGPR[] = {
1774    ARM::R8_R9, ARM::R10_R11,
1775  };
1776
1777  // GPRPair_with_gsub_1_in_hGPR_and_rGPR Bit set.
1778  const uint8_t GPRPair_with_gsub_1_in_hGPR_and_rGPRBits[] = {
1779    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
1780  };
1781
1782  // GPRPair_with_gsub_1_in_tcGPR Register Class...
1783  const MCPhysReg GPRPair_with_gsub_1_in_tcGPR[] = {
1784    ARM::R0_R1, ARM::R2_R3,
1785  };
1786
1787  // GPRPair_with_gsub_1_in_tcGPR Bit set.
1788  const uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = {
1789    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c,
1790  };
1791
1792  // GPRPair_with_gsub_1_in_GPRsp Register Class...
1793  const MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = {
1794    ARM::R12_SP,
1795  };
1796
1797  // GPRPair_with_gsub_1_in_GPRsp Bit set.
1798  const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = {
1799    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
1800  };
1801
1802  // DPairSpc Register Class...
1803  const MCPhysReg DPairSpc[] = {
1804    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, ARM::D28_D30, ARM::D29_D31,
1805  };
1806
1807  // DPairSpc Bit set.
1808  const uint8_t DPairSpcBits[] = {
1809    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f,
1810  };
1811
1812  // DPairSpc_with_ssub_0 Register Class...
1813  const MCPhysReg DPairSpc_with_ssub_0[] = {
1814    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1815  };
1816
1817  // DPairSpc_with_ssub_0 Bit set.
1818  const uint8_t DPairSpc_with_ssub_0Bits[] = {
1819    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1820  };
1821
1822  // DPairSpc_with_ssub_4 Register Class...
1823  const MCPhysReg DPairSpc_with_ssub_4[] = {
1824    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15,
1825  };
1826
1827  // DPairSpc_with_ssub_4 Bit set.
1828  const uint8_t DPairSpc_with_ssub_4Bits[] = {
1829    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f,
1830  };
1831
1832  // DPairSpc_with_dsub_0_in_DPR_8 Register Class...
1833  const MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = {
1834    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1835  };
1836
1837  // DPairSpc_with_dsub_0_in_DPR_8 Bit set.
1838  const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = {
1839    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1840  };
1841
1842  // DPairSpc_with_dsub_2_in_DPR_8 Register Class...
1843  const MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = {
1844    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7,
1845  };
1846
1847  // DPairSpc_with_dsub_2_in_DPR_8 Bit set.
1848  const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = {
1849    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f,
1850  };
1851
1852  // DPair Register Class...
1853  const MCPhysReg DPair[] = {
1854    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, ARM::Q15,
1855  };
1856
1857  // DPair Bit set.
1858  const uint8_t DPairBits[] = {
1859    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
1860  };
1861
1862  // DPair_with_ssub_0 Register Class...
1863  const MCPhysReg DPair_with_ssub_0[] = {
1864    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16,
1865  };
1866
1867  // DPair_with_ssub_0 Bit set.
1868  const uint8_t DPair_with_ssub_0Bits[] = {
1869    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
1870  };
1871
1872  // QPR Register Class...
1873  const MCPhysReg QPR[] = {
1874    ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15,
1875  };
1876
1877  // QPR Bit set.
1878  const uint8_t QPRBits[] = {
1879    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
1880  };
1881
1882  // DPair_with_ssub_2 Register Class...
1883  const MCPhysReg DPair_with_ssub_2[] = {
1884    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7,
1885  };
1886
1887  // DPair_with_ssub_2 Bit set.
1888  const uint8_t DPair_with_ssub_2Bits[] = {
1889    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
1890  };
1891
1892  // DPair_with_dsub_0_in_DPR_8 Register Class...
1893  const MCPhysReg DPair_with_dsub_0_in_DPR_8[] = {
1894    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8,
1895  };
1896
1897  // DPair_with_dsub_0_in_DPR_8 Bit set.
1898  const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = {
1899    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
1900  };
1901
1902  // QPR_VFP2 Register Class...
1903  const MCPhysReg QPR_VFP2[] = {
1904    ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1905  };
1906
1907  // QPR_VFP2 Bit set.
1908  const uint8_t QPR_VFP2Bits[] = {
1909    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
1910  };
1911
1912  // DPair_with_dsub_1_in_DPR_8 Register Class...
1913  const MCPhysReg DPair_with_dsub_1_in_DPR_8[] = {
1914    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3,
1915  };
1916
1917  // DPair_with_dsub_1_in_DPR_8 Bit set.
1918  const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = {
1919    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
1920  };
1921
1922  // QPR_8 Register Class...
1923  const MCPhysReg QPR_8[] = {
1924    ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1925  };
1926
1927  // QPR_8 Bit set.
1928  const uint8_t QPR_8Bits[] = {
1929    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1930  };
1931
1932  // DTriple Register Class...
1933  const MCPhysReg DTriple[] = {
1934    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, ARM::D16_D17_D18, ARM::D17_D18_D19, ARM::D18_D19_D20, ARM::D19_D20_D21, ARM::D20_D21_D22, ARM::D21_D22_D23, ARM::D22_D23_D24, ARM::D23_D24_D25, ARM::D24_D25_D26, ARM::D25_D26_D27, ARM::D26_D27_D28, ARM::D27_D28_D29, ARM::D28_D29_D30, ARM::D29_D30_D31,
1935  };
1936
1937  // DTriple Bit set.
1938  const uint8_t DTripleBits[] = {
1939    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x3f,
1940  };
1941
1942  // DTripleSpc Register Class...
1943  const MCPhysReg DTripleSpc[] = {
1944    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31,
1945  };
1946
1947  // DTripleSpc Bit set.
1948  const uint8_t DTripleSpcBits[] = {
1949    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03,
1950  };
1951
1952  // DTripleSpc_with_ssub_0 Register Class...
1953  const MCPhysReg DTripleSpc_with_ssub_0[] = {
1954    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19,
1955  };
1956
1957  // DTripleSpc_with_ssub_0 Bit set.
1958  const uint8_t DTripleSpc_with_ssub_0Bits[] = {
1959    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
1960  };
1961
1962  // DTriple_with_ssub_0 Register Class...
1963  const MCPhysReg DTriple_with_ssub_0[] = {
1964    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17,
1965  };
1966
1967  // DTriple_with_ssub_0 Bit set.
1968  const uint8_t DTriple_with_ssub_0Bits[] = {
1969    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
1970  };
1971
1972  // DTriple_with_qsub_0_in_QPR Register Class...
1973  const MCPhysReg DTriple_with_qsub_0_in_QPR[] = {
1974    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, ARM::D16_D17_D18, ARM::D18_D19_D20, ARM::D20_D21_D22, ARM::D22_D23_D24, ARM::D24_D25_D26, ARM::D26_D27_D28, ARM::D28_D29_D30,
1975  };
1976
1977  // DTriple_with_qsub_0_in_QPR Bit set.
1978  const uint8_t DTriple_with_qsub_0_in_QPRBits[] = {
1979    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15,
1980  };
1981
1982  // DTriple_with_ssub_2 Register Class...
1983  const MCPhysReg DTriple_with_ssub_2[] = {
1984    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16,
1985  };
1986
1987  // DTriple_with_ssub_2 Bit set.
1988  const uint8_t DTriple_with_ssub_2Bits[] = {
1989    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f,
1990  };
1991
1992  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
1993  const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
1994    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, ARM::D17_D18_D19, ARM::D19_D20_D21, ARM::D21_D22_D23, ARM::D23_D24_D25, ARM::D25_D26_D27, ARM::D27_D28_D29, ARM::D29_D30_D31,
1995  };
1996
1997  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
1998  const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
1999    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x2a,
2000  };
2001
2002  // DTripleSpc_with_ssub_4 Register Class...
2003  const MCPhysReg DTripleSpc_with_ssub_4[] = {
2004    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17,
2005  };
2006
2007  // DTripleSpc_with_ssub_4 Bit set.
2008  const uint8_t DTripleSpc_with_ssub_4Bits[] = {
2009    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f,
2010  };
2011
2012  // DTriple_with_ssub_4 Register Class...
2013  const MCPhysReg DTriple_with_ssub_4[] = {
2014    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15,
2015  };
2016
2017  // DTriple_with_ssub_4 Bit set.
2018  const uint8_t DTriple_with_ssub_4Bits[] = {
2019    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f,
2020  };
2021
2022  // DTripleSpc_with_ssub_8 Register Class...
2023  const MCPhysReg DTripleSpc_with_ssub_8[] = {
2024    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15,
2025  };
2026
2027  // DTripleSpc_with_ssub_8 Bit set.
2028  const uint8_t DTripleSpc_with_ssub_8Bits[] = {
2029    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03,
2030  };
2031
2032  // DTripleSpc_with_dsub_0_in_DPR_8 Register Class...
2033  const MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = {
2034    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11,
2035  };
2036
2037  // DTripleSpc_with_dsub_0_in_DPR_8 Bit set.
2038  const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = {
2039    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
2040  };
2041
2042  // DTriple_with_dsub_0_in_DPR_8 Register Class...
2043  const MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = {
2044    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9,
2045  };
2046
2047  // DTriple_with_dsub_0_in_DPR_8 Bit set.
2048  const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = {
2049    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
2050  };
2051
2052  // DTriple_with_qsub_0_in_QPR_VFP2 Register Class...
2053  const MCPhysReg DTriple_with_qsub_0_in_QPR_VFP2[] = {
2054    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16,
2055  };
2056
2057  // DTriple_with_qsub_0_in_QPR_VFP2 Bit set.
2058  const uint8_t DTriple_with_qsub_0_in_QPR_VFP2Bits[] = {
2059    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
2060  };
2061
2062  // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2063  const MCPhysReg DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2064    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17,
2065  };
2066
2067  // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2068  const uint8_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2069    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa,
2070  };
2071
2072  // DTriple_with_dsub_1_in_DPR_8 Register Class...
2073  const MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = {
2074    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8,
2075  };
2076
2077  // DTriple_with_dsub_1_in_DPR_8 Bit set.
2078  const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = {
2079    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
2080  };
2081
2082  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Register Class...
2083  const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2[] = {
2084    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15,
2085  };
2086
2087  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Bit set.
2088  const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits[] = {
2089    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a,
2090  };
2091
2092  // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR Register Class...
2093  const MCPhysReg DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR[] = {
2094    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14,
2095  };
2096
2097  // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR Bit set.
2098  const uint8_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits[] = {
2099    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15,
2100  };
2101
2102  // DTripleSpc_with_dsub_2_in_DPR_8 Register Class...
2103  const MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = {
2104    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9,
2105  };
2106
2107  // DTripleSpc_with_dsub_2_in_DPR_8 Bit set.
2108  const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = {
2109    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
2110  };
2111
2112  // DTriple_with_dsub_2_in_DPR_8 Register Class...
2113  const MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = {
2114    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7,
2115  };
2116
2117  // DTriple_with_dsub_2_in_DPR_8 Bit set.
2118  const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = {
2119    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f,
2120  };
2121
2122  // DTripleSpc_with_dsub_4_in_DPR_8 Register Class...
2123  const MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = {
2124    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7,
2125  };
2126
2127  // DTripleSpc_with_dsub_4_in_DPR_8 Bit set.
2128  const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = {
2129    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03,
2130  };
2131
2132  // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2133  const MCPhysReg DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2134    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9,
2135  };
2136
2137  // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2138  const uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2139    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa,
2140  };
2141
2142  // DTriple_with_qsub_0_in_QPR_8 Register Class...
2143  const MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = {
2144    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8,
2145  };
2146
2147  // DTriple_with_qsub_0_in_QPR_8 Bit set.
2148  const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = {
2149    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55,
2150  };
2151
2152  // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Register Class...
2153  const MCPhysReg DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR[] = {
2154    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6,
2155  };
2156
2157  // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Bit set.
2158  const uint8_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits[] = {
2159    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15,
2160  };
2161
2162  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
2163  const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
2164    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7,
2165  };
2166
2167  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
2168  const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
2169    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a,
2170  };
2171
2172  // DQuadSpc Register Class...
2173  const MCPhysReg DQuadSpc[] = {
2174    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31,
2175  };
2176
2177  // DQuadSpc Bit set.
2178  const uint8_t DQuadSpcBits[] = {
2179    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03,
2180  };
2181
2182  // DQuadSpc_with_ssub_0 Register Class...
2183  const MCPhysReg DQuadSpc_with_ssub_0[] = {
2184    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19,
2185  };
2186
2187  // DQuadSpc_with_ssub_0 Bit set.
2188  const uint8_t DQuadSpc_with_ssub_0Bits[] = {
2189    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
2190  };
2191
2192  // DQuadSpc_with_ssub_4 Register Class...
2193  const MCPhysReg DQuadSpc_with_ssub_4[] = {
2194    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17,
2195  };
2196
2197  // DQuadSpc_with_ssub_4 Bit set.
2198  const uint8_t DQuadSpc_with_ssub_4Bits[] = {
2199    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f,
2200  };
2201
2202  // DQuadSpc_with_ssub_8 Register Class...
2203  const MCPhysReg DQuadSpc_with_ssub_8[] = {
2204    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15,
2205  };
2206
2207  // DQuadSpc_with_ssub_8 Bit set.
2208  const uint8_t DQuadSpc_with_ssub_8Bits[] = {
2209    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03,
2210  };
2211
2212  // DQuadSpc_with_dsub_0_in_DPR_8 Register Class...
2213  const MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = {
2214    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11,
2215  };
2216
2217  // DQuadSpc_with_dsub_0_in_DPR_8 Bit set.
2218  const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = {
2219    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
2220  };
2221
2222  // DQuadSpc_with_dsub_2_in_DPR_8 Register Class...
2223  const MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = {
2224    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9,
2225  };
2226
2227  // DQuadSpc_with_dsub_2_in_DPR_8 Bit set.
2228  const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = {
2229    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
2230  };
2231
2232  // DQuadSpc_with_dsub_4_in_DPR_8 Register Class...
2233  const MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = {
2234    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7,
2235  };
2236
2237  // DQuadSpc_with_dsub_4_in_DPR_8 Bit set.
2238  const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = {
2239    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03,
2240  };
2241
2242  // DQuad Register Class...
2243  const MCPhysReg DQuad[] = {
2244    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, ARM::Q8_Q9, ARM::D17_D18_D19_D20, ARM::Q9_Q10, ARM::D19_D20_D21_D22, ARM::Q10_Q11, ARM::D21_D22_D23_D24, ARM::Q11_Q12, ARM::D23_D24_D25_D26, ARM::Q12_Q13, ARM::D25_D26_D27_D28, ARM::Q13_Q14, ARM::D27_D28_D29_D30, ARM::Q14_Q15,
2245  };
2246
2247  // DQuad Bit set.
2248  const uint8_t DQuadBits[] = {
2249    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
2250  };
2251
2252  // DQuad_with_ssub_0 Register Class...
2253  const MCPhysReg DQuad_with_ssub_0[] = {
2254    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18,
2255  };
2256
2257  // DQuad_with_ssub_0 Bit set.
2258  const uint8_t DQuad_with_ssub_0Bits[] = {
2259    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
2260  };
2261
2262  // DQuad_with_ssub_2 Register Class...
2263  const MCPhysReg DQuad_with_ssub_2[] = {
2264    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8,
2265  };
2266
2267  // DQuad_with_ssub_2 Bit set.
2268  const uint8_t DQuad_with_ssub_2Bits[] = {
2269    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
2270  };
2271
2272  // QQPR Register Class...
2273  const MCPhysReg QQPR[] = {
2274    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, ARM::Q8_Q9, ARM::Q9_Q10, ARM::Q10_Q11, ARM::Q11_Q12, ARM::Q12_Q13, ARM::Q13_Q14, ARM::Q14_Q15,
2275  };
2276
2277  // QQPR Bit set.
2278  const uint8_t QQPRBits[] = {
2279    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
2280  };
2281
2282  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2283  const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2284    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, ARM::D17_D18_D19_D20, ARM::D19_D20_D21_D22, ARM::D21_D22_D23_D24, ARM::D23_D24_D25_D26, ARM::D25_D26_D27_D28, ARM::D27_D28_D29_D30,
2285  };
2286
2287  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2288  const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2289    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
2290  };
2291
2292  // DQuad_with_ssub_4 Register Class...
2293  const MCPhysReg DQuad_with_ssub_4[] = {
2294    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16,
2295  };
2296
2297  // DQuad_with_ssub_4 Bit set.
2298  const uint8_t DQuad_with_ssub_4Bits[] = {
2299    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
2300  };
2301
2302  // DQuad_with_ssub_6 Register Class...
2303  const MCPhysReg DQuad_with_ssub_6[] = {
2304    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7,
2305  };
2306
2307  // DQuad_with_ssub_6 Bit set.
2308  const uint8_t DQuad_with_ssub_6Bits[] = {
2309    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01,
2310  };
2311
2312  // DQuad_with_dsub_0_in_DPR_8 Register Class...
2313  const MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = {
2314    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10,
2315  };
2316
2317  // DQuad_with_dsub_0_in_DPR_8 Bit set.
2318  const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = {
2319    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
2320  };
2321
2322  // DQuad_with_qsub_0_in_QPR_VFP2 Register Class...
2323  const MCPhysReg DQuad_with_qsub_0_in_QPR_VFP2[] = {
2324    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8,
2325  };
2326
2327  // DQuad_with_qsub_0_in_QPR_VFP2 Bit set.
2328  const uint8_t DQuad_with_qsub_0_in_QPR_VFP2Bits[] = {
2329    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
2330  };
2331
2332  // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2333  const MCPhysReg DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2334    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18,
2335  };
2336
2337  // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2338  const uint8_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2339    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
2340  };
2341
2342  // DQuad_with_dsub_1_in_DPR_8 Register Class...
2343  const MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = {
2344    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4,
2345  };
2346
2347  // DQuad_with_dsub_1_in_DPR_8 Bit set.
2348  const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = {
2349    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
2350  };
2351
2352  // DQuad_with_qsub_1_in_QPR_VFP2 Register Class...
2353  const MCPhysReg DQuad_with_qsub_1_in_QPR_VFP2[] = {
2354    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7,
2355  };
2356
2357  // DQuad_with_qsub_1_in_QPR_VFP2 Bit set.
2358  const uint8_t DQuad_with_qsub_1_in_QPR_VFP2Bits[] = {
2359    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f,
2360  };
2361
2362  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Register Class...
2363  const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2[] = {
2364    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16,
2365  };
2366
2367  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Bit set.
2368  const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits[] = {
2369    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
2370  };
2371
2372  // DQuad_with_dsub_2_in_DPR_8 Register Class...
2373  const MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = {
2374    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8,
2375  };
2376
2377  // DQuad_with_dsub_2_in_DPR_8 Bit set.
2378  const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = {
2379    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
2380  };
2381
2382  // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2383  const MCPhysReg DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2384    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14,
2385  };
2386
2387  // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2388  const uint8_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2389    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01,
2390  };
2391
2392  // DQuad_with_dsub_3_in_DPR_8 Register Class...
2393  const MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = {
2394    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3,
2395  };
2396
2397  // DQuad_with_dsub_3_in_DPR_8 Bit set.
2398  const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = {
2399    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
2400  };
2401
2402  // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2403  const MCPhysReg DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2404    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10,
2405  };
2406
2407  // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2408  const uint8_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2409    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
2410  };
2411
2412  // DQuad_with_qsub_0_in_QPR_8 Register Class...
2413  const MCPhysReg DQuad_with_qsub_0_in_QPR_8[] = {
2414    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,
2415  };
2416
2417  // DQuad_with_qsub_0_in_QPR_8 Bit set.
2418  const uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = {
2419    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
2420  };
2421
2422  // DQuad_with_qsub_1_in_QPR_8 Register Class...
2423  const MCPhysReg DQuad_with_qsub_1_in_QPR_8[] = {
2424    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3,
2425  };
2426
2427  // DQuad_with_qsub_1_in_QPR_8 Bit set.
2428  const uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = {
2429    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
2430  };
2431
2432  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
2433  const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
2434    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8,
2435  };
2436
2437  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
2438  const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
2439    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
2440  };
2441
2442  // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
2443  const MCPhysReg DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
2444    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6,
2445  };
2446
2447  // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
2448  const uint8_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
2449    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
2450  };
2451
2452  // QQQQPR Register Class...
2453  const MCPhysReg QQQQPR[] = {
2454    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, ARM::Q8_Q9_Q10_Q11, ARM::Q9_Q10_Q11_Q12, ARM::Q10_Q11_Q12_Q13, ARM::Q11_Q12_Q13_Q14, ARM::Q12_Q13_Q14_Q15,
2455  };
2456
2457  // QQQQPR Bit set.
2458  const uint8_t QQQQPRBits[] = {
2459    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01,
2460  };
2461
2462  // QQQQPR_with_ssub_0 Register Class...
2463  const MCPhysReg QQQQPR_with_ssub_0[] = {
2464    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10,
2465  };
2466
2467  // QQQQPR_with_ssub_0 Bit set.
2468  const uint8_t QQQQPR_with_ssub_0Bits[] = {
2469    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
2470  };
2471
2472  // QQQQPR_with_ssub_4 Register Class...
2473  const MCPhysReg QQQQPR_with_ssub_4[] = {
2474    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9,
2475  };
2476
2477  // QQQQPR_with_ssub_4 Bit set.
2478  const uint8_t QQQQPR_with_ssub_4Bits[] = {
2479    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
2480  };
2481
2482  // QQQQPR_with_ssub_8 Register Class...
2483  const MCPhysReg QQQQPR_with_ssub_8[] = {
2484    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8,
2485  };
2486
2487  // QQQQPR_with_ssub_8 Bit set.
2488  const uint8_t QQQQPR_with_ssub_8Bits[] = {
2489    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03,
2490  };
2491
2492  // QQQQPR_with_ssub_12 Register Class...
2493  const MCPhysReg QQQQPR_with_ssub_12[] = {
2494    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7,
2495  };
2496
2497  // QQQQPR_with_ssub_12 Bit set.
2498  const uint8_t QQQQPR_with_ssub_12Bits[] = {
2499    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01,
2500  };
2501
2502  // QQQQPR_with_dsub_0_in_DPR_8 Register Class...
2503  const MCPhysReg QQQQPR_with_dsub_0_in_DPR_8[] = {
2504    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6,
2505  };
2506
2507  // QQQQPR_with_dsub_0_in_DPR_8 Bit set.
2508  const uint8_t QQQQPR_with_dsub_0_in_DPR_8Bits[] = {
2509    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
2510  };
2511
2512  // QQQQPR_with_dsub_2_in_DPR_8 Register Class...
2513  const MCPhysReg QQQQPR_with_dsub_2_in_DPR_8[] = {
2514    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,
2515  };
2516
2517  // QQQQPR_with_dsub_2_in_DPR_8 Bit set.
2518  const uint8_t QQQQPR_with_dsub_2_in_DPR_8Bits[] = {
2519    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
2520  };
2521
2522  // QQQQPR_with_dsub_4_in_DPR_8 Register Class...
2523  const MCPhysReg QQQQPR_with_dsub_4_in_DPR_8[] = {
2524    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4,
2525  };
2526
2527  // QQQQPR_with_dsub_4_in_DPR_8 Bit set.
2528  const uint8_t QQQQPR_with_dsub_4_in_DPR_8Bits[] = {
2529    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
2530  };
2531
2532  // QQQQPR_with_dsub_6_in_DPR_8 Register Class...
2533  const MCPhysReg QQQQPR_with_dsub_6_in_DPR_8[] = {
2534    ARM::Q0_Q1_Q2_Q3,
2535  };
2536
2537  // QQQQPR_with_dsub_6_in_DPR_8 Bit set.
2538  const uint8_t QQQQPR_with_dsub_6_in_DPR_8Bits[] = {
2539    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2540  };
2541
2542} // end anonymous namespace
2543
2544extern const char ARMRegClassStrings[] = {
2545  /* 0 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2546  /* 19 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2547  /* 40 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2548  /* 63 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2549  /* 84 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2550  /* 102 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2551  /* 122 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
2552  /* 140 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '1', '2', 0,
2553  /* 160 */ 'D', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2554  /* 169 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2555  /* 199 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2556  /* 231 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2557  /* 261 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2558  /* 312 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
2559  /* 365 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
2560  /* 383 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
2561  /* 403 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
2562  /* 421 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2563  /* 440 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2564  /* 461 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2565  /* 484 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2566  /* 505 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2567  /* 523 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
2568  /* 543 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '6', 0,
2569  /* 561 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2570  /* 589 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2571  /* 619 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2572  /* 651 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2573  /* 681 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2574  /* 708 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2575  /* 737 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2576  /* 764 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2577  /* 791 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2578  /* 820 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2579  /* 847 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2580  /* 875 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2581  /* 905 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2582  /* 937 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2583  /* 967 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2584  /* 994 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2585  /* 1023 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '3', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2586  /* 1050 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2587  /* 1078 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2588  /* 1108 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2589  /* 1140 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '6', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
2590  /* 1168 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
2591  /* 1195 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
2592  /* 1224 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
2593  /* 1251 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
2594  /* 1299 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
2595  /* 1349 */ 'S', 'P', 'R', '_', '8', 0,
2596  /* 1355 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0,
2597  /* 1374 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0,
2598  /* 1395 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0,
2599  /* 1418 */ 'C', 'C', 'R', 0,
2600  /* 1422 */ 'D', 'P', 'R', 0,
2601  /* 1426 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0,
2602  /* 1441 */ 't', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0,
2603  /* 1456 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', 0,
2604  /* 1485 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', 0,
2605  /* 1514 */ 'G', 'P', 'R', 'n', 'o', 'p', 'c', '_', 'a', 'n', 'd', '_', 'h', 'G', 'P', 'R', 0,
2606  /* 1531 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'h', 'G', 'P', 'R', 0,
2607  /* 1559 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 'r', 'G', 'P', 'R', 0,
2608  /* 1596 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'r', 'G', 'P', 'R', 0,
2609  /* 1624 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 't', 'G', 'P', 'R', 0,
2610  /* 1652 */ 'H', 'P', 'R', 0,
2611  /* 1656 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', 0,
2612  /* 1663 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2613  /* 1714 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2614  /* 1774 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2615  /* 1842 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '6', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2616  /* 1910 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2617  /* 1987 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '3', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2618  /* 2064 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2619  /* 2136 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
2620  /* 2217 */ 'S', 'P', 'R', 0,
2621  /* 2221 */ 'G', 'P', 'R', 'w', 'i', 't', 'h', 'A', 'P', 'S', 'R', 0,
2622  /* 2233 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', 0,
2623  /* 2242 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', 0,
2624  /* 2253 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', 0,
2625  /* 2262 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'G', 'P', 'R', 'w', 'i', 't', 'h', 'p', 'c', 0,
2626  /* 2282 */ 'G', 'P', 'R', 'n', 'o', 'p', 'c', 0,
2627  /* 2290 */ 'D', 'Q', 'u', 'a', 'd', 0,
2628  /* 2296 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 0,
2629  /* 2304 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'G', 'P', 'R', 's', 'p', 0,
2630  /* 2333 */ 'D', 'P', 'a', 'i', 'r', 0,
2631  /* 2339 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', 0,
2632};
2633
2634extern const MCRegisterClass ARMMCRegisterClasses[] = {
2635  { HPR, HPRBits, 1652, 32, sizeof(HPRBits), ARM::HPRRegClassID, 2, 1, true },
2636  { SPR, SPRBits, 2217, 32, sizeof(SPRBits), ARM::SPRRegClassID, 4, 1, true },
2637  { GPR, GPRBits, 1437, 16, sizeof(GPRBits), ARM::GPRRegClassID, 4, 1, true },
2638  { GPRwithAPSR, GPRwithAPSRBits, 2221, 16, sizeof(GPRwithAPSRBits), ARM::GPRwithAPSRRegClassID, 4, 1, true },
2639  { SPR_8, SPR_8Bits, 1349, 16, sizeof(SPR_8Bits), ARM::SPR_8RegClassID, 4, 1, true },
2640  { GPRnopc, GPRnopcBits, 2282, 15, sizeof(GPRnopcBits), ARM::GPRnopcRegClassID, 4, 1, true },
2641  { rGPR, rGPRBits, 1591, 14, sizeof(rGPRBits), ARM::rGPRRegClassID, 4, 1, true },
2642  { tGPRwithpc, tGPRwithpcBits, 2271, 9, sizeof(tGPRwithpcBits), ARM::tGPRwithpcRegClassID, 4, 1, true },
2643  { hGPR, hGPRBits, 1526, 8, sizeof(hGPRBits), ARM::hGPRRegClassID, 4, 1, true },
2644  { tGPR, tGPRBits, 1647, 8, sizeof(tGPRBits), ARM::tGPRRegClassID, 4, 1, true },
2645  { GPRnopc_and_hGPR, GPRnopc_and_hGPRBits, 1514, 7, sizeof(GPRnopc_and_hGPRBits), ARM::GPRnopc_and_hGPRRegClassID, 4, 1, true },
2646  { hGPR_and_rGPR, hGPR_and_rGPRBits, 1582, 6, sizeof(hGPR_and_rGPRBits), ARM::hGPR_and_rGPRRegClassID, 4, 1, true },
2647  { tcGPR, tcGPRBits, 1435, 5, sizeof(tcGPRBits), ARM::tcGPRRegClassID, 4, 1, true },
2648  { tGPR_and_tcGPR, tGPR_and_tcGPRBits, 1441, 4, sizeof(tGPR_and_tcGPRBits), ARM::tGPR_and_tcGPRRegClassID, 4, 1, true },
2649  { CCR, CCRBits, 1418, 1, sizeof(CCRBits), ARM::CCRRegClassID, 4, -1, false },
2650  { GPRsp, GPRspBits, 2327, 1, sizeof(GPRspBits), ARM::GPRspRegClassID, 4, 1, true },
2651  { hGPR_and_tGPRwithpc, hGPR_and_tGPRwithpcBits, 2262, 1, sizeof(hGPR_and_tGPRwithpcBits), ARM::hGPR_and_tGPRwithpcRegClassID, 4, 1, true },
2652  { hGPR_and_tcGPR, hGPR_and_tcGPRBits, 1426, 1, sizeof(hGPR_and_tcGPRBits), ARM::hGPR_and_tcGPRRegClassID, 4, 1, true },
2653  { DPR, DPRBits, 1422, 32, sizeof(DPRBits), ARM::DPRRegClassID, 8, 1, true },
2654  { DPR_VFP2, DPR_VFP2Bits, 160, 16, sizeof(DPR_VFP2Bits), ARM::DPR_VFP2RegClassID, 8, 1, true },
2655  { DPR_8, DPR_8Bits, 583, 8, sizeof(DPR_8Bits), ARM::DPR_8RegClassID, 8, 1, true },
2656  { GPRPair, GPRPairBits, 2339, 7, sizeof(GPRPairBits), ARM::GPRPairRegClassID, 8, 1, true },
2657  { GPRPair_with_gsub_1_in_rGPR, GPRPair_with_gsub_1_in_rGPRBits, 1596, 6, sizeof(GPRPair_with_gsub_1_in_rGPRBits), ARM::GPRPair_with_gsub_1_in_rGPRRegClassID, 8, 1, true },
2658  { GPRPair_with_gsub_0_in_tGPR, GPRPair_with_gsub_0_in_tGPRBits, 1624, 4, sizeof(GPRPair_with_gsub_0_in_tGPRBits), ARM::GPRPair_with_gsub_0_in_tGPRRegClassID, 8, 1, true },
2659  { GPRPair_with_gsub_0_in_hGPR, GPRPair_with_gsub_0_in_hGPRBits, 1531, 3, sizeof(GPRPair_with_gsub_0_in_hGPRBits), ARM::GPRPair_with_gsub_0_in_hGPRRegClassID, 8, 1, true },
2660  { GPRPair_with_gsub_0_in_tcGPR, GPRPair_with_gsub_0_in_tcGPRBits, 1456, 3, sizeof(GPRPair_with_gsub_0_in_tcGPRBits), ARM::GPRPair_with_gsub_0_in_tcGPRRegClassID, 8, 1, true },
2661  { GPRPair_with_gsub_1_in_hGPR_and_rGPR, GPRPair_with_gsub_1_in_hGPR_and_rGPRBits, 1559, 2, sizeof(GPRPair_with_gsub_1_in_hGPR_and_rGPRBits), ARM::GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID, 8, 1, true },
2662  { GPRPair_with_gsub_1_in_tcGPR, GPRPair_with_gsub_1_in_tcGPRBits, 1485, 2, sizeof(GPRPair_with_gsub_1_in_tcGPRBits), ARM::GPRPair_with_gsub_1_in_tcGPRRegClassID, 8, 1, true },
2663  { GPRPair_with_gsub_1_in_GPRsp, GPRPair_with_gsub_1_in_GPRspBits, 2304, 1, sizeof(GPRPair_with_gsub_1_in_GPRspBits), ARM::GPRPair_with_gsub_1_in_GPRspRegClassID, 8, 1, true },
2664  { DPairSpc, DPairSpcBits, 2253, 30, sizeof(DPairSpcBits), ARM::DPairSpcRegClassID, 16, 1, true },
2665  { DPairSpc_with_ssub_0, DPairSpc_with_ssub_0Bits, 63, 16, sizeof(DPairSpc_with_ssub_0Bits), ARM::DPairSpc_with_ssub_0RegClassID, 16, 1, true },
2666  { DPairSpc_with_ssub_4, DPairSpc_with_ssub_4Bits, 484, 14, sizeof(DPairSpc_with_ssub_4Bits), ARM::DPairSpc_with_ssub_4RegClassID, 16, 1, true },
2667  { DPairSpc_with_dsub_0_in_DPR_8, DPairSpc_with_dsub_0_in_DPR_8Bits, 651, 8, sizeof(DPairSpc_with_dsub_0_in_DPR_8Bits), ARM::DPairSpc_with_dsub_0_in_DPR_8RegClassID, 16, 1, true },
2668  { DPairSpc_with_dsub_2_in_DPR_8, DPairSpc_with_dsub_2_in_DPR_8Bits, 937, 6, sizeof(DPairSpc_with_dsub_2_in_DPR_8Bits), ARM::DPairSpc_with_dsub_2_in_DPR_8RegClassID, 16, 1, true },
2669  { DPair, DPairBits, 2333, 31, sizeof(DPairBits), ARM::DPairRegClassID, 16, 1, true },
2670  { DPair_with_ssub_0, DPair_with_ssub_0Bits, 122, 16, sizeof(DPair_with_ssub_0Bits), ARM::DPair_with_ssub_0RegClassID, 16, 1, true },
2671  { QPR, QPRBits, 1659, 16, sizeof(QPRBits), ARM::QPRRegClassID, 16, 1, true },
2672  { DPair_with_ssub_2, DPair_with_ssub_2Bits, 403, 15, sizeof(DPair_with_ssub_2Bits), ARM::DPair_with_ssub_2RegClassID, 16, 1, true },
2673  { DPair_with_dsub_0_in_DPR_8, DPair_with_dsub_0_in_DPR_8Bits, 737, 8, sizeof(DPair_with_dsub_0_in_DPR_8Bits), ARM::DPair_with_dsub_0_in_DPR_8RegClassID, 16, 1, true },
2674  { QPR_VFP2, QPR_VFP2Bits, 190, 8, sizeof(QPR_VFP2Bits), ARM::QPR_VFP2RegClassID, 16, 1, true },
2675  { DPair_with_dsub_1_in_DPR_8, DPair_with_dsub_1_in_DPR_8Bits, 820, 7, sizeof(DPair_with_dsub_1_in_DPR_8Bits), ARM::DPair_with_dsub_1_in_DPR_8RegClassID, 16, 1, true },
2676  { QPR_8, QPR_8Bits, 1189, 4, sizeof(QPR_8Bits), ARM::QPR_8RegClassID, 16, 1, true },
2677  { DTriple, DTripleBits, 2296, 30, sizeof(DTripleBits), ARM::DTripleRegClassID, 24, 1, true },
2678  { DTripleSpc, DTripleSpcBits, 2242, 28, sizeof(DTripleSpcBits), ARM::DTripleSpcRegClassID, 24, 1, true },
2679  { DTripleSpc_with_ssub_0, DTripleSpc_with_ssub_0Bits, 40, 16, sizeof(DTripleSpc_with_ssub_0Bits), ARM::DTripleSpc_with_ssub_0RegClassID, 24, 1, true },
2680  { DTriple_with_ssub_0, DTriple_with_ssub_0Bits, 102, 16, sizeof(DTriple_with_ssub_0Bits), ARM::DTriple_with_ssub_0RegClassID, 24, 1, true },
2681  { DTriple_with_qsub_0_in_QPR, DTriple_with_qsub_0_in_QPRBits, 1687, 15, sizeof(DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_qsub_0_in_QPRRegClassID, 24, 1, true },
2682  { DTriple_with_ssub_2, DTriple_with_ssub_2Bits, 383, 15, sizeof(DTriple_with_ssub_2Bits), ARM::DTriple_with_ssub_2RegClassID, 24, 1, true },
2683  { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2088, 15, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 24, 1, true },
2684  { DTripleSpc_with_ssub_4, DTripleSpc_with_ssub_4Bits, 461, 14, sizeof(DTripleSpc_with_ssub_4Bits), ARM::DTripleSpc_with_ssub_4RegClassID, 24, 1, true },
2685  { DTriple_with_ssub_4, DTriple_with_ssub_4Bits, 523, 14, sizeof(DTriple_with_ssub_4Bits), ARM::DTriple_with_ssub_4RegClassID, 24, 1, true },
2686  { DTripleSpc_with_ssub_8, DTripleSpc_with_ssub_8Bits, 1395, 12, sizeof(DTripleSpc_with_ssub_8Bits), ARM::DTripleSpc_with_ssub_8RegClassID, 24, 1, true },
2687  { DTripleSpc_with_dsub_0_in_DPR_8, DTripleSpc_with_dsub_0_in_DPR_8Bits, 619, 8, sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID, 24, 1, true },
2688  { DTriple_with_dsub_0_in_DPR_8, DTriple_with_dsub_0_in_DPR_8Bits, 708, 8, sizeof(DTriple_with_dsub_0_in_DPR_8Bits), ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, 24, 1, true },
2689  { DTriple_with_qsub_0_in_QPR_VFP2, DTriple_with_qsub_0_in_QPR_VFP2Bits, 199, 8, sizeof(DTriple_with_qsub_0_in_QPR_VFP2Bits), ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClassID, 24, 1, true },
2690  { DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2064, 8, sizeof(DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 24, 1, true },
2691  { DTriple_with_dsub_1_in_DPR_8, DTriple_with_dsub_1_in_DPR_8Bits, 791, 7, sizeof(DTriple_with_dsub_1_in_DPR_8Bits), ARM::DTriple_with_dsub_1_in_DPR_8RegClassID, 24, 1, true },
2692  { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits, 312, 7, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID, 24, 1, true },
2693  { DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR, DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits, 1663, 7, sizeof(DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClassID, 24, 1, true },
2694  { DTripleSpc_with_dsub_2_in_DPR_8, DTripleSpc_with_dsub_2_in_DPR_8Bits, 905, 6, sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClassID, 24, 1, true },
2695  { DTriple_with_dsub_2_in_DPR_8, DTriple_with_dsub_2_in_DPR_8Bits, 994, 6, sizeof(DTriple_with_dsub_2_in_DPR_8Bits), ARM::DTriple_with_dsub_2_in_DPR_8RegClassID, 24, 1, true },
2696  { DTripleSpc_with_dsub_4_in_DPR_8, DTripleSpc_with_dsub_4_in_DPR_8Bits, 1108, 4, sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClassID, 24, 1, true },
2697  { DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2136, 4, sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 24, 1, true },
2698  { DTriple_with_qsub_0_in_QPR_8, DTriple_with_qsub_0_in_QPR_8Bits, 1195, 4, sizeof(DTriple_with_qsub_0_in_QPR_8Bits), ARM::DTriple_with_qsub_0_in_QPR_8RegClassID, 24, 1, true },
2699  { DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR, DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits, 1714, 3, sizeof(DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID, 24, 1, true },
2700  { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, 1299, 3, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID, 24, 1, true },
2701  { DQuadSpc, DQuadSpcBits, 2233, 28, sizeof(DQuadSpcBits), ARM::DQuadSpcRegClassID, 32, 1, true },
2702  { DQuadSpc_with_ssub_0, DQuadSpc_with_ssub_0Bits, 19, 16, sizeof(DQuadSpc_with_ssub_0Bits), ARM::DQuadSpc_with_ssub_0RegClassID, 32, 1, true },
2703  { DQuadSpc_with_ssub_4, DQuadSpc_with_ssub_4Bits, 440, 14, sizeof(DQuadSpc_with_ssub_4Bits), ARM::DQuadSpc_with_ssub_4RegClassID, 32, 1, true },
2704  { DQuadSpc_with_ssub_8, DQuadSpc_with_ssub_8Bits, 1374, 12, sizeof(DQuadSpc_with_ssub_8Bits), ARM::DQuadSpc_with_ssub_8RegClassID, 32, 1, true },
2705  { DQuadSpc_with_dsub_0_in_DPR_8, DQuadSpc_with_dsub_0_in_DPR_8Bits, 589, 8, sizeof(DQuadSpc_with_dsub_0_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClassID, 32, 1, true },
2706  { DQuadSpc_with_dsub_2_in_DPR_8, DQuadSpc_with_dsub_2_in_DPR_8Bits, 875, 6, sizeof(DQuadSpc_with_dsub_2_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClassID, 32, 1, true },
2707  { DQuadSpc_with_dsub_4_in_DPR_8, DQuadSpc_with_dsub_4_in_DPR_8Bits, 1078, 4, sizeof(DQuadSpc_with_dsub_4_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClassID, 32, 1, true },
2708  { DQuad, DQuadBits, 2290, 29, sizeof(DQuadBits), ARM::DQuadRegClassID, 32, 1, true },
2709  { DQuad_with_ssub_0, DQuad_with_ssub_0Bits, 84, 16, sizeof(DQuad_with_ssub_0Bits), ARM::DQuad_with_ssub_0RegClassID, 32, 1, true },
2710  { DQuad_with_ssub_2, DQuad_with_ssub_2Bits, 365, 15, sizeof(DQuad_with_ssub_2Bits), ARM::DQuad_with_ssub_2RegClassID, 32, 1, true },
2711  { QQPR, QQPRBits, 1658, 15, sizeof(QQPRBits), ARM::QQPRRegClassID, 32, 1, true },
2712  { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1796, 14, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 32, 1, true },
2713  { DQuad_with_ssub_4, DQuad_with_ssub_4Bits, 505, 14, sizeof(DQuad_with_ssub_4Bits), ARM::DQuad_with_ssub_4RegClassID, 32, 1, true },
2714  { DQuad_with_ssub_6, DQuad_with_ssub_6Bits, 543, 13, sizeof(DQuad_with_ssub_6Bits), ARM::DQuad_with_ssub_6RegClassID, 32, 1, true },
2715  { DQuad_with_dsub_0_in_DPR_8, DQuad_with_dsub_0_in_DPR_8Bits, 681, 8, sizeof(DQuad_with_dsub_0_in_DPR_8Bits), ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, 32, 1, true },
2716  { DQuad_with_qsub_0_in_QPR_VFP2, DQuad_with_qsub_0_in_QPR_VFP2Bits, 169, 8, sizeof(DQuad_with_qsub_0_in_QPR_VFP2Bits), ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClassID, 32, 1, true },
2717  { DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1774, 8, sizeof(DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 32, 1, true },
2718  { DQuad_with_dsub_1_in_DPR_8, DQuad_with_dsub_1_in_DPR_8Bits, 764, 7, sizeof(DQuad_with_dsub_1_in_DPR_8Bits), ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, 32, 1, true },
2719  { DQuad_with_qsub_1_in_QPR_VFP2, DQuad_with_qsub_1_in_QPR_VFP2Bits, 231, 7, sizeof(DQuad_with_qsub_1_in_QPR_VFP2Bits), ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClassID, 32, 1, true },
2720  { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits, 261, 7, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID, 32, 1, true },
2721  { DQuad_with_dsub_2_in_DPR_8, DQuad_with_dsub_2_in_DPR_8Bits, 967, 6, sizeof(DQuad_with_dsub_2_in_DPR_8Bits), ARM::DQuad_with_dsub_2_in_DPR_8RegClassID, 32, 1, true },
2722  { DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1842, 6, sizeof(DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 32, 1, true },
2723  { DQuad_with_dsub_3_in_DPR_8, DQuad_with_dsub_3_in_DPR_8Bits, 1023, 5, sizeof(DQuad_with_dsub_3_in_DPR_8Bits), ARM::DQuad_with_dsub_3_in_DPR_8RegClassID, 32, 1, true },
2724  { DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1910, 4, sizeof(DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 32, 1, true },
2725  { DQuad_with_qsub_0_in_QPR_8, DQuad_with_qsub_0_in_QPR_8Bits, 1168, 4, sizeof(DQuad_with_qsub_0_in_QPR_8Bits), ARM::DQuad_with_qsub_0_in_QPR_8RegClassID, 32, 1, true },
2726  { DQuad_with_qsub_1_in_QPR_8, DQuad_with_qsub_1_in_QPR_8Bits, 1224, 3, sizeof(DQuad_with_qsub_1_in_QPR_8Bits), ARM::DQuad_with_qsub_1_in_QPR_8RegClassID, 32, 1, true },
2727  { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, 1251, 3, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID, 32, 1, true },
2728  { DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1987, 2, sizeof(DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 32, 1, true },
2729  { QQQQPR, QQQQPRBits, 1656, 13, sizeof(QQQQPRBits), ARM::QQQQPRRegClassID, 64, 1, true },
2730  { QQQQPR_with_ssub_0, QQQQPR_with_ssub_0Bits, 0, 8, sizeof(QQQQPR_with_ssub_0Bits), ARM::QQQQPR_with_ssub_0RegClassID, 64, 1, true },
2731  { QQQQPR_with_ssub_4, QQQQPR_with_ssub_4Bits, 421, 7, sizeof(QQQQPR_with_ssub_4Bits), ARM::QQQQPR_with_ssub_4RegClassID, 64, 1, true },
2732  { QQQQPR_with_ssub_8, QQQQPR_with_ssub_8Bits, 1355, 6, sizeof(QQQQPR_with_ssub_8Bits), ARM::QQQQPR_with_ssub_8RegClassID, 64, 1, true },
2733  { QQQQPR_with_ssub_12, QQQQPR_with_ssub_12Bits, 140, 5, sizeof(QQQQPR_with_ssub_12Bits), ARM::QQQQPR_with_ssub_12RegClassID, 64, 1, true },
2734  { QQQQPR_with_dsub_0_in_DPR_8, QQQQPR_with_dsub_0_in_DPR_8Bits, 561, 4, sizeof(QQQQPR_with_dsub_0_in_DPR_8Bits), ARM::QQQQPR_with_dsub_0_in_DPR_8RegClassID, 64, 1, true },
2735  { QQQQPR_with_dsub_2_in_DPR_8, QQQQPR_with_dsub_2_in_DPR_8Bits, 847, 3, sizeof(QQQQPR_with_dsub_2_in_DPR_8Bits), ARM::QQQQPR_with_dsub_2_in_DPR_8RegClassID, 64, 1, true },
2736  { QQQQPR_with_dsub_4_in_DPR_8, QQQQPR_with_dsub_4_in_DPR_8Bits, 1050, 2, sizeof(QQQQPR_with_dsub_4_in_DPR_8Bits), ARM::QQQQPR_with_dsub_4_in_DPR_8RegClassID, 64, 1, true },
2737  { QQQQPR_with_dsub_6_in_DPR_8, QQQQPR_with_dsub_6_in_DPR_8Bits, 1140, 1, sizeof(QQQQPR_with_dsub_6_in_DPR_8Bits), ARM::QQQQPR_with_dsub_6_in_DPR_8RegClassID, 64, 1, true },
2738};
2739
2740// ARM Dwarf<->LLVM register mappings.
2741extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0Dwarf2L[] = {
2742  { 0U, ARM::R0 },
2743  { 1U, ARM::R1 },
2744  { 2U, ARM::R2 },
2745  { 3U, ARM::R3 },
2746  { 4U, ARM::R4 },
2747  { 5U, ARM::R5 },
2748  { 6U, ARM::R6 },
2749  { 7U, ARM::R7 },
2750  { 8U, ARM::R8 },
2751  { 9U, ARM::R9 },
2752  { 10U, ARM::R10 },
2753  { 11U, ARM::R11 },
2754  { 12U, ARM::R12 },
2755  { 13U, ARM::SP },
2756  { 14U, ARM::LR },
2757  { 15U, ARM::PC },
2758  { 256U, ARM::D0 },
2759  { 257U, ARM::D1 },
2760  { 258U, ARM::D2 },
2761  { 259U, ARM::D3 },
2762  { 260U, ARM::D4 },
2763  { 261U, ARM::D5 },
2764  { 262U, ARM::D6 },
2765  { 263U, ARM::D7 },
2766  { 264U, ARM::D8 },
2767  { 265U, ARM::D9 },
2768  { 266U, ARM::D10 },
2769  { 267U, ARM::D11 },
2770  { 268U, ARM::D12 },
2771  { 269U, ARM::D13 },
2772  { 270U, ARM::D14 },
2773  { 271U, ARM::D15 },
2774  { 272U, ARM::D16 },
2775  { 273U, ARM::D17 },
2776  { 274U, ARM::D18 },
2777  { 275U, ARM::D19 },
2778  { 276U, ARM::D20 },
2779  { 277U, ARM::D21 },
2780  { 278U, ARM::D22 },
2781  { 279U, ARM::D23 },
2782  { 280U, ARM::D24 },
2783  { 281U, ARM::D25 },
2784  { 282U, ARM::D26 },
2785  { 283U, ARM::D27 },
2786  { 284U, ARM::D28 },
2787  { 285U, ARM::D29 },
2788  { 286U, ARM::D30 },
2789  { 287U, ARM::D31 },
2790};
2791extern const unsigned ARMDwarfFlavour0Dwarf2LSize = array_lengthof(ARMDwarfFlavour0Dwarf2L);
2792
2793extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0Dwarf2L[] = {
2794  { 0U, ARM::R0 },
2795  { 1U, ARM::R1 },
2796  { 2U, ARM::R2 },
2797  { 3U, ARM::R3 },
2798  { 4U, ARM::R4 },
2799  { 5U, ARM::R5 },
2800  { 6U, ARM::R6 },
2801  { 7U, ARM::R7 },
2802  { 8U, ARM::R8 },
2803  { 9U, ARM::R9 },
2804  { 10U, ARM::R10 },
2805  { 11U, ARM::R11 },
2806  { 12U, ARM::R12 },
2807  { 13U, ARM::SP },
2808  { 14U, ARM::LR },
2809  { 15U, ARM::PC },
2810  { 256U, ARM::D0 },
2811  { 257U, ARM::D1 },
2812  { 258U, ARM::D2 },
2813  { 259U, ARM::D3 },
2814  { 260U, ARM::D4 },
2815  { 261U, ARM::D5 },
2816  { 262U, ARM::D6 },
2817  { 263U, ARM::D7 },
2818  { 264U, ARM::D8 },
2819  { 265U, ARM::D9 },
2820  { 266U, ARM::D10 },
2821  { 267U, ARM::D11 },
2822  { 268U, ARM::D12 },
2823  { 269U, ARM::D13 },
2824  { 270U, ARM::D14 },
2825  { 271U, ARM::D15 },
2826  { 272U, ARM::D16 },
2827  { 273U, ARM::D17 },
2828  { 274U, ARM::D18 },
2829  { 275U, ARM::D19 },
2830  { 276U, ARM::D20 },
2831  { 277U, ARM::D21 },
2832  { 278U, ARM::D22 },
2833  { 279U, ARM::D23 },
2834  { 280U, ARM::D24 },
2835  { 281U, ARM::D25 },
2836  { 282U, ARM::D26 },
2837  { 283U, ARM::D27 },
2838  { 284U, ARM::D28 },
2839  { 285U, ARM::D29 },
2840  { 286U, ARM::D30 },
2841  { 287U, ARM::D31 },
2842};
2843extern const unsigned ARMEHFlavour0Dwarf2LSize = array_lengthof(ARMEHFlavour0Dwarf2L);
2844
2845extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0L2Dwarf[] = {
2846  { ARM::LR, 14U },
2847  { ARM::PC, 15U },
2848  { ARM::SP, 13U },
2849  { ARM::D0, 256U },
2850  { ARM::D1, 257U },
2851  { ARM::D2, 258U },
2852  { ARM::D3, 259U },
2853  { ARM::D4, 260U },
2854  { ARM::D5, 261U },
2855  { ARM::D6, 262U },
2856  { ARM::D7, 263U },
2857  { ARM::D8, 264U },
2858  { ARM::D9, 265U },
2859  { ARM::D10, 266U },
2860  { ARM::D11, 267U },
2861  { ARM::D12, 268U },
2862  { ARM::D13, 269U },
2863  { ARM::D14, 270U },
2864  { ARM::D15, 271U },
2865  { ARM::D16, 272U },
2866  { ARM::D17, 273U },
2867  { ARM::D18, 274U },
2868  { ARM::D19, 275U },
2869  { ARM::D20, 276U },
2870  { ARM::D21, 277U },
2871  { ARM::D22, 278U },
2872  { ARM::D23, 279U },
2873  { ARM::D24, 280U },
2874  { ARM::D25, 281U },
2875  { ARM::D26, 282U },
2876  { ARM::D27, 283U },
2877  { ARM::D28, 284U },
2878  { ARM::D29, 285U },
2879  { ARM::D30, 286U },
2880  { ARM::D31, 287U },
2881  { ARM::R0, 0U },
2882  { ARM::R1, 1U },
2883  { ARM::R2, 2U },
2884  { ARM::R3, 3U },
2885  { ARM::R4, 4U },
2886  { ARM::R5, 5U },
2887  { ARM::R6, 6U },
2888  { ARM::R7, 7U },
2889  { ARM::R8, 8U },
2890  { ARM::R9, 9U },
2891  { ARM::R10, 10U },
2892  { ARM::R11, 11U },
2893  { ARM::R12, 12U },
2894};
2895extern const unsigned ARMDwarfFlavour0L2DwarfSize = array_lengthof(ARMDwarfFlavour0L2Dwarf);
2896
2897extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0L2Dwarf[] = {
2898  { ARM::LR, 14U },
2899  { ARM::PC, 15U },
2900  { ARM::SP, 13U },
2901  { ARM::D0, 256U },
2902  { ARM::D1, 257U },
2903  { ARM::D2, 258U },
2904  { ARM::D3, 259U },
2905  { ARM::D4, 260U },
2906  { ARM::D5, 261U },
2907  { ARM::D6, 262U },
2908  { ARM::D7, 263U },
2909  { ARM::D8, 264U },
2910  { ARM::D9, 265U },
2911  { ARM::D10, 266U },
2912  { ARM::D11, 267U },
2913  { ARM::D12, 268U },
2914  { ARM::D13, 269U },
2915  { ARM::D14, 270U },
2916  { ARM::D15, 271U },
2917  { ARM::D16, 272U },
2918  { ARM::D17, 273U },
2919  { ARM::D18, 274U },
2920  { ARM::D19, 275U },
2921  { ARM::D20, 276U },
2922  { ARM::D21, 277U },
2923  { ARM::D22, 278U },
2924  { ARM::D23, 279U },
2925  { ARM::D24, 280U },
2926  { ARM::D25, 281U },
2927  { ARM::D26, 282U },
2928  { ARM::D27, 283U },
2929  { ARM::D28, 284U },
2930  { ARM::D29, 285U },
2931  { ARM::D30, 286U },
2932  { ARM::D31, 287U },
2933  { ARM::R0, 0U },
2934  { ARM::R1, 1U },
2935  { ARM::R2, 2U },
2936  { ARM::R3, 3U },
2937  { ARM::R4, 4U },
2938  { ARM::R5, 5U },
2939  { ARM::R6, 6U },
2940  { ARM::R7, 7U },
2941  { ARM::R8, 8U },
2942  { ARM::R9, 9U },
2943  { ARM::R10, 10U },
2944  { ARM::R11, 11U },
2945  { ARM::R12, 12U },
2946};
2947extern const unsigned ARMEHFlavour0L2DwarfSize = array_lengthof(ARMEHFlavour0L2Dwarf);
2948
2949extern const uint16_t ARMRegEncodingTable[] = {
2950  0,
2951  1,
2952  15,
2953  0,
2954  8,
2955  9,
2956  3,
2957  3,
2958  0,
2959  4,
2960  14,
2961  15,
2962  13,
2963  2,
2964  0,
2965  1,
2966  2,
2967  3,
2968  4,
2969  5,
2970  6,
2971  7,
2972  8,
2973  9,
2974  10,
2975  11,
2976  12,
2977  13,
2978  14,
2979  15,
2980  16,
2981  17,
2982  18,
2983  19,
2984  20,
2985  21,
2986  22,
2987  23,
2988  24,
2989  25,
2990  26,
2991  27,
2992  28,
2993  29,
2994  30,
2995  31,
2996  10,
2997  7,
2998  6,
2999  5,
3000  0,
3001  1,
3002  2,
3003  3,
3004  4,
3005  5,
3006  6,
3007  7,
3008  8,
3009  9,
3010  10,
3011  11,
3012  12,
3013  13,
3014  14,
3015  15,
3016  0,
3017  1,
3018  2,
3019  3,
3020  4,
3021  5,
3022  6,
3023  7,
3024  8,
3025  9,
3026  10,
3027  11,
3028  12,
3029  0,
3030  1,
3031  2,
3032  3,
3033  4,
3034  5,
3035  6,
3036  7,
3037  8,
3038  9,
3039  10,
3040  11,
3041  12,
3042  13,
3043  14,
3044  15,
3045  16,
3046  17,
3047  18,
3048  19,
3049  20,
3050  21,
3051  22,
3052  23,
3053  24,
3054  25,
3055  26,
3056  27,
3057  28,
3058  29,
3059  30,
3060  31,
3061  0,
3062  1,
3063  2,
3064  3,
3065  4,
3066  5,
3067  6,
3068  7,
3069  8,
3070  9,
3071  10,
3072  11,
3073  12,
3074  13,
3075  14,
3076  15,
3077  16,
3078  17,
3079  18,
3080  19,
3081  20,
3082  21,
3083  22,
3084  23,
3085  24,
3086  25,
3087  26,
3088  27,
3089  28,
3090  29,
3091  0,
3092  1,
3093  2,
3094  3,
3095  4,
3096  5,
3097  6,
3098  7,
3099  8,
3100  9,
3101  10,
3102  11,
3103  12,
3104  13,
3105  14,
3106  0,
3107  1,
3108  2,
3109  3,
3110  4,
3111  5,
3112  6,
3113  7,
3114  8,
3115  9,
3116  10,
3117  11,
3118  12,
3119  12,
3120  0,
3121  2,
3122  4,
3123  6,
3124  8,
3125  10,
3126  0,
3127  1,
3128  2,
3129  3,
3130  4,
3131  5,
3132  6,
3133  7,
3134  8,
3135  9,
3136  10,
3137  11,
3138  12,
3139  13,
3140  14,
3141  15,
3142  16,
3143  17,
3144  18,
3145  19,
3146  20,
3147  21,
3148  22,
3149  23,
3150  24,
3151  25,
3152  26,
3153  27,
3154  28,
3155  29,
3156  0,
3157  1,
3158  2,
3159  3,
3160  4,
3161  5,
3162  6,
3163  7,
3164  8,
3165  9,
3166  10,
3167  11,
3168  12,
3169  13,
3170  14,
3171  15,
3172  16,
3173  17,
3174  18,
3175  19,
3176  20,
3177  21,
3178  22,
3179  23,
3180  24,
3181  25,
3182  26,
3183  27,
3184  0,
3185  1,
3186  2,
3187  3,
3188  4,
3189  5,
3190  6,
3191  7,
3192  8,
3193  9,
3194  10,
3195  11,
3196  12,
3197  13,
3198  14,
3199  15,
3200  16,
3201  17,
3202  18,
3203  19,
3204  20,
3205  21,
3206  22,
3207  23,
3208  24,
3209  25,
3210  1,
3211  3,
3212  5,
3213  7,
3214  9,
3215  11,
3216  13,
3217  15,
3218  17,
3219  19,
3220  21,
3221  23,
3222  25,
3223  27,
3224  29,
3225  1,
3226  3,
3227  5,
3228  7,
3229  9,
3230  11,
3231  13,
3232  15,
3233  17,
3234  19,
3235  21,
3236  23,
3237  25,
3238  27,
3239};
3240static inline void InitARMMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
3241  RI->InitMCRegisterInfo(ARMRegDesc, 289, RA, PC, ARMMCRegisterClasses, 103, ARMRegUnitRoots, 77, ARMRegDiffLists, ARMLaneMaskLists, ARMRegStrings, ARMRegClassStrings, ARMSubRegIdxLists, 57,
3242ARMSubRegIdxRanges, ARMRegEncodingTable);
3243
3244  switch (DwarfFlavour) {
3245  default:
3246    llvm_unreachable("Unknown DWARF flavour");
3247  case 0:
3248    RI->mapDwarfRegsToLLVMRegs(ARMDwarfFlavour0Dwarf2L, ARMDwarfFlavour0Dwarf2LSize, false);
3249    break;
3250  }
3251  switch (EHFlavour) {
3252  default:
3253    llvm_unreachable("Unknown DWARF flavour");
3254  case 0:
3255    RI->mapDwarfRegsToLLVMRegs(ARMEHFlavour0Dwarf2L, ARMEHFlavour0Dwarf2LSize, true);
3256    break;
3257  }
3258  switch (DwarfFlavour) {
3259  default:
3260    llvm_unreachable("Unknown DWARF flavour");
3261  case 0:
3262    RI->mapLLVMRegsToDwarfRegs(ARMDwarfFlavour0L2Dwarf, ARMDwarfFlavour0L2DwarfSize, false);
3263    break;
3264  }
3265  switch (EHFlavour) {
3266  default:
3267    llvm_unreachable("Unknown DWARF flavour");
3268  case 0:
3269    RI->mapLLVMRegsToDwarfRegs(ARMEHFlavour0L2Dwarf, ARMEHFlavour0L2DwarfSize, true);
3270    break;
3271  }
3272}
3273
3274} // end namespace llvm
3275
3276#endif // GET_REGINFO_MC_DESC
3277
3278/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3279|*                                                                            *|
3280|* Register Information Header Fragment                                       *|
3281|*                                                                            *|
3282|* Automatically generated file, do not edit!                                 *|
3283|*                                                                            *|
3284\*===----------------------------------------------------------------------===*/
3285
3286
3287#ifdef GET_REGINFO_HEADER
3288#undef GET_REGINFO_HEADER
3289
3290#include "llvm/CodeGen/TargetRegisterInfo.h"
3291
3292namespace llvm {
3293
3294class ARMFrameLowering;
3295
3296struct ARMGenRegisterInfo : public TargetRegisterInfo {
3297  explicit ARMGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
3298      unsigned PC = 0, unsigned HwMode = 0);
3299  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
3300  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3301  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3302  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
3303  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
3304  unsigned getRegUnitWeight(unsigned RegUnit) const override;
3305  unsigned getNumRegPressureSets() const override;
3306  const char *getRegPressureSetName(unsigned Idx) const override;
3307  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
3308  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
3309  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
3310  ArrayRef<const char *> getRegMaskNames() const override;
3311  ArrayRef<const uint32_t *> getRegMasks() const override;
3312  /// Devirtualized TargetFrameLowering.
3313  static const ARMFrameLowering *getFrameLowering(
3314      const MachineFunction &MF);
3315};
3316
3317namespace ARM { // Register classes
3318  extern const TargetRegisterClass HPRRegClass;
3319  extern const TargetRegisterClass SPRRegClass;
3320  extern const TargetRegisterClass GPRRegClass;
3321  extern const TargetRegisterClass GPRwithAPSRRegClass;
3322  extern const TargetRegisterClass SPR_8RegClass;
3323  extern const TargetRegisterClass GPRnopcRegClass;
3324  extern const TargetRegisterClass rGPRRegClass;
3325  extern const TargetRegisterClass tGPRwithpcRegClass;
3326  extern const TargetRegisterClass hGPRRegClass;
3327  extern const TargetRegisterClass tGPRRegClass;
3328  extern const TargetRegisterClass GPRnopc_and_hGPRRegClass;
3329  extern const TargetRegisterClass hGPR_and_rGPRRegClass;
3330  extern const TargetRegisterClass tcGPRRegClass;
3331  extern const TargetRegisterClass tGPR_and_tcGPRRegClass;
3332  extern const TargetRegisterClass CCRRegClass;
3333  extern const TargetRegisterClass GPRspRegClass;
3334  extern const TargetRegisterClass hGPR_and_tGPRwithpcRegClass;
3335  extern const TargetRegisterClass hGPR_and_tcGPRRegClass;
3336  extern const TargetRegisterClass DPRRegClass;
3337  extern const TargetRegisterClass DPR_VFP2RegClass;
3338  extern const TargetRegisterClass DPR_8RegClass;
3339  extern const TargetRegisterClass GPRPairRegClass;
3340  extern const TargetRegisterClass GPRPair_with_gsub_1_in_rGPRRegClass;
3341  extern const TargetRegisterClass GPRPair_with_gsub_0_in_tGPRRegClass;
3342  extern const TargetRegisterClass GPRPair_with_gsub_0_in_hGPRRegClass;
3343  extern const TargetRegisterClass GPRPair_with_gsub_0_in_tcGPRRegClass;
3344  extern const TargetRegisterClass GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClass;
3345  extern const TargetRegisterClass GPRPair_with_gsub_1_in_tcGPRRegClass;
3346  extern const TargetRegisterClass GPRPair_with_gsub_1_in_GPRspRegClass;
3347  extern const TargetRegisterClass DPairSpcRegClass;
3348  extern const TargetRegisterClass DPairSpc_with_ssub_0RegClass;
3349  extern const TargetRegisterClass DPairSpc_with_ssub_4RegClass;
3350  extern const TargetRegisterClass DPairSpc_with_dsub_0_in_DPR_8RegClass;
3351  extern const TargetRegisterClass DPairSpc_with_dsub_2_in_DPR_8RegClass;
3352  extern const TargetRegisterClass DPairRegClass;
3353  extern const TargetRegisterClass DPair_with_ssub_0RegClass;
3354  extern const TargetRegisterClass QPRRegClass;
3355  extern const TargetRegisterClass DPair_with_ssub_2RegClass;
3356  extern const TargetRegisterClass DPair_with_dsub_0_in_DPR_8RegClass;
3357  extern const TargetRegisterClass QPR_VFP2RegClass;
3358  extern const TargetRegisterClass DPair_with_dsub_1_in_DPR_8RegClass;
3359  extern const TargetRegisterClass QPR_8RegClass;
3360  extern const TargetRegisterClass DTripleRegClass;
3361  extern const TargetRegisterClass DTripleSpcRegClass;
3362  extern const TargetRegisterClass DTripleSpc_with_ssub_0RegClass;
3363  extern const TargetRegisterClass DTriple_with_ssub_0RegClass;
3364  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPRRegClass;
3365  extern const TargetRegisterClass DTriple_with_ssub_2RegClass;
3366  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3367  extern const TargetRegisterClass DTripleSpc_with_ssub_4RegClass;
3368  extern const TargetRegisterClass DTriple_with_ssub_4RegClass;
3369  extern const TargetRegisterClass DTripleSpc_with_ssub_8RegClass;
3370  extern const TargetRegisterClass DTripleSpc_with_dsub_0_in_DPR_8RegClass;
3371  extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8RegClass;
3372  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_VFP2RegClass;
3373  extern const TargetRegisterClass DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3374  extern const TargetRegisterClass DTriple_with_dsub_1_in_DPR_8RegClass;
3375  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass;
3376  extern const TargetRegisterClass DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass;
3377  extern const TargetRegisterClass DTripleSpc_with_dsub_2_in_DPR_8RegClass;
3378  extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8RegClass;
3379  extern const TargetRegisterClass DTripleSpc_with_dsub_4_in_DPR_8RegClass;
3380  extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3381  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_8RegClass;
3382  extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClass;
3383  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass;
3384  extern const TargetRegisterClass DQuadSpcRegClass;
3385  extern const TargetRegisterClass DQuadSpc_with_ssub_0RegClass;
3386  extern const TargetRegisterClass DQuadSpc_with_ssub_4RegClass;
3387  extern const TargetRegisterClass DQuadSpc_with_ssub_8RegClass;
3388  extern const TargetRegisterClass DQuadSpc_with_dsub_0_in_DPR_8RegClass;
3389  extern const TargetRegisterClass DQuadSpc_with_dsub_2_in_DPR_8RegClass;
3390  extern const TargetRegisterClass DQuadSpc_with_dsub_4_in_DPR_8RegClass;
3391  extern const TargetRegisterClass DQuadRegClass;
3392  extern const TargetRegisterClass DQuad_with_ssub_0RegClass;
3393  extern const TargetRegisterClass DQuad_with_ssub_2RegClass;
3394  extern const TargetRegisterClass QQPRRegClass;
3395  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3396  extern const TargetRegisterClass DQuad_with_ssub_4RegClass;
3397  extern const TargetRegisterClass DQuad_with_ssub_6RegClass;
3398  extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8RegClass;
3399  extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_VFP2RegClass;
3400  extern const TargetRegisterClass DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3401  extern const TargetRegisterClass DQuad_with_dsub_1_in_DPR_8RegClass;
3402  extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_VFP2RegClass;
3403  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass;
3404  extern const TargetRegisterClass DQuad_with_dsub_2_in_DPR_8RegClass;
3405  extern const TargetRegisterClass DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3406  extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8RegClass;
3407  extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3408  extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_8RegClass;
3409  extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_8RegClass;
3410  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass;
3411  extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3412  extern const TargetRegisterClass QQQQPRRegClass;
3413  extern const TargetRegisterClass QQQQPR_with_ssub_0RegClass;
3414  extern const TargetRegisterClass QQQQPR_with_ssub_4RegClass;
3415  extern const TargetRegisterClass QQQQPR_with_ssub_8RegClass;
3416  extern const TargetRegisterClass QQQQPR_with_ssub_12RegClass;
3417  extern const TargetRegisterClass QQQQPR_with_dsub_0_in_DPR_8RegClass;
3418  extern const TargetRegisterClass QQQQPR_with_dsub_2_in_DPR_8RegClass;
3419  extern const TargetRegisterClass QQQQPR_with_dsub_4_in_DPR_8RegClass;
3420  extern const TargetRegisterClass QQQQPR_with_dsub_6_in_DPR_8RegClass;
3421} // end namespace ARM
3422
3423} // end namespace llvm
3424
3425#endif // GET_REGINFO_HEADER
3426
3427/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3428|*                                                                            *|
3429|* Target Register and Register Classes Information                           *|
3430|*                                                                            *|
3431|* Automatically generated file, do not edit!                                 *|
3432|*                                                                            *|
3433\*===----------------------------------------------------------------------===*/
3434
3435
3436#ifdef GET_REGINFO_TARGET_DESC
3437#undef GET_REGINFO_TARGET_DESC
3438
3439namespace llvm {
3440
3441extern const MCRegisterClass ARMMCRegisterClasses[];
3442
3443static const MVT::SimpleValueType VTLists[] = {
3444  /* 0 */ MVT::i32, MVT::Other,
3445  /* 2 */ MVT::f16, MVT::Other,
3446  /* 4 */ MVT::f32, MVT::Other,
3447  /* 6 */ MVT::v2i64, MVT::Other,
3448  /* 8 */ MVT::v4i64, MVT::Other,
3449  /* 10 */ MVT::v8i64, MVT::Other,
3450  /* 12 */ MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64, MVT::v2f32, MVT::v4f16, MVT::Other,
3451  /* 20 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::Other,
3452  /* 28 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other,
3453  /* 35 */ MVT::Untyped, MVT::Other,
3454};
3455
3456static const char *const SubRegIndexNameTable[] = { "dsub_0", "dsub_1", "dsub_2", "dsub_3", "dsub_4", "dsub_5", "dsub_6", "dsub_7", "gsub_0", "gsub_1", "qqsub_0", "qqsub_1", "qsub_0", "qsub_1", "qsub_2", "qsub_3", "ssub_0", "ssub_1", "ssub_2", "ssub_3", "ssub_4", "ssub_5", "ssub_6", "ssub_7", "ssub_8", "ssub_9", "ssub_10", "ssub_11", "ssub_12", "ssub_13", "dsub_7_then_ssub_0", "dsub_7_then_ssub_1", "ssub_0_ssub_1_ssub_4_ssub_5", "ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5", "ssub_2_ssub_3_ssub_6_ssub_7", "ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7", "ssub_2_ssub_3_ssub_4_ssub_5", "ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9", "ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13", "ssub_2_ssub_3_ssub_6_ssub_7_dsub_5", "ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7", "ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13", "ssub_6_ssub_7_dsub_5", "ssub_6_ssub_7_ssub_8_ssub_9_dsub_5", "ssub_6_ssub_7_dsub_5_dsub_7", "ssub_6_ssub_7_ssub_8_ssub_9", "ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13", "ssub_8_ssub_9_ssub_12_ssub_13", "ssub_8_ssub_9_dsub_5_ssub_12_ssub_13", "dsub_5_dsub_7", "dsub_5_ssub_12_ssub_13_dsub_7", "dsub_5_ssub_12_ssub_13", "ssub_4_ssub_5_ssub_6_ssub_7_qsub_2", "" };
3457
3458
3459static const LaneBitmask SubRegIndexLaneMaskTable[] = {
3460  LaneBitmask::getAll(),
3461  LaneBitmask(0x0000000C), // dsub_0
3462  LaneBitmask(0x00000030), // dsub_1
3463  LaneBitmask(0x000000C0), // dsub_2
3464  LaneBitmask(0x00000300), // dsub_3
3465  LaneBitmask(0x00000C00), // dsub_4
3466  LaneBitmask(0x00003000), // dsub_5
3467  LaneBitmask(0x0000C000), // dsub_6
3468  LaneBitmask(0x00030000), // dsub_7
3469  LaneBitmask(0x00000001), // gsub_0
3470  LaneBitmask(0x00000002), // gsub_1
3471  LaneBitmask(0x000003FC), // qqsub_0
3472  LaneBitmask(0x0003FC00), // qqsub_1
3473  LaneBitmask(0x0000003C), // qsub_0
3474  LaneBitmask(0x000003C0), // qsub_1
3475  LaneBitmask(0x00003C00), // qsub_2
3476  LaneBitmask(0x0003C000), // qsub_3
3477  LaneBitmask(0x00000004), // ssub_0
3478  LaneBitmask(0x00000008), // ssub_1
3479  LaneBitmask(0x00000010), // ssub_2
3480  LaneBitmask(0x00000020), // ssub_3
3481  LaneBitmask(0x00000040), // ssub_4
3482  LaneBitmask(0x00000080), // ssub_5
3483  LaneBitmask(0x00000100), // ssub_6
3484  LaneBitmask(0x00000200), // ssub_7
3485  LaneBitmask(0x00000400), // ssub_8
3486  LaneBitmask(0x00000800), // ssub_9
3487  LaneBitmask(0x00001000), // ssub_10
3488  LaneBitmask(0x00002000), // ssub_11
3489  LaneBitmask(0x00004000), // ssub_12
3490  LaneBitmask(0x00008000), // ssub_13
3491  LaneBitmask(0x00010000), // dsub_7_then_ssub_0
3492  LaneBitmask(0x00020000), // dsub_7_then_ssub_1
3493  LaneBitmask(0x000000CC), // ssub_0_ssub_1_ssub_4_ssub_5
3494  LaneBitmask(0x000000FC), // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
3495  LaneBitmask(0x00000330), // ssub_2_ssub_3_ssub_6_ssub_7
3496  LaneBitmask(0x000003F0), // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
3497  LaneBitmask(0x000000F0), // ssub_2_ssub_3_ssub_4_ssub_5
3498  LaneBitmask(0x00000CCC), // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
3499  LaneBitmask(0x0000CCCC), // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
3500  LaneBitmask(0x00003330), // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
3501  LaneBitmask(0x00033330), // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
3502  LaneBitmask(0x00000FF0), // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
3503  LaneBitmask(0x00000CC0), // ssub_4_ssub_5_ssub_8_ssub_9
3504  LaneBitmask(0x00000FC0), // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
3505  LaneBitmask(0x0000CCC0), // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
3506  LaneBitmask(0x00003300), // ssub_6_ssub_7_dsub_5
3507  LaneBitmask(0x00003F00), // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
3508  LaneBitmask(0x00033300), // ssub_6_ssub_7_dsub_5_dsub_7
3509  LaneBitmask(0x00000F00), // ssub_6_ssub_7_ssub_8_ssub_9
3510  LaneBitmask(0x0000FF00), // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
3511  LaneBitmask(0x0000CC00), // ssub_8_ssub_9_ssub_12_ssub_13
3512  LaneBitmask(0x0000FC00), // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
3513  LaneBitmask(0x00033000), // dsub_5_dsub_7
3514  LaneBitmask(0x0003F000), // dsub_5_ssub_12_ssub_13_dsub_7
3515  LaneBitmask(0x0000F000), // dsub_5_ssub_12_ssub_13
3516  LaneBitmask(0x00003FC0), // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
3517 };
3518
3519
3520
3521static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
3522  // Mode = 0 (Default)
3523  { 16, 16, 32, VTLists+2 },    // HPR
3524  { 32, 32, 32, VTLists+4 },    // SPR
3525  { 32, 32, 32, VTLists+0 },    // GPR
3526  { 32, 32, 32, VTLists+0 },    // GPRwithAPSR
3527  { 32, 32, 32, VTLists+4 },    // SPR_8
3528  { 32, 32, 32, VTLists+0 },    // GPRnopc
3529  { 32, 32, 32, VTLists+0 },    // rGPR
3530  { 32, 32, 32, VTLists+0 },    // tGPRwithpc
3531  { 32, 32, 32, VTLists+0 },    // hGPR
3532  { 32, 32, 32, VTLists+0 },    // tGPR
3533  { 32, 32, 32, VTLists+0 },    // GPRnopc_and_hGPR
3534  { 32, 32, 32, VTLists+0 },    // hGPR_and_rGPR
3535  { 32, 32, 32, VTLists+0 },    // tcGPR
3536  { 32, 32, 32, VTLists+0 },    // tGPR_and_tcGPR
3537  { 32, 32, 32, VTLists+0 },    // CCR
3538  { 32, 32, 32, VTLists+0 },    // GPRsp
3539  { 32, 32, 32, VTLists+0 },    // hGPR_and_tGPRwithpc
3540  { 32, 32, 32, VTLists+0 },    // hGPR_and_tcGPR
3541  { 64, 64, 64, VTLists+12 },    // DPR
3542  { 64, 64, 64, VTLists+12 },    // DPR_VFP2
3543  { 64, 64, 64, VTLists+12 },    // DPR_8
3544  { 64, 64, 64, VTLists+35 },    // GPRPair
3545  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_1_in_rGPR
3546  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_0_in_tGPR
3547  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_0_in_hGPR
3548  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_0_in_tcGPR
3549  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_1_in_hGPR_and_rGPR
3550  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_1_in_tcGPR
3551  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_1_in_GPRsp
3552  { 128, 128, 64, VTLists+6 },    // DPairSpc
3553  { 128, 128, 64, VTLists+6 },    // DPairSpc_with_ssub_0
3554  { 128, 128, 64, VTLists+6 },    // DPairSpc_with_ssub_4
3555  { 128, 128, 64, VTLists+6 },    // DPairSpc_with_dsub_0_in_DPR_8
3556  { 128, 128, 64, VTLists+6 },    // DPairSpc_with_dsub_2_in_DPR_8
3557  { 128, 128, 128, VTLists+28 },    // DPair
3558  { 128, 128, 128, VTLists+28 },    // DPair_with_ssub_0
3559  { 128, 128, 128, VTLists+20 },    // QPR
3560  { 128, 128, 128, VTLists+28 },    // DPair_with_ssub_2
3561  { 128, 128, 128, VTLists+28 },    // DPair_with_dsub_0_in_DPR_8
3562  { 128, 128, 128, VTLists+28 },    // QPR_VFP2
3563  { 128, 128, 128, VTLists+28 },    // DPair_with_dsub_1_in_DPR_8
3564  { 128, 128, 128, VTLists+28 },    // QPR_8
3565  { 192, 192, 64, VTLists+35 },    // DTriple
3566  { 192, 192, 64, VTLists+35 },    // DTripleSpc
3567  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_ssub_0
3568  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_0
3569  { 192, 192, 64, VTLists+35 },    // DTriple_with_qsub_0_in_QPR
3570  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_2
3571  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3572  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_ssub_4
3573  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_4
3574  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_ssub_8
3575  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_dsub_0_in_DPR_8
3576  { 192, 192, 64, VTLists+35 },    // DTriple_with_dsub_0_in_DPR_8
3577  { 192, 192, 64, VTLists+35 },    // DTriple_with_qsub_0_in_QPR_VFP2
3578  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3579  { 192, 192, 64, VTLists+35 },    // DTriple_with_dsub_1_in_DPR_8
3580  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
3581  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
3582  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_dsub_2_in_DPR_8
3583  { 192, 192, 64, VTLists+35 },    // DTriple_with_dsub_2_in_DPR_8
3584  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_dsub_4_in_DPR_8
3585  { 192, 192, 64, VTLists+35 },    // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3586  { 192, 192, 64, VTLists+35 },    // DTriple_with_qsub_0_in_QPR_8
3587  { 192, 192, 64, VTLists+35 },    // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
3588  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
3589  { 256, 256, 64, VTLists+8 },    // DQuadSpc
3590  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_ssub_0
3591  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_ssub_4
3592  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_ssub_8
3593  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_dsub_0_in_DPR_8
3594  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_dsub_2_in_DPR_8
3595  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_dsub_4_in_DPR_8
3596  { 256, 256, 256, VTLists+8 },    // DQuad
3597  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_0
3598  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_2
3599  { 256, 256, 256, VTLists+8 },    // QQPR
3600  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3601  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_4
3602  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_6
3603  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_0_in_DPR_8
3604  { 256, 256, 256, VTLists+8 },    // DQuad_with_qsub_0_in_QPR_VFP2
3605  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3606  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_1_in_DPR_8
3607  { 256, 256, 256, VTLists+8 },    // DQuad_with_qsub_1_in_QPR_VFP2
3608  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
3609  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_2_in_DPR_8
3610  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3611  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_3_in_DPR_8
3612  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3613  { 256, 256, 256, VTLists+8 },    // DQuad_with_qsub_0_in_QPR_8
3614  { 256, 256, 256, VTLists+8 },    // DQuad_with_qsub_1_in_QPR_8
3615  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
3616  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3617  { 512, 512, 256, VTLists+10 },    // QQQQPR
3618  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_ssub_0
3619  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_ssub_4
3620  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_ssub_8
3621  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_ssub_12
3622  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_dsub_0_in_DPR_8
3623  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_dsub_2_in_DPR_8
3624  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_dsub_4_in_DPR_8
3625  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_dsub_6_in_DPR_8
3626};
3627
3628static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
3629
3630static const uint32_t HPRSubClassMask[] = {
3631  0x00000013, 0x00000000, 0x00000000, 0x00000000,
3632  0xc0180000, 0xfffeb3eb, 0xbfffcdfb, 0x0000007f, // ssub_0
3633  0xc0180000, 0xfffeb3eb, 0xbfffcdfb, 0x0000007f, // ssub_1
3634  0x00000000, 0xd76483e0, 0xbffbc803, 0x0000007f, // ssub_2
3635  0x00000000, 0xd76483e0, 0xbffbc803, 0x0000007f, // ssub_3
3636  0x80000000, 0xff3e0003, 0x3ff9c1f3, 0x0000007f, // ssub_4
3637  0x80000000, 0xff3e0003, 0x3ff9c1f3, 0x0000007f, // ssub_5
3638  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_6
3639  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_7
3640  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // ssub_8
3641  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // ssub_9
3642  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_10
3643  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_11
3644  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_12
3645  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_13
3646  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_7_then_ssub_0
3647  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_7_then_ssub_1
3648};
3649
3650static const uint32_t SPRSubClassMask[] = {
3651  0x00000012, 0x00000000, 0x00000000, 0x00000000,
3652  0xc0180000, 0xfffeb3eb, 0xbfffcdfb, 0x0000007f, // ssub_0
3653  0xc0180000, 0xfffeb3eb, 0xbfffcdfb, 0x0000007f, // ssub_1
3654  0x00000000, 0xd76483e0, 0xbffbc803, 0x0000007f, // ssub_2
3655  0x00000000, 0xd76483e0, 0xbffbc803, 0x0000007f, // ssub_3
3656  0x80000000, 0xff3e0003, 0x3ff9c1f3, 0x0000007f, // ssub_4
3657  0x80000000, 0xff3e0003, 0x3ff9c1f3, 0x0000007f, // ssub_5
3658  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_6
3659  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_7
3660  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // ssub_8
3661  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // ssub_9
3662  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_10
3663  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_11
3664  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_12
3665  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_13
3666  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_7_then_ssub_0
3667  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_7_then_ssub_1
3668};
3669
3670static const uint32_t GPRSubClassMask[] = {
3671  0x0003bfe4, 0x00000000, 0x00000000, 0x00000000,
3672  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3673  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3674};
3675
3676static const uint32_t GPRwithAPSRSubClassMask[] = {
3677  0x0002be68, 0x00000000, 0x00000000, 0x00000000,
3678  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3679  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3680};
3681
3682static const uint32_t SPR_8SubClassMask[] = {
3683  0x00000010, 0x00000000, 0x00000000, 0x00000000,
3684  0x00100000, 0xf9300343, 0x3f4901c3, 0x00000078, // ssub_0
3685  0x00100000, 0xf9300343, 0x3f4901c3, 0x00000078, // ssub_1
3686  0x00000000, 0x91000300, 0x3d480003, 0x00000078, // ssub_2
3687  0x00000000, 0x91000300, 0x3d480003, 0x00000078, // ssub_3
3688  0x00000000, 0x38000002, 0x39400183, 0x00000070, // ssub_4
3689  0x00000000, 0x38000002, 0x39400183, 0x00000070, // ssub_5
3690  0x00000000, 0x00000000, 0x29000000, 0x00000070, // ssub_6
3691  0x00000000, 0x00000000, 0x29000000, 0x00000070, // ssub_7
3692  0x00000000, 0x20000000, 0x00000100, 0x00000060, // ssub_8
3693  0x00000000, 0x20000000, 0x00000100, 0x00000060, // ssub_9
3694  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_10
3695  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_11
3696  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_12
3697  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_13
3698  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_7_then_ssub_0
3699  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_7_then_ssub_1
3700};
3701
3702static const uint32_t GPRnopcSubClassMask[] = {
3703  0x0002be60, 0x00000000, 0x00000000, 0x00000000,
3704  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3705  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3706};
3707
3708static const uint32_t rGPRSubClassMask[] = {
3709  0x00023a40, 0x00000000, 0x00000000, 0x00000000,
3710  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3711  0x0cc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3712};
3713
3714static const uint32_t tGPRwithpcSubClassMask[] = {
3715  0x00012280, 0x00000000, 0x00000000, 0x00000000,
3716  0x08800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3717  0x08800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3718};
3719
3720static const uint32_t hGPRSubClassMask[] = {
3721  0x00038d00, 0x00000000, 0x00000000, 0x00000000,
3722  0x15000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3723  0x15000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3724};
3725
3726static const uint32_t tGPRSubClassMask[] = {
3727  0x00002200, 0x00000000, 0x00000000, 0x00000000,
3728  0x08800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3729  0x08800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3730};
3731
3732static const uint32_t GPRnopc_and_hGPRSubClassMask[] = {
3733  0x00028c00, 0x00000000, 0x00000000, 0x00000000,
3734  0x15000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3735  0x15000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3736};
3737
3738static const uint32_t hGPR_and_rGPRSubClassMask[] = {
3739  0x00020800, 0x00000000, 0x00000000, 0x00000000,
3740  0x15000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3741  0x04000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3742};
3743
3744static const uint32_t tcGPRSubClassMask[] = {
3745  0x00023000, 0x00000000, 0x00000000, 0x00000000,
3746  0x1a000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3747  0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3748};
3749
3750static const uint32_t tGPR_and_tcGPRSubClassMask[] = {
3751  0x00002000, 0x00000000, 0x00000000, 0x00000000,
3752  0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3753  0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3754};
3755
3756static const uint32_t CCRSubClassMask[] = {
3757  0x00004000, 0x00000000, 0x00000000, 0x00000000,
3758};
3759
3760static const uint32_t GPRspSubClassMask[] = {
3761  0x00008000, 0x00000000, 0x00000000, 0x00000000,
3762  0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
3763};
3764
3765static const uint32_t hGPR_and_tGPRwithpcSubClassMask[] = {
3766  0x00010000, 0x00000000, 0x00000000, 0x00000000,
3767};
3768
3769static const uint32_t hGPR_and_tcGPRSubClassMask[] = {
3770  0x00020000, 0x00000000, 0x00000000, 0x00000000,
3771  0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
3772};
3773
3774static const uint32_t DPRSubClassMask[] = {
3775  0x001c0000, 0x00000000, 0x00000000, 0x00000000,
3776  0xe0000000, 0xffffffff, 0xffffffff, 0x0000007f, // dsub_0
3777  0x00000000, 0xd7e5e7fc, 0xfffffe03, 0x0000007f, // dsub_1
3778  0xe0000000, 0xfffffc03, 0xffffffff, 0x0000007f, // dsub_2
3779  0x00000000, 0x00000000, 0xfffffe00, 0x0000007f, // dsub_3
3780  0x00000000, 0x281a1800, 0xc00001fc, 0x0000007f, // dsub_4
3781  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_5
3782  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_6
3783  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_7
3784};
3785
3786static const uint32_t DPR_VFP2SubClassMask[] = {
3787  0x00180000, 0x00000000, 0x00000000, 0x00000000,
3788  0xc0000000, 0xfffeb3eb, 0xbfffcdfb, 0x0000007f, // dsub_0
3789  0x00000000, 0xd76483e0, 0xbffbc803, 0x0000007f, // dsub_1
3790  0x80000000, 0xff3e0003, 0x3ff9c1f3, 0x0000007f, // dsub_2
3791  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // dsub_3
3792  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // dsub_4
3793  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // dsub_5
3794  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_6
3795  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_7
3796};
3797
3798static const uint32_t DPR_8SubClassMask[] = {
3799  0x00100000, 0x00000000, 0x00000000, 0x00000000,
3800  0x00000000, 0xf9300343, 0x3f4901c3, 0x00000078, // dsub_0
3801  0x00000000, 0x91000300, 0x3d480003, 0x00000078, // dsub_1
3802  0x00000000, 0x38000002, 0x39400183, 0x00000070, // dsub_2
3803  0x00000000, 0x00000000, 0x29000000, 0x00000070, // dsub_3
3804  0x00000000, 0x20000000, 0x00000100, 0x00000060, // dsub_4
3805  0x00000000, 0x00000000, 0x00000000, 0x00000060, // dsub_5
3806  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_6
3807  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_7
3808};
3809
3810static const uint32_t GPRPairSubClassMask[] = {
3811  0x1fe00000, 0x00000000, 0x00000000, 0x00000000,
3812};
3813
3814static const uint32_t GPRPair_with_gsub_1_in_rGPRSubClassMask[] = {
3815  0x0cc00000, 0x00000000, 0x00000000, 0x00000000,
3816};
3817
3818static const uint32_t GPRPair_with_gsub_0_in_tGPRSubClassMask[] = {
3819  0x08800000, 0x00000000, 0x00000000, 0x00000000,
3820};
3821
3822static const uint32_t GPRPair_with_gsub_0_in_hGPRSubClassMask[] = {
3823  0x15000000, 0x00000000, 0x00000000, 0x00000000,
3824};
3825
3826static const uint32_t GPRPair_with_gsub_0_in_tcGPRSubClassMask[] = {
3827  0x1a000000, 0x00000000, 0x00000000, 0x00000000,
3828};
3829
3830static const uint32_t GPRPair_with_gsub_1_in_hGPR_and_rGPRSubClassMask[] = {
3831  0x04000000, 0x00000000, 0x00000000, 0x00000000,
3832};
3833
3834static const uint32_t GPRPair_with_gsub_1_in_tcGPRSubClassMask[] = {
3835  0x08000000, 0x00000000, 0x00000000, 0x00000000,
3836};
3837
3838static const uint32_t GPRPair_with_gsub_1_in_GPRspSubClassMask[] = {
3839  0x10000000, 0x00000000, 0x00000000, 0x00000000,
3840};
3841
3842static const uint32_t DPairSpcSubClassMask[] = {
3843  0xe0000000, 0x00000003, 0x00000000, 0x00000000,
3844  0x00000000, 0xfffffc00, 0xffffffff, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5
3845  0x00000000, 0x00000000, 0xfffffe00, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7
3846  0x00000000, 0x281a1800, 0xc00001fc, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9
3847  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_dsub_5
3848  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_8_ssub_9_ssub_12_ssub_13
3849  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_5_dsub_7
3850};
3851
3852static const uint32_t DPairSpc_with_ssub_0SubClassMask[] = {
3853  0xc0000000, 0x00000003, 0x00000000, 0x00000000,
3854  0x00000000, 0xfffeb000, 0xbfffcdfb, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5
3855  0x00000000, 0x00000000, 0xbffbc800, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7
3856  0x00000000, 0x281a0000, 0x000001f0, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9
3857  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_dsub_5
3858  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_8_ssub_9_ssub_12_ssub_13
3859  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // dsub_5_dsub_7
3860};
3861
3862static const uint32_t DPairSpc_with_ssub_4SubClassMask[] = {
3863  0x80000000, 0x00000003, 0x00000000, 0x00000000,
3864  0x00000000, 0xff3e0000, 0x3ff9c1f3, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5
3865  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7
3866  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // ssub_4_ssub_5_ssub_8_ssub_9
3867  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_dsub_5
3868  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_8_ssub_9_ssub_12_ssub_13
3869  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_5_dsub_7
3870};
3871
3872static const uint32_t DPairSpc_with_dsub_0_in_DPR_8SubClassMask[] = {
3873  0x00000000, 0x00000003, 0x00000000, 0x00000000,
3874  0x00000000, 0xf9300000, 0x3f4901c3, 0x00000078, // ssub_0_ssub_1_ssub_4_ssub_5
3875  0x00000000, 0x00000000, 0x3d480000, 0x00000078, // ssub_2_ssub_3_ssub_6_ssub_7
3876  0x00000000, 0x28000000, 0x00000180, 0x00000070, // ssub_4_ssub_5_ssub_8_ssub_9
3877  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_dsub_5
3878  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_8_ssub_9_ssub_12_ssub_13
3879  0x00000000, 0x00000000, 0x00000000, 0x00000060, // dsub_5_dsub_7
3880};
3881
3882static const uint32_t DPairSpc_with_dsub_2_in_DPR_8SubClassMask[] = {
3883  0x00000000, 0x00000002, 0x00000000, 0x00000000,
3884  0x00000000, 0x38000000, 0x39400183, 0x00000070, // ssub_0_ssub_1_ssub_4_ssub_5
3885  0x00000000, 0x00000000, 0x29000000, 0x00000070, // ssub_2_ssub_3_ssub_6_ssub_7
3886  0x00000000, 0x20000000, 0x00000100, 0x00000060, // ssub_4_ssub_5_ssub_8_ssub_9
3887  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_dsub_5
3888  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_8_ssub_9_ssub_12_ssub_13
3889  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_5_dsub_7
3890};
3891
3892static const uint32_t DPairSubClassMask[] = {
3893  0x00000000, 0x000003fc, 0x00000000, 0x00000000,
3894  0x00000000, 0xd7e5e400, 0xfffffe03, 0x0000007f, // qsub_0
3895  0x00000000, 0x00000000, 0xfffffe00, 0x0000007f, // qsub_1
3896  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qsub_2
3897  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qsub_3
3898  0x00000000, 0xd7e5e400, 0xfffffe03, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5
3899  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9
3900  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_5_ssub_12_ssub_13
3901};
3902
3903static const uint32_t DPair_with_ssub_0SubClassMask[] = {
3904  0x00000000, 0x000003e8, 0x00000000, 0x00000000,
3905  0x00000000, 0xd7e4a000, 0xbfffcc03, 0x0000007f, // qsub_0
3906  0x00000000, 0x00000000, 0x3ff9c000, 0x0000007f, // qsub_1
3907  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qsub_2
3908  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qsub_3
3909  0x00000000, 0xd7648000, 0xbffbc803, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5
3910  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9
3911  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // dsub_5_ssub_12_ssub_13
3912};
3913
3914static const uint32_t QPRSubClassMask[] = {
3915  0x00000000, 0x00000290, 0x00000000, 0x00000000,
3916  0x00000000, 0x84404000, 0xcc121001, 0x0000007f, // qsub_0
3917  0x00000000, 0x00000000, 0xcc121000, 0x0000007f, // qsub_1
3918  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qsub_2
3919  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qsub_3
3920  0x00000000, 0x42810000, 0x32a42002, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
3921};
3922
3923static const uint32_t DPair_with_ssub_2SubClassMask[] = {
3924  0x00000000, 0x000003e0, 0x00000000, 0x00000000,
3925  0x00000000, 0xd7648000, 0xbffbc803, 0x0000007f, // qsub_0
3926  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // qsub_1
3927  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qsub_2
3928  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qsub_3
3929  0x00000000, 0xd7240000, 0x3ff9c003, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5
3930  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9
3931  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_5_ssub_12_ssub_13
3932};
3933
3934static const uint32_t DPair_with_dsub_0_in_DPR_8SubClassMask[] = {
3935  0x00000000, 0x00000340, 0x00000000, 0x00000000,
3936  0x00000000, 0xd1200000, 0x3f490003, 0x00000078, // qsub_0
3937  0x00000000, 0x00000000, 0x39400000, 0x00000070, // qsub_1
3938  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qsub_2
3939  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qsub_3
3940  0x00000000, 0x91000000, 0x3d480003, 0x00000078, // ssub_2_ssub_3_ssub_4_ssub_5
3941  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_ssub_8_ssub_9
3942  0x00000000, 0x00000000, 0x00000000, 0x00000060, // dsub_5_ssub_12_ssub_13
3943};
3944
3945static const uint32_t QPR_VFP2SubClassMask[] = {
3946  0x00000000, 0x00000280, 0x00000000, 0x00000000,
3947  0x00000000, 0x84400000, 0x8c120001, 0x0000007f, // qsub_0
3948  0x00000000, 0x00000000, 0x0c100000, 0x0000007f, // qsub_1
3949  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qsub_2
3950  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qsub_3
3951  0x00000000, 0x42000000, 0x32a00002, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
3952};
3953
3954static const uint32_t DPair_with_dsub_1_in_DPR_8SubClassMask[] = {
3955  0x00000000, 0x00000300, 0x00000000, 0x00000000,
3956  0x00000000, 0x91000000, 0x3d480003, 0x00000078, // qsub_0
3957  0x00000000, 0x00000000, 0x29000000, 0x00000070, // qsub_1
3958  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qsub_2
3959  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qsub_3
3960  0x00000000, 0x10000000, 0x39400003, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5
3961  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9
3962  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_5_ssub_12_ssub_13
3963};
3964
3965static const uint32_t QPR_8SubClassMask[] = {
3966  0x00000000, 0x00000200, 0x00000000, 0x00000000,
3967  0x00000000, 0x80000000, 0x0c000001, 0x00000078, // qsub_0
3968  0x00000000, 0x00000000, 0x08000000, 0x00000070, // qsub_1
3969  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qsub_2
3970  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qsub_3
3971  0x00000000, 0x00000000, 0x30000002, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
3972};
3973
3974static const uint32_t DTripleSubClassMask[] = {
3975  0x00000000, 0xd7e5e400, 0x00000003, 0x00000000,
3976  0x00000000, 0x00000000, 0xfffffe00, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
3977  0x00000000, 0x00000000, 0xfffffe00, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
3978  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
3979  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
3980  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
3981  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_5_ssub_12_ssub_13_dsub_7
3982};
3983
3984static const uint32_t DTripleSpcSubClassMask[] = {
3985  0x00000000, 0x281a1800, 0x000001fc, 0x00000000,
3986  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
3987  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
3988  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
3989  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_dsub_5_dsub_7
3990};
3991
3992static const uint32_t DTripleSpc_with_ssub_0SubClassMask[] = {
3993  0x00000000, 0x281a1000, 0x000001f8, 0x00000000,
3994  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
3995  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
3996  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
3997  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_dsub_5_dsub_7
3998};
3999
4000static const uint32_t DTriple_with_ssub_0SubClassMask[] = {
4001  0x00000000, 0xd7e4a000, 0x00000003, 0x00000000,
4002  0x00000000, 0x00000000, 0xbfffcc00, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4003  0x00000000, 0x00000000, 0xbffbc800, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4004  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4005  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4006  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4007  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // dsub_5_ssub_12_ssub_13_dsub_7
4008};
4009
4010static const uint32_t DTriple_with_qsub_0_in_QPRSubClassMask[] = {
4011  0x00000000, 0x84404000, 0x00000001, 0x00000000,
4012  0x00000000, 0x00000000, 0xcc121000, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4013  0x00000000, 0x00000000, 0x32a42000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4014  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4015  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4016};
4017
4018static const uint32_t DTriple_with_ssub_2SubClassMask[] = {
4019  0x00000000, 0xd7648000, 0x00000003, 0x00000000,
4020  0x00000000, 0x00000000, 0xbffbc800, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4021  0x00000000, 0x00000000, 0x3ff9c000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4022  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4023  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4024  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4025  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_5_ssub_12_ssub_13_dsub_7
4026};
4027
4028static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4029  0x00000000, 0x42810000, 0x00000002, 0x00000000,
4030  0x00000000, 0x00000000, 0x32a42000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4031  0x00000000, 0x00000000, 0xcc121000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4032  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4033  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_5_ssub_12_ssub_13_dsub_7
4034};
4035
4036static const uint32_t DTripleSpc_with_ssub_4SubClassMask[] = {
4037  0x00000000, 0x281a0000, 0x000001f0, 0x00000000,
4038  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4039  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4040  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4041  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_dsub_5_dsub_7
4042};
4043
4044static const uint32_t DTriple_with_ssub_4SubClassMask[] = {
4045  0x00000000, 0xd7240000, 0x00000003, 0x00000000,
4046  0x00000000, 0x00000000, 0x3ff9c000, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4047  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4048  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4049  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4050  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4051  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_5_ssub_12_ssub_13_dsub_7
4052};
4053
4054static const uint32_t DTripleSpc_with_ssub_8SubClassMask[] = {
4055  0x00000000, 0x28180000, 0x000001e0, 0x00000000,
4056  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4057  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4058  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4059  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_6_ssub_7_dsub_5_dsub_7
4060};
4061
4062static const uint32_t DTripleSpc_with_dsub_0_in_DPR_8SubClassMask[] = {
4063  0x00000000, 0x28100000, 0x000001c0, 0x00000000,
4064  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4065  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4066  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4067  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_dsub_5_dsub_7
4068};
4069
4070static const uint32_t DTriple_with_dsub_0_in_DPR_8SubClassMask[] = {
4071  0x00000000, 0xd1200000, 0x00000003, 0x00000000,
4072  0x00000000, 0x00000000, 0x3f490000, 0x00000078, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4073  0x00000000, 0x00000000, 0x3d480000, 0x00000078, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4074  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4075  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4076  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4077  0x00000000, 0x00000000, 0x00000000, 0x00000060, // dsub_5_ssub_12_ssub_13_dsub_7
4078};
4079
4080static const uint32_t DTriple_with_qsub_0_in_QPR_VFP2SubClassMask[] = {
4081  0x00000000, 0x84400000, 0x00000001, 0x00000000,
4082  0x00000000, 0x00000000, 0x8c120000, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4083  0x00000000, 0x00000000, 0x32a00000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4084  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4085  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4086};
4087
4088static const uint32_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4089  0x00000000, 0x42800000, 0x00000002, 0x00000000,
4090  0x00000000, 0x00000000, 0x32a40000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4091  0x00000000, 0x00000000, 0x8c120000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4092  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4093  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // dsub_5_ssub_12_ssub_13_dsub_7
4094};
4095
4096static const uint32_t DTriple_with_dsub_1_in_DPR_8SubClassMask[] = {
4097  0x00000000, 0x91000000, 0x00000003, 0x00000000,
4098  0x00000000, 0x00000000, 0x3d480000, 0x00000078, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4099  0x00000000, 0x00000000, 0x39400000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4100  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4101  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4102  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4103  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_5_ssub_12_ssub_13_dsub_7
4104};
4105
4106static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2SubClassMask[] = {
4107  0x00000000, 0x42000000, 0x00000002, 0x00000000,
4108  0x00000000, 0x00000000, 0x32a00000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4109  0x00000000, 0x00000000, 0x0c100000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4110  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4111  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_5_ssub_12_ssub_13_dsub_7
4112};
4113
4114static const uint32_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRSubClassMask[] = {
4115  0x00000000, 0x84000000, 0x00000001, 0x00000000,
4116  0x00000000, 0x00000000, 0x0c100000, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4117  0x00000000, 0x00000000, 0x32800000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4118  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4119  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4120};
4121
4122static const uint32_t DTripleSpc_with_dsub_2_in_DPR_8SubClassMask[] = {
4123  0x00000000, 0x28000000, 0x00000180, 0x00000000,
4124  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4125  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4126  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4127  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_dsub_5_dsub_7
4128};
4129
4130static const uint32_t DTriple_with_dsub_2_in_DPR_8SubClassMask[] = {
4131  0x00000000, 0x10000000, 0x00000003, 0x00000000,
4132  0x00000000, 0x00000000, 0x39400000, 0x00000070, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4133  0x00000000, 0x00000000, 0x29000000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4134  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4135  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4136  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4137  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_5_ssub_12_ssub_13_dsub_7
4138};
4139
4140static const uint32_t DTripleSpc_with_dsub_4_in_DPR_8SubClassMask[] = {
4141  0x00000000, 0x20000000, 0x00000100, 0x00000000,
4142  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4143  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4144  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4145  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_6_ssub_7_dsub_5_dsub_7
4146};
4147
4148static const uint32_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4149  0x00000000, 0x40000000, 0x00000002, 0x00000000,
4150  0x00000000, 0x00000000, 0x32000000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4151  0x00000000, 0x00000000, 0x0c000000, 0x00000078, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4152  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4153  0x00000000, 0x00000000, 0x00000000, 0x00000060, // dsub_5_ssub_12_ssub_13_dsub_7
4154};
4155
4156static const uint32_t DTriple_with_qsub_0_in_QPR_8SubClassMask[] = {
4157  0x00000000, 0x80000000, 0x00000001, 0x00000000,
4158  0x00000000, 0x00000000, 0x0c000000, 0x00000078, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4159  0x00000000, 0x00000000, 0x30000000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4160  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4161  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4162};
4163
4164static const uint32_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRSubClassMask[] = {
4165  0x00000000, 0x00000000, 0x00000001, 0x00000000,
4166  0x00000000, 0x00000000, 0x08000000, 0x00000070, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4167  0x00000000, 0x00000000, 0x20000000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4168  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4169  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4170};
4171
4172static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask[] = {
4173  0x00000000, 0x00000000, 0x00000002, 0x00000000,
4174  0x00000000, 0x00000000, 0x30000000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
4175  0x00000000, 0x00000000, 0x08000000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
4176  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
4177  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_5_ssub_12_ssub_13_dsub_7
4178};
4179
4180static const uint32_t DQuadSpcSubClassMask[] = {
4181  0x00000000, 0x00000000, 0x000001fc, 0x00000000,
4182  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4183  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4184  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4185  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_dsub_5_dsub_7
4186};
4187
4188static const uint32_t DQuadSpc_with_ssub_0SubClassMask[] = {
4189  0x00000000, 0x00000000, 0x000001f8, 0x00000000,
4190  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4191  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4192  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4193  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_dsub_5_dsub_7
4194};
4195
4196static const uint32_t DQuadSpc_with_ssub_4SubClassMask[] = {
4197  0x00000000, 0x00000000, 0x000001f0, 0x00000000,
4198  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4199  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4200  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4201  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_dsub_5_dsub_7
4202};
4203
4204static const uint32_t DQuadSpc_with_ssub_8SubClassMask[] = {
4205  0x00000000, 0x00000000, 0x000001e0, 0x00000000,
4206  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4207  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4208  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4209  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_6_ssub_7_dsub_5_dsub_7
4210};
4211
4212static const uint32_t DQuadSpc_with_dsub_0_in_DPR_8SubClassMask[] = {
4213  0x00000000, 0x00000000, 0x000001c0, 0x00000000,
4214  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4215  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4216  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4217  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_dsub_5_dsub_7
4218};
4219
4220static const uint32_t DQuadSpc_with_dsub_2_in_DPR_8SubClassMask[] = {
4221  0x00000000, 0x00000000, 0x00000180, 0x00000000,
4222  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4223  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4224  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4225  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_dsub_5_dsub_7
4226};
4227
4228static const uint32_t DQuadSpc_with_dsub_4_in_DPR_8SubClassMask[] = {
4229  0x00000000, 0x00000000, 0x00000100, 0x00000000,
4230  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
4231  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
4232  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
4233  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_6_ssub_7_dsub_5_dsub_7
4234};
4235
4236static const uint32_t DQuadSubClassMask[] = {
4237  0x00000000, 0x00000000, 0x3ffffe00, 0x00000000,
4238  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qqsub_0
4239  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qqsub_1
4240  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4241  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4242  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4243};
4244
4245static const uint32_t DQuad_with_ssub_0SubClassMask[] = {
4246  0x00000000, 0x00000000, 0x3fffcc00, 0x00000000,
4247  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // qqsub_0
4248  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qqsub_1
4249  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4250  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4251  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4252};
4253
4254static const uint32_t DQuad_with_ssub_2SubClassMask[] = {
4255  0x00000000, 0x00000000, 0x3ffbc800, 0x00000000,
4256  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // qqsub_0
4257  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qqsub_1
4258  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4259  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4260  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4261};
4262
4263static const uint32_t QQPRSubClassMask[] = {
4264  0x00000000, 0x00000000, 0x0c121000, 0x00000000,
4265  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qqsub_0
4266  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qqsub_1
4267  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4268};
4269
4270static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4271  0x00000000, 0x00000000, 0x32a42000, 0x00000000,
4272  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4273  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4274};
4275
4276static const uint32_t DQuad_with_ssub_4SubClassMask[] = {
4277  0x00000000, 0x00000000, 0x3ff9c000, 0x00000000,
4278  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // qqsub_0
4279  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qqsub_1
4280  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4281  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4282  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4283};
4284
4285static const uint32_t DQuad_with_ssub_6SubClassMask[] = {
4286  0x00000000, 0x00000000, 0x3fd98000, 0x00000000,
4287  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // qqsub_0
4288  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qqsub_1
4289  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4290  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4291  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4292};
4293
4294static const uint32_t DQuad_with_dsub_0_in_DPR_8SubClassMask[] = {
4295  0x00000000, 0x00000000, 0x3f490000, 0x00000000,
4296  0x00000000, 0x00000000, 0x00000000, 0x00000078, // qqsub_0
4297  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qqsub_1
4298  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4299  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4300  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4301};
4302
4303static const uint32_t DQuad_with_qsub_0_in_QPR_VFP2SubClassMask[] = {
4304  0x00000000, 0x00000000, 0x0c120000, 0x00000000,
4305  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // qqsub_0
4306  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qqsub_1
4307  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4308};
4309
4310static const uint32_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4311  0x00000000, 0x00000000, 0x32a40000, 0x00000000,
4312  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4313  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4314};
4315
4316static const uint32_t DQuad_with_dsub_1_in_DPR_8SubClassMask[] = {
4317  0x00000000, 0x00000000, 0x3d480000, 0x00000000,
4318  0x00000000, 0x00000000, 0x00000000, 0x00000078, // qqsub_0
4319  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qqsub_1
4320  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4321  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4322  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4323};
4324
4325static const uint32_t DQuad_with_qsub_1_in_QPR_VFP2SubClassMask[] = {
4326  0x00000000, 0x00000000, 0x0c100000, 0x00000000,
4327  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // qqsub_0
4328  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qqsub_1
4329  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4330};
4331
4332static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2SubClassMask[] = {
4333  0x00000000, 0x00000000, 0x32a00000, 0x00000000,
4334  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4335  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4336};
4337
4338static const uint32_t DQuad_with_dsub_2_in_DPR_8SubClassMask[] = {
4339  0x00000000, 0x00000000, 0x39400000, 0x00000000,
4340  0x00000000, 0x00000000, 0x00000000, 0x00000070, // qqsub_0
4341  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qqsub_1
4342  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4343  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4344  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4345};
4346
4347static const uint32_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4348  0x00000000, 0x00000000, 0x32800000, 0x00000000,
4349  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4350  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4351};
4352
4353static const uint32_t DQuad_with_dsub_3_in_DPR_8SubClassMask[] = {
4354  0x00000000, 0x00000000, 0x29000000, 0x00000000,
4355  0x00000000, 0x00000000, 0x00000000, 0x00000070, // qqsub_0
4356  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qqsub_1
4357  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4358  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4359  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4360};
4361
4362static const uint32_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4363  0x00000000, 0x00000000, 0x32000000, 0x00000000,
4364  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4365  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4366};
4367
4368static const uint32_t DQuad_with_qsub_0_in_QPR_8SubClassMask[] = {
4369  0x00000000, 0x00000000, 0x0c000000, 0x00000000,
4370  0x00000000, 0x00000000, 0x00000000, 0x00000078, // qqsub_0
4371  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qqsub_1
4372  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4373};
4374
4375static const uint32_t DQuad_with_qsub_1_in_QPR_8SubClassMask[] = {
4376  0x00000000, 0x00000000, 0x08000000, 0x00000000,
4377  0x00000000, 0x00000000, 0x00000000, 0x00000070, // qqsub_0
4378  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qqsub_1
4379  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
4380};
4381
4382static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask[] = {
4383  0x00000000, 0x00000000, 0x30000000, 0x00000000,
4384  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4385  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4386};
4387
4388static const uint32_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
4389  0x00000000, 0x00000000, 0x20000000, 0x00000000,
4390  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
4391  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
4392};
4393
4394static const uint32_t QQQQPRSubClassMask[] = {
4395  0x00000000, 0x00000000, 0xc0000000, 0x0000007f,
4396};
4397
4398static const uint32_t QQQQPR_with_ssub_0SubClassMask[] = {
4399  0x00000000, 0x00000000, 0x80000000, 0x0000007f,
4400};
4401
4402static const uint32_t QQQQPR_with_ssub_4SubClassMask[] = {
4403  0x00000000, 0x00000000, 0x00000000, 0x0000007f,
4404};
4405
4406static const uint32_t QQQQPR_with_ssub_8SubClassMask[] = {
4407  0x00000000, 0x00000000, 0x00000000, 0x0000007e,
4408};
4409
4410static const uint32_t QQQQPR_with_ssub_12SubClassMask[] = {
4411  0x00000000, 0x00000000, 0x00000000, 0x0000007c,
4412};
4413
4414static const uint32_t QQQQPR_with_dsub_0_in_DPR_8SubClassMask[] = {
4415  0x00000000, 0x00000000, 0x00000000, 0x00000078,
4416};
4417
4418static const uint32_t QQQQPR_with_dsub_2_in_DPR_8SubClassMask[] = {
4419  0x00000000, 0x00000000, 0x00000000, 0x00000070,
4420};
4421
4422static const uint32_t QQQQPR_with_dsub_4_in_DPR_8SubClassMask[] = {
4423  0x00000000, 0x00000000, 0x00000000, 0x00000060,
4424};
4425
4426static const uint32_t QQQQPR_with_dsub_6_in_DPR_8SubClassMask[] = {
4427  0x00000000, 0x00000000, 0x00000000, 0x00000040,
4428};
4429
4430static const uint16_t SuperRegIdxSeqs[] = {
4431  /* 0 */ 1, 2, 3, 4, 5, 6, 7, 8, 0,
4432  /* 9 */ 9, 0,
4433  /* 11 */ 9, 10, 0,
4434  /* 14 */ 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 0,
4435  /* 31 */ 13, 14, 15, 16, 37, 0,
4436  /* 37 */ 38, 40, 45, 48, 0,
4437  /* 42 */ 42, 50, 0,
4438  /* 45 */ 34, 36, 44, 52, 0,
4439  /* 50 */ 33, 35, 43, 46, 51, 53, 0,
4440  /* 57 */ 34, 36, 47, 54, 0,
4441  /* 62 */ 34, 36, 44, 47, 52, 54, 0,
4442  /* 69 */ 13, 14, 15, 16, 37, 49, 55, 0,
4443  /* 77 */ 11, 12, 56, 0,
4444  /* 81 */ 11, 12, 42, 50, 56, 0,
4445};
4446
4447static const TargetRegisterClass *const SPRSuperclasses[] = {
4448  &ARM::HPRRegClass,
4449  nullptr
4450};
4451
4452static const TargetRegisterClass *const SPR_8Superclasses[] = {
4453  &ARM::HPRRegClass,
4454  &ARM::SPRRegClass,
4455  nullptr
4456};
4457
4458static const TargetRegisterClass *const GPRnopcSuperclasses[] = {
4459  &ARM::GPRRegClass,
4460  &ARM::GPRwithAPSRRegClass,
4461  nullptr
4462};
4463
4464static const TargetRegisterClass *const rGPRSuperclasses[] = {
4465  &ARM::GPRRegClass,
4466  &ARM::GPRwithAPSRRegClass,
4467  &ARM::GPRnopcRegClass,
4468  nullptr
4469};
4470
4471static const TargetRegisterClass *const tGPRwithpcSuperclasses[] = {
4472  &ARM::GPRRegClass,
4473  nullptr
4474};
4475
4476static const TargetRegisterClass *const hGPRSuperclasses[] = {
4477  &ARM::GPRRegClass,
4478  nullptr
4479};
4480
4481static const TargetRegisterClass *const tGPRSuperclasses[] = {
4482  &ARM::GPRRegClass,
4483  &ARM::GPRwithAPSRRegClass,
4484  &ARM::GPRnopcRegClass,
4485  &ARM::rGPRRegClass,
4486  &ARM::tGPRwithpcRegClass,
4487  nullptr
4488};
4489
4490static const TargetRegisterClass *const GPRnopc_and_hGPRSuperclasses[] = {
4491  &ARM::GPRRegClass,
4492  &ARM::GPRwithAPSRRegClass,
4493  &ARM::GPRnopcRegClass,
4494  &ARM::hGPRRegClass,
4495  nullptr
4496};
4497
4498static const TargetRegisterClass *const hGPR_and_rGPRSuperclasses[] = {
4499  &ARM::GPRRegClass,
4500  &ARM::GPRwithAPSRRegClass,
4501  &ARM::GPRnopcRegClass,
4502  &ARM::rGPRRegClass,
4503  &ARM::hGPRRegClass,
4504  &ARM::GPRnopc_and_hGPRRegClass,
4505  nullptr
4506};
4507
4508static const TargetRegisterClass *const tcGPRSuperclasses[] = {
4509  &ARM::GPRRegClass,
4510  &ARM::GPRwithAPSRRegClass,
4511  &ARM::GPRnopcRegClass,
4512  &ARM::rGPRRegClass,
4513  nullptr
4514};
4515
4516static const TargetRegisterClass *const tGPR_and_tcGPRSuperclasses[] = {
4517  &ARM::GPRRegClass,
4518  &ARM::GPRwithAPSRRegClass,
4519  &ARM::GPRnopcRegClass,
4520  &ARM::rGPRRegClass,
4521  &ARM::tGPRwithpcRegClass,
4522  &ARM::tGPRRegClass,
4523  &ARM::tcGPRRegClass,
4524  nullptr
4525};
4526
4527static const TargetRegisterClass *const GPRspSuperclasses[] = {
4528  &ARM::GPRRegClass,
4529  &ARM::GPRwithAPSRRegClass,
4530  &ARM::GPRnopcRegClass,
4531  &ARM::hGPRRegClass,
4532  &ARM::GPRnopc_and_hGPRRegClass,
4533  nullptr
4534};
4535
4536static const TargetRegisterClass *const hGPR_and_tGPRwithpcSuperclasses[] = {
4537  &ARM::GPRRegClass,
4538  &ARM::tGPRwithpcRegClass,
4539  &ARM::hGPRRegClass,
4540  nullptr
4541};
4542
4543static const TargetRegisterClass *const hGPR_and_tcGPRSuperclasses[] = {
4544  &ARM::GPRRegClass,
4545  &ARM::GPRwithAPSRRegClass,
4546  &ARM::GPRnopcRegClass,
4547  &ARM::rGPRRegClass,
4548  &ARM::hGPRRegClass,
4549  &ARM::GPRnopc_and_hGPRRegClass,
4550  &ARM::hGPR_and_rGPRRegClass,
4551  &ARM::tcGPRRegClass,
4552  nullptr
4553};
4554
4555static const TargetRegisterClass *const DPR_VFP2Superclasses[] = {
4556  &ARM::DPRRegClass,
4557  nullptr
4558};
4559
4560static const TargetRegisterClass *const DPR_8Superclasses[] = {
4561  &ARM::DPRRegClass,
4562  &ARM::DPR_VFP2RegClass,
4563  nullptr
4564};
4565
4566static const TargetRegisterClass *const GPRPair_with_gsub_1_in_rGPRSuperclasses[] = {
4567  &ARM::GPRPairRegClass,
4568  nullptr
4569};
4570
4571static const TargetRegisterClass *const GPRPair_with_gsub_0_in_tGPRSuperclasses[] = {
4572  &ARM::GPRPairRegClass,
4573  &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
4574  nullptr
4575};
4576
4577static const TargetRegisterClass *const GPRPair_with_gsub_0_in_hGPRSuperclasses[] = {
4578  &ARM::GPRPairRegClass,
4579  nullptr
4580};
4581
4582static const TargetRegisterClass *const GPRPair_with_gsub_0_in_tcGPRSuperclasses[] = {
4583  &ARM::GPRPairRegClass,
4584  nullptr
4585};
4586
4587static const TargetRegisterClass *const GPRPair_with_gsub_1_in_hGPR_and_rGPRSuperclasses[] = {
4588  &ARM::GPRPairRegClass,
4589  &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
4590  &ARM::GPRPair_with_gsub_0_in_hGPRRegClass,
4591  nullptr
4592};
4593
4594static const TargetRegisterClass *const GPRPair_with_gsub_1_in_tcGPRSuperclasses[] = {
4595  &ARM::GPRPairRegClass,
4596  &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
4597  &ARM::GPRPair_with_gsub_0_in_tGPRRegClass,
4598  &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass,
4599  nullptr
4600};
4601
4602static const TargetRegisterClass *const GPRPair_with_gsub_1_in_GPRspSuperclasses[] = {
4603  &ARM::GPRPairRegClass,
4604  &ARM::GPRPair_with_gsub_0_in_hGPRRegClass,
4605  &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass,
4606  nullptr
4607};
4608
4609static const TargetRegisterClass *const DPairSpc_with_ssub_0Superclasses[] = {
4610  &ARM::DPairSpcRegClass,
4611  nullptr
4612};
4613
4614static const TargetRegisterClass *const DPairSpc_with_ssub_4Superclasses[] = {
4615  &ARM::DPairSpcRegClass,
4616  &ARM::DPairSpc_with_ssub_0RegClass,
4617  nullptr
4618};
4619
4620static const TargetRegisterClass *const DPairSpc_with_dsub_0_in_DPR_8Superclasses[] = {
4621  &ARM::DPairSpcRegClass,
4622  &ARM::DPairSpc_with_ssub_0RegClass,
4623  &ARM::DPairSpc_with_ssub_4RegClass,
4624  nullptr
4625};
4626
4627static const TargetRegisterClass *const DPairSpc_with_dsub_2_in_DPR_8Superclasses[] = {
4628  &ARM::DPairSpcRegClass,
4629  &ARM::DPairSpc_with_ssub_0RegClass,
4630  &ARM::DPairSpc_with_ssub_4RegClass,
4631  &ARM::DPairSpc_with_dsub_0_in_DPR_8RegClass,
4632  nullptr
4633};
4634
4635static const TargetRegisterClass *const DPair_with_ssub_0Superclasses[] = {
4636  &ARM::DPairRegClass,
4637  nullptr
4638};
4639
4640static const TargetRegisterClass *const QPRSuperclasses[] = {
4641  &ARM::DPairRegClass,
4642  nullptr
4643};
4644
4645static const TargetRegisterClass *const DPair_with_ssub_2Superclasses[] = {
4646  &ARM::DPairRegClass,
4647  &ARM::DPair_with_ssub_0RegClass,
4648  nullptr
4649};
4650
4651static const TargetRegisterClass *const DPair_with_dsub_0_in_DPR_8Superclasses[] = {
4652  &ARM::DPairRegClass,
4653  &ARM::DPair_with_ssub_0RegClass,
4654  &ARM::DPair_with_ssub_2RegClass,
4655  nullptr
4656};
4657
4658static const TargetRegisterClass *const QPR_VFP2Superclasses[] = {
4659  &ARM::DPairRegClass,
4660  &ARM::DPair_with_ssub_0RegClass,
4661  &ARM::QPRRegClass,
4662  &ARM::DPair_with_ssub_2RegClass,
4663  nullptr
4664};
4665
4666static const TargetRegisterClass *const DPair_with_dsub_1_in_DPR_8Superclasses[] = {
4667  &ARM::DPairRegClass,
4668  &ARM::DPair_with_ssub_0RegClass,
4669  &ARM::DPair_with_ssub_2RegClass,
4670  &ARM::DPair_with_dsub_0_in_DPR_8RegClass,
4671  nullptr
4672};
4673
4674static const TargetRegisterClass *const QPR_8Superclasses[] = {
4675  &ARM::DPairRegClass,
4676  &ARM::DPair_with_ssub_0RegClass,
4677  &ARM::QPRRegClass,
4678  &ARM::DPair_with_ssub_2RegClass,
4679  &ARM::DPair_with_dsub_0_in_DPR_8RegClass,
4680  &ARM::QPR_VFP2RegClass,
4681  &ARM::DPair_with_dsub_1_in_DPR_8RegClass,
4682  nullptr
4683};
4684
4685static const TargetRegisterClass *const DTripleSpc_with_ssub_0Superclasses[] = {
4686  &ARM::DTripleSpcRegClass,
4687  nullptr
4688};
4689
4690static const TargetRegisterClass *const DTriple_with_ssub_0Superclasses[] = {
4691  &ARM::DTripleRegClass,
4692  nullptr
4693};
4694
4695static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPRSuperclasses[] = {
4696  &ARM::DTripleRegClass,
4697  nullptr
4698};
4699
4700static const TargetRegisterClass *const DTriple_with_ssub_2Superclasses[] = {
4701  &ARM::DTripleRegClass,
4702  &ARM::DTriple_with_ssub_0RegClass,
4703  nullptr
4704};
4705
4706static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
4707  &ARM::DTripleRegClass,
4708  nullptr
4709};
4710
4711static const TargetRegisterClass *const DTripleSpc_with_ssub_4Superclasses[] = {
4712  &ARM::DTripleSpcRegClass,
4713  &ARM::DTripleSpc_with_ssub_0RegClass,
4714  nullptr
4715};
4716
4717static const TargetRegisterClass *const DTriple_with_ssub_4Superclasses[] = {
4718  &ARM::DTripleRegClass,
4719  &ARM::DTriple_with_ssub_0RegClass,
4720  &ARM::DTriple_with_ssub_2RegClass,
4721  nullptr
4722};
4723
4724static const TargetRegisterClass *const DTripleSpc_with_ssub_8Superclasses[] = {
4725  &ARM::DTripleSpcRegClass,
4726  &ARM::DTripleSpc_with_ssub_0RegClass,
4727  &ARM::DTripleSpc_with_ssub_4RegClass,
4728  nullptr
4729};
4730
4731static const TargetRegisterClass *const DTripleSpc_with_dsub_0_in_DPR_8Superclasses[] = {
4732  &ARM::DTripleSpcRegClass,
4733  &ARM::DTripleSpc_with_ssub_0RegClass,
4734  &ARM::DTripleSpc_with_ssub_4RegClass,
4735  &ARM::DTripleSpc_with_ssub_8RegClass,
4736  nullptr
4737};
4738
4739static const TargetRegisterClass *const DTriple_with_dsub_0_in_DPR_8Superclasses[] = {
4740  &ARM::DTripleRegClass,
4741  &ARM::DTriple_with_ssub_0RegClass,
4742  &ARM::DTriple_with_ssub_2RegClass,
4743  &ARM::DTriple_with_ssub_4RegClass,
4744  nullptr
4745};
4746
4747static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPR_VFP2Superclasses[] = {
4748  &ARM::DTripleRegClass,
4749  &ARM::DTriple_with_ssub_0RegClass,
4750  &ARM::DTriple_with_qsub_0_in_QPRRegClass,
4751  &ARM::DTriple_with_ssub_2RegClass,
4752  nullptr
4753};
4754
4755static const TargetRegisterClass *const DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
4756  &ARM::DTripleRegClass,
4757  &ARM::DTriple_with_ssub_0RegClass,
4758  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4759  nullptr
4760};
4761
4762static const TargetRegisterClass *const DTriple_with_dsub_1_in_DPR_8Superclasses[] = {
4763  &ARM::DTripleRegClass,
4764  &ARM::DTriple_with_ssub_0RegClass,
4765  &ARM::DTriple_with_ssub_2RegClass,
4766  &ARM::DTriple_with_ssub_4RegClass,
4767  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4768  nullptr
4769};
4770
4771static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Superclasses[] = {
4772  &ARM::DTripleRegClass,
4773  &ARM::DTriple_with_ssub_0RegClass,
4774  &ARM::DTriple_with_ssub_2RegClass,
4775  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4776  &ARM::DTriple_with_ssub_4RegClass,
4777  &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4778  nullptr
4779};
4780
4781static const TargetRegisterClass *const DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRSuperclasses[] = {
4782  &ARM::DTripleRegClass,
4783  &ARM::DTriple_with_ssub_0RegClass,
4784  &ARM::DTriple_with_qsub_0_in_QPRRegClass,
4785  &ARM::DTriple_with_ssub_2RegClass,
4786  &ARM::DTriple_with_ssub_4RegClass,
4787  &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
4788  nullptr
4789};
4790
4791static const TargetRegisterClass *const DTripleSpc_with_dsub_2_in_DPR_8Superclasses[] = {
4792  &ARM::DTripleSpcRegClass,
4793  &ARM::DTripleSpc_with_ssub_0RegClass,
4794  &ARM::DTripleSpc_with_ssub_4RegClass,
4795  &ARM::DTripleSpc_with_ssub_8RegClass,
4796  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
4797  nullptr
4798};
4799
4800static const TargetRegisterClass *const DTriple_with_dsub_2_in_DPR_8Superclasses[] = {
4801  &ARM::DTripleRegClass,
4802  &ARM::DTriple_with_ssub_0RegClass,
4803  &ARM::DTriple_with_ssub_2RegClass,
4804  &ARM::DTriple_with_ssub_4RegClass,
4805  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4806  &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
4807  nullptr
4808};
4809
4810static const TargetRegisterClass *const DTripleSpc_with_dsub_4_in_DPR_8Superclasses[] = {
4811  &ARM::DTripleSpcRegClass,
4812  &ARM::DTripleSpc_with_ssub_0RegClass,
4813  &ARM::DTripleSpc_with_ssub_4RegClass,
4814  &ARM::DTripleSpc_with_ssub_8RegClass,
4815  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
4816  &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
4817  nullptr
4818};
4819
4820static const TargetRegisterClass *const DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
4821  &ARM::DTripleRegClass,
4822  &ARM::DTriple_with_ssub_0RegClass,
4823  &ARM::DTriple_with_ssub_2RegClass,
4824  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4825  &ARM::DTriple_with_ssub_4RegClass,
4826  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4827  &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4828  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
4829  nullptr
4830};
4831
4832static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPR_8Superclasses[] = {
4833  &ARM::DTripleRegClass,
4834  &ARM::DTriple_with_ssub_0RegClass,
4835  &ARM::DTriple_with_qsub_0_in_QPRRegClass,
4836  &ARM::DTriple_with_ssub_2RegClass,
4837  &ARM::DTriple_with_ssub_4RegClass,
4838  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4839  &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
4840  &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
4841  &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass,
4842  nullptr
4843};
4844
4845static const TargetRegisterClass *const DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRSuperclasses[] = {
4846  &ARM::DTripleRegClass,
4847  &ARM::DTriple_with_ssub_0RegClass,
4848  &ARM::DTriple_with_qsub_0_in_QPRRegClass,
4849  &ARM::DTriple_with_ssub_2RegClass,
4850  &ARM::DTriple_with_ssub_4RegClass,
4851  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4852  &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
4853  &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
4854  &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass,
4855  &ARM::DTriple_with_dsub_2_in_DPR_8RegClass,
4856  &ARM::DTriple_with_qsub_0_in_QPR_8RegClass,
4857  nullptr
4858};
4859
4860static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses[] = {
4861  &ARM::DTripleRegClass,
4862  &ARM::DTriple_with_ssub_0RegClass,
4863  &ARM::DTriple_with_ssub_2RegClass,
4864  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4865  &ARM::DTriple_with_ssub_4RegClass,
4866  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
4867  &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4868  &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
4869  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
4870  &ARM::DTriple_with_dsub_2_in_DPR_8RegClass,
4871  &ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
4872  nullptr
4873};
4874
4875static const TargetRegisterClass *const DQuadSpcSuperclasses[] = {
4876  &ARM::DTripleSpcRegClass,
4877  nullptr
4878};
4879
4880static const TargetRegisterClass *const DQuadSpc_with_ssub_0Superclasses[] = {
4881  &ARM::DTripleSpcRegClass,
4882  &ARM::DTripleSpc_with_ssub_0RegClass,
4883  &ARM::DQuadSpcRegClass,
4884  nullptr
4885};
4886
4887static const TargetRegisterClass *const DQuadSpc_with_ssub_4Superclasses[] = {
4888  &ARM::DTripleSpcRegClass,
4889  &ARM::DTripleSpc_with_ssub_0RegClass,
4890  &ARM::DTripleSpc_with_ssub_4RegClass,
4891  &ARM::DQuadSpcRegClass,
4892  &ARM::DQuadSpc_with_ssub_0RegClass,
4893  nullptr
4894};
4895
4896static const TargetRegisterClass *const DQuadSpc_with_ssub_8Superclasses[] = {
4897  &ARM::DTripleSpcRegClass,
4898  &ARM::DTripleSpc_with_ssub_0RegClass,
4899  &ARM::DTripleSpc_with_ssub_4RegClass,
4900  &ARM::DTripleSpc_with_ssub_8RegClass,
4901  &ARM::DQuadSpcRegClass,
4902  &ARM::DQuadSpc_with_ssub_0RegClass,
4903  &ARM::DQuadSpc_with_ssub_4RegClass,
4904  nullptr
4905};
4906
4907static const TargetRegisterClass *const DQuadSpc_with_dsub_0_in_DPR_8Superclasses[] = {
4908  &ARM::DTripleSpcRegClass,
4909  &ARM::DTripleSpc_with_ssub_0RegClass,
4910  &ARM::DTripleSpc_with_ssub_4RegClass,
4911  &ARM::DTripleSpc_with_ssub_8RegClass,
4912  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
4913  &ARM::DQuadSpcRegClass,
4914  &ARM::DQuadSpc_with_ssub_0RegClass,
4915  &ARM::DQuadSpc_with_ssub_4RegClass,
4916  &ARM::DQuadSpc_with_ssub_8RegClass,
4917  nullptr
4918};
4919
4920static const TargetRegisterClass *const DQuadSpc_with_dsub_2_in_DPR_8Superclasses[] = {
4921  &ARM::DTripleSpcRegClass,
4922  &ARM::DTripleSpc_with_ssub_0RegClass,
4923  &ARM::DTripleSpc_with_ssub_4RegClass,
4924  &ARM::DTripleSpc_with_ssub_8RegClass,
4925  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
4926  &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
4927  &ARM::DQuadSpcRegClass,
4928  &ARM::DQuadSpc_with_ssub_0RegClass,
4929  &ARM::DQuadSpc_with_ssub_4RegClass,
4930  &ARM::DQuadSpc_with_ssub_8RegClass,
4931  &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass,
4932  nullptr
4933};
4934
4935static const TargetRegisterClass *const DQuadSpc_with_dsub_4_in_DPR_8Superclasses[] = {
4936  &ARM::DTripleSpcRegClass,
4937  &ARM::DTripleSpc_with_ssub_0RegClass,
4938  &ARM::DTripleSpc_with_ssub_4RegClass,
4939  &ARM::DTripleSpc_with_ssub_8RegClass,
4940  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
4941  &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
4942  &ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClass,
4943  &ARM::DQuadSpcRegClass,
4944  &ARM::DQuadSpc_with_ssub_0RegClass,
4945  &ARM::DQuadSpc_with_ssub_4RegClass,
4946  &ARM::DQuadSpc_with_ssub_8RegClass,
4947  &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass,
4948  &ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClass,
4949  nullptr
4950};
4951
4952static const TargetRegisterClass *const DQuad_with_ssub_0Superclasses[] = {
4953  &ARM::DQuadRegClass,
4954  nullptr
4955};
4956
4957static const TargetRegisterClass *const DQuad_with_ssub_2Superclasses[] = {
4958  &ARM::DQuadRegClass,
4959  &ARM::DQuad_with_ssub_0RegClass,
4960  nullptr
4961};
4962
4963static const TargetRegisterClass *const QQPRSuperclasses[] = {
4964  &ARM::DQuadRegClass,
4965  nullptr
4966};
4967
4968static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
4969  &ARM::DQuadRegClass,
4970  nullptr
4971};
4972
4973static const TargetRegisterClass *const DQuad_with_ssub_4Superclasses[] = {
4974  &ARM::DQuadRegClass,
4975  &ARM::DQuad_with_ssub_0RegClass,
4976  &ARM::DQuad_with_ssub_2RegClass,
4977  nullptr
4978};
4979
4980static const TargetRegisterClass *const DQuad_with_ssub_6Superclasses[] = {
4981  &ARM::DQuadRegClass,
4982  &ARM::DQuad_with_ssub_0RegClass,
4983  &ARM::DQuad_with_ssub_2RegClass,
4984  &ARM::DQuad_with_ssub_4RegClass,
4985  nullptr
4986};
4987
4988static const TargetRegisterClass *const DQuad_with_dsub_0_in_DPR_8Superclasses[] = {
4989  &ARM::DQuadRegClass,
4990  &ARM::DQuad_with_ssub_0RegClass,
4991  &ARM::DQuad_with_ssub_2RegClass,
4992  &ARM::DQuad_with_ssub_4RegClass,
4993  &ARM::DQuad_with_ssub_6RegClass,
4994  nullptr
4995};
4996
4997static const TargetRegisterClass *const DQuad_with_qsub_0_in_QPR_VFP2Superclasses[] = {
4998  &ARM::DQuadRegClass,
4999  &ARM::DQuad_with_ssub_0RegClass,
5000  &ARM::DQuad_with_ssub_2RegClass,
5001  &ARM::QQPRRegClass,
5002  nullptr
5003};
5004
5005static const TargetRegisterClass *const DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
5006  &ARM::DQuadRegClass,
5007  &ARM::DQuad_with_ssub_0RegClass,
5008  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5009  nullptr
5010};
5011
5012static const TargetRegisterClass *const DQuad_with_dsub_1_in_DPR_8Superclasses[] = {
5013  &ARM::DQuadRegClass,
5014  &ARM::DQuad_with_ssub_0RegClass,
5015  &ARM::DQuad_with_ssub_2RegClass,
5016  &ARM::DQuad_with_ssub_4RegClass,
5017  &ARM::DQuad_with_ssub_6RegClass,
5018  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5019  nullptr
5020};
5021
5022static const TargetRegisterClass *const DQuad_with_qsub_1_in_QPR_VFP2Superclasses[] = {
5023  &ARM::DQuadRegClass,
5024  &ARM::DQuad_with_ssub_0RegClass,
5025  &ARM::DQuad_with_ssub_2RegClass,
5026  &ARM::QQPRRegClass,
5027  &ARM::DQuad_with_ssub_4RegClass,
5028  &ARM::DQuad_with_ssub_6RegClass,
5029  &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
5030  nullptr
5031};
5032
5033static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Superclasses[] = {
5034  &ARM::DQuadRegClass,
5035  &ARM::DQuad_with_ssub_0RegClass,
5036  &ARM::DQuad_with_ssub_2RegClass,
5037  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5038  &ARM::DQuad_with_ssub_4RegClass,
5039  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5040  nullptr
5041};
5042
5043static const TargetRegisterClass *const DQuad_with_dsub_2_in_DPR_8Superclasses[] = {
5044  &ARM::DQuadRegClass,
5045  &ARM::DQuad_with_ssub_0RegClass,
5046  &ARM::DQuad_with_ssub_2RegClass,
5047  &ARM::DQuad_with_ssub_4RegClass,
5048  &ARM::DQuad_with_ssub_6RegClass,
5049  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5050  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5051  nullptr
5052};
5053
5054static const TargetRegisterClass *const DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
5055  &ARM::DQuadRegClass,
5056  &ARM::DQuad_with_ssub_0RegClass,
5057  &ARM::DQuad_with_ssub_2RegClass,
5058  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5059  &ARM::DQuad_with_ssub_4RegClass,
5060  &ARM::DQuad_with_ssub_6RegClass,
5061  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5062  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
5063  nullptr
5064};
5065
5066static const TargetRegisterClass *const DQuad_with_dsub_3_in_DPR_8Superclasses[] = {
5067  &ARM::DQuadRegClass,
5068  &ARM::DQuad_with_ssub_0RegClass,
5069  &ARM::DQuad_with_ssub_2RegClass,
5070  &ARM::DQuad_with_ssub_4RegClass,
5071  &ARM::DQuad_with_ssub_6RegClass,
5072  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5073  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5074  &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
5075  nullptr
5076};
5077
5078static const TargetRegisterClass *const DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
5079  &ARM::DQuadRegClass,
5080  &ARM::DQuad_with_ssub_0RegClass,
5081  &ARM::DQuad_with_ssub_2RegClass,
5082  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5083  &ARM::DQuad_with_ssub_4RegClass,
5084  &ARM::DQuad_with_ssub_6RegClass,
5085  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5086  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5087  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
5088  &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5089  nullptr
5090};
5091
5092static const TargetRegisterClass *const DQuad_with_qsub_0_in_QPR_8Superclasses[] = {
5093  &ARM::DQuadRegClass,
5094  &ARM::DQuad_with_ssub_0RegClass,
5095  &ARM::DQuad_with_ssub_2RegClass,
5096  &ARM::QQPRRegClass,
5097  &ARM::DQuad_with_ssub_4RegClass,
5098  &ARM::DQuad_with_ssub_6RegClass,
5099  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5100  &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
5101  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5102  &ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClass,
5103  nullptr
5104};
5105
5106static const TargetRegisterClass *const DQuad_with_qsub_1_in_QPR_8Superclasses[] = {
5107  &ARM::DQuadRegClass,
5108  &ARM::DQuad_with_ssub_0RegClass,
5109  &ARM::DQuad_with_ssub_2RegClass,
5110  &ARM::QQPRRegClass,
5111  &ARM::DQuad_with_ssub_4RegClass,
5112  &ARM::DQuad_with_ssub_6RegClass,
5113  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5114  &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
5115  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5116  &ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClass,
5117  &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
5118  &ARM::DQuad_with_dsub_3_in_DPR_8RegClass,
5119  &ARM::DQuad_with_qsub_0_in_QPR_8RegClass,
5120  nullptr
5121};
5122
5123static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses[] = {
5124  &ARM::DQuadRegClass,
5125  &ARM::DQuad_with_ssub_0RegClass,
5126  &ARM::DQuad_with_ssub_2RegClass,
5127  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5128  &ARM::DQuad_with_ssub_4RegClass,
5129  &ARM::DQuad_with_ssub_6RegClass,
5130  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5131  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5132  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5133  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
5134  &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
5135  &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5136  &ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5137  nullptr
5138};
5139
5140static const TargetRegisterClass *const DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
5141  &ARM::DQuadRegClass,
5142  &ARM::DQuad_with_ssub_0RegClass,
5143  &ARM::DQuad_with_ssub_2RegClass,
5144  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5145  &ARM::DQuad_with_ssub_4RegClass,
5146  &ARM::DQuad_with_ssub_6RegClass,
5147  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
5148  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5149  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
5150  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
5151  &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
5152  &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5153  &ARM::DQuad_with_dsub_3_in_DPR_8RegClass,
5154  &ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
5155  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass,
5156  nullptr
5157};
5158
5159static const TargetRegisterClass *const QQQQPR_with_ssub_0Superclasses[] = {
5160  &ARM::QQQQPRRegClass,
5161  nullptr
5162};
5163
5164static const TargetRegisterClass *const QQQQPR_with_ssub_4Superclasses[] = {
5165  &ARM::QQQQPRRegClass,
5166  &ARM::QQQQPR_with_ssub_0RegClass,
5167  nullptr
5168};
5169
5170static const TargetRegisterClass *const QQQQPR_with_ssub_8Superclasses[] = {
5171  &ARM::QQQQPRRegClass,
5172  &ARM::QQQQPR_with_ssub_0RegClass,
5173  &ARM::QQQQPR_with_ssub_4RegClass,
5174  nullptr
5175};
5176
5177static const TargetRegisterClass *const QQQQPR_with_ssub_12Superclasses[] = {
5178  &ARM::QQQQPRRegClass,
5179  &ARM::QQQQPR_with_ssub_0RegClass,
5180  &ARM::QQQQPR_with_ssub_4RegClass,
5181  &ARM::QQQQPR_with_ssub_8RegClass,
5182  nullptr
5183};
5184
5185static const TargetRegisterClass *const QQQQPR_with_dsub_0_in_DPR_8Superclasses[] = {
5186  &ARM::QQQQPRRegClass,
5187  &ARM::QQQQPR_with_ssub_0RegClass,
5188  &ARM::QQQQPR_with_ssub_4RegClass,
5189  &ARM::QQQQPR_with_ssub_8RegClass,
5190  &ARM::QQQQPR_with_ssub_12RegClass,
5191  nullptr
5192};
5193
5194static const TargetRegisterClass *const QQQQPR_with_dsub_2_in_DPR_8Superclasses[] = {
5195  &ARM::QQQQPRRegClass,
5196  &ARM::QQQQPR_with_ssub_0RegClass,
5197  &ARM::QQQQPR_with_ssub_4RegClass,
5198  &ARM::QQQQPR_with_ssub_8RegClass,
5199  &ARM::QQQQPR_with_ssub_12RegClass,
5200  &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass,
5201  nullptr
5202};
5203
5204static const TargetRegisterClass *const QQQQPR_with_dsub_4_in_DPR_8Superclasses[] = {
5205  &ARM::QQQQPRRegClass,
5206  &ARM::QQQQPR_with_ssub_0RegClass,
5207  &ARM::QQQQPR_with_ssub_4RegClass,
5208  &ARM::QQQQPR_with_ssub_8RegClass,
5209  &ARM::QQQQPR_with_ssub_12RegClass,
5210  &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass,
5211  &ARM::QQQQPR_with_dsub_2_in_DPR_8RegClass,
5212  nullptr
5213};
5214
5215static const TargetRegisterClass *const QQQQPR_with_dsub_6_in_DPR_8Superclasses[] = {
5216  &ARM::QQQQPRRegClass,
5217  &ARM::QQQQPR_with_ssub_0RegClass,
5218  &ARM::QQQQPR_with_ssub_4RegClass,
5219  &ARM::QQQQPR_with_ssub_8RegClass,
5220  &ARM::QQQQPR_with_ssub_12RegClass,
5221  &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass,
5222  &ARM::QQQQPR_with_dsub_2_in_DPR_8RegClass,
5223  &ARM::QQQQPR_with_dsub_4_in_DPR_8RegClass,
5224  nullptr
5225};
5226
5227
5228static inline unsigned HPRAltOrderSelect(const MachineFunction &MF) {
5229    return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(MF);
5230  }
5231
5232static ArrayRef<MCPhysReg> HPRGetRawAllocationOrder(const MachineFunction &MF) {
5233  static const MCPhysReg AltOrder1[] = { ARM::S0, ARM::S2, ARM::S4, ARM::S6, ARM::S8, ARM::S10, ARM::S12, ARM::S14, ARM::S16, ARM::S18, ARM::S20, ARM::S22, ARM::S24, ARM::S26, ARM::S28, ARM::S30, ARM::S1, ARM::S3, ARM::S5, ARM::S7, ARM::S9, ARM::S11, ARM::S13, ARM::S15, ARM::S17, ARM::S19, ARM::S21, ARM::S23, ARM::S25, ARM::S27, ARM::S29, ARM::S31 };
5234  static const MCPhysReg AltOrder2[] = { ARM::S0, ARM::S4, ARM::S8, ARM::S12, ARM::S16, ARM::S20, ARM::S24, ARM::S28, ARM::S2, ARM::S6, ARM::S10, ARM::S14, ARM::S18, ARM::S22, ARM::S26, ARM::S30, ARM::S1, ARM::S5, ARM::S9, ARM::S13, ARM::S17, ARM::S21, ARM::S25, ARM::S29, ARM::S3, ARM::S7, ARM::S11, ARM::S15, ARM::S19, ARM::S23, ARM::S27, ARM::S31 };
5235  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::HPRRegClassID];
5236  const ArrayRef<MCPhysReg> Order[] = {
5237    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5238    makeArrayRef(AltOrder1),
5239    makeArrayRef(AltOrder2)
5240  };
5241  const unsigned Select = HPRAltOrderSelect(MF);
5242  assert(Select < 3);
5243  return Order[Select];
5244}
5245
5246static inline unsigned SPRAltOrderSelect(const MachineFunction &MF) {
5247    return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(MF);
5248  }
5249
5250static ArrayRef<MCPhysReg> SPRGetRawAllocationOrder(const MachineFunction &MF) {
5251  static const MCPhysReg AltOrder1[] = { ARM::S0, ARM::S2, ARM::S4, ARM::S6, ARM::S8, ARM::S10, ARM::S12, ARM::S14, ARM::S16, ARM::S18, ARM::S20, ARM::S22, ARM::S24, ARM::S26, ARM::S28, ARM::S30, ARM::S1, ARM::S3, ARM::S5, ARM::S7, ARM::S9, ARM::S11, ARM::S13, ARM::S15, ARM::S17, ARM::S19, ARM::S21, ARM::S23, ARM::S25, ARM::S27, ARM::S29, ARM::S31 };
5252  static const MCPhysReg AltOrder2[] = { ARM::S0, ARM::S4, ARM::S8, ARM::S12, ARM::S16, ARM::S20, ARM::S24, ARM::S28, ARM::S2, ARM::S6, ARM::S10, ARM::S14, ARM::S18, ARM::S22, ARM::S26, ARM::S30, ARM::S1, ARM::S5, ARM::S9, ARM::S13, ARM::S17, ARM::S21, ARM::S25, ARM::S29, ARM::S3, ARM::S7, ARM::S11, ARM::S15, ARM::S19, ARM::S23, ARM::S27, ARM::S31 };
5253  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::SPRRegClassID];
5254  const ArrayRef<MCPhysReg> Order[] = {
5255    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5256    makeArrayRef(AltOrder1),
5257    makeArrayRef(AltOrder2)
5258  };
5259  const unsigned Select = SPRAltOrderSelect(MF);
5260  assert(Select < 3);
5261  return Order[Select];
5262}
5263
5264static inline unsigned GPRAltOrderSelect(const MachineFunction &MF) {
5265      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
5266  }
5267
5268static ArrayRef<MCPhysReg> GPRGetRawAllocationOrder(const MachineFunction &MF) {
5269  static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::PC };
5270  static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5271  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRRegClassID];
5272  const ArrayRef<MCPhysReg> Order[] = {
5273    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5274    makeArrayRef(AltOrder1),
5275    makeArrayRef(AltOrder2)
5276  };
5277  const unsigned Select = GPRAltOrderSelect(MF);
5278  assert(Select < 3);
5279  return Order[Select];
5280}
5281
5282static inline unsigned GPRwithAPSRAltOrderSelect(const MachineFunction &MF) {
5283      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
5284  }
5285
5286static ArrayRef<MCPhysReg> GPRwithAPSRGetRawAllocationOrder(const MachineFunction &MF) {
5287  static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP };
5288  static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5289  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRwithAPSRRegClassID];
5290  const ArrayRef<MCPhysReg> Order[] = {
5291    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5292    makeArrayRef(AltOrder1),
5293    makeArrayRef(AltOrder2)
5294  };
5295  const unsigned Select = GPRwithAPSRAltOrderSelect(MF);
5296  assert(Select < 3);
5297  return Order[Select];
5298}
5299
5300static inline unsigned GPRnopcAltOrderSelect(const MachineFunction &MF) {
5301      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
5302  }
5303
5304static ArrayRef<MCPhysReg> GPRnopcGetRawAllocationOrder(const MachineFunction &MF) {
5305  static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP };
5306  static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5307  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRnopcRegClassID];
5308  const ArrayRef<MCPhysReg> Order[] = {
5309    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5310    makeArrayRef(AltOrder1),
5311    makeArrayRef(AltOrder2)
5312  };
5313  const unsigned Select = GPRnopcAltOrderSelect(MF);
5314  assert(Select < 3);
5315  return Order[Select];
5316}
5317
5318static inline unsigned rGPRAltOrderSelect(const MachineFunction &MF) {
5319      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
5320  }
5321
5322static ArrayRef<MCPhysReg> rGPRGetRawAllocationOrder(const MachineFunction &MF) {
5323  static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12 };
5324  static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5325  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::rGPRRegClassID];
5326  const ArrayRef<MCPhysReg> Order[] = {
5327    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5328    makeArrayRef(AltOrder1),
5329    makeArrayRef(AltOrder2)
5330  };
5331  const unsigned Select = rGPRAltOrderSelect(MF);
5332  assert(Select < 3);
5333  return Order[Select];
5334}
5335
5336static inline unsigned tcGPRAltOrderSelect(const MachineFunction &MF) {
5337      return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
5338  }
5339
5340static ArrayRef<MCPhysReg> tcGPRGetRawAllocationOrder(const MachineFunction &MF) {
5341  static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
5342  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tcGPRRegClassID];
5343  const ArrayRef<MCPhysReg> Order[] = {
5344    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5345    makeArrayRef(AltOrder1)
5346  };
5347  const unsigned Select = tcGPRAltOrderSelect(MF);
5348  assert(Select < 2);
5349  return Order[Select];
5350}
5351
5352static inline unsigned tGPR_and_tcGPRAltOrderSelect(const MachineFunction &MF) {
5353      return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
5354  }
5355
5356static ArrayRef<MCPhysReg> tGPR_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) {
5357  static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
5358  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPR_and_tcGPRRegClassID];
5359  const ArrayRef<MCPhysReg> Order[] = {
5360    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5361    makeArrayRef(AltOrder1)
5362  };
5363  const unsigned Select = tGPR_and_tcGPRAltOrderSelect(MF);
5364  assert(Select < 2);
5365  return Order[Select];
5366}
5367
5368static inline unsigned hGPR_and_tcGPRAltOrderSelect(const MachineFunction &MF) {
5369      return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
5370  }
5371
5372static ArrayRef<MCPhysReg> hGPR_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) {
5373  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::hGPR_and_tcGPRRegClassID];
5374  const ArrayRef<MCPhysReg> Order[] = {
5375    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5376    ArrayRef<MCPhysReg>()
5377  };
5378  const unsigned Select = hGPR_and_tcGPRAltOrderSelect(MF);
5379  assert(Select < 2);
5380  return Order[Select];
5381}
5382
5383static inline unsigned DPRAltOrderSelect(const MachineFunction &MF) {
5384    return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(MF);
5385  }
5386
5387static ArrayRef<MCPhysReg> DPRGetRawAllocationOrder(const MachineFunction &MF) {
5388  static const MCPhysReg AltOrder1[] = { ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15 };
5389  static const MCPhysReg AltOrder2[] = { ARM::D16, ARM::D18, ARM::D20, ARM::D22, ARM::D24, ARM::D26, ARM::D28, ARM::D30, ARM::D0, ARM::D2, ARM::D4, ARM::D6, ARM::D8, ARM::D10, ARM::D12, ARM::D14, ARM::D17, ARM::D19, ARM::D21, ARM::D23, ARM::D25, ARM::D27, ARM::D29, ARM::D31, ARM::D1, ARM::D3, ARM::D5, ARM::D7, ARM::D9, ARM::D11, ARM::D13, ARM::D15 };
5390  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPRRegClassID];
5391  const ArrayRef<MCPhysReg> Order[] = {
5392    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5393    makeArrayRef(AltOrder1),
5394    makeArrayRef(AltOrder2)
5395  };
5396  const unsigned Select = DPRAltOrderSelect(MF);
5397  assert(Select < 3);
5398  return Order[Select];
5399}
5400
5401static inline unsigned DPairAltOrderSelect(const MachineFunction &MF) { return 1; }
5402
5403static ArrayRef<MCPhysReg> DPairGetRawAllocationOrder(const MachineFunction &MF) {
5404  static const MCPhysReg AltOrder1[] = { ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D17_D18, ARM::D19_D20, ARM::D21_D22, ARM::D23_D24, ARM::D25_D26, ARM::D27_D28, ARM::D29_D30, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14, ARM::D15_D16 };
5405  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPairRegClassID];
5406  const ArrayRef<MCPhysReg> Order[] = {
5407    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5408    makeArrayRef(AltOrder1)
5409  };
5410  const unsigned Select = DPairAltOrderSelect(MF);
5411  assert(Select < 2);
5412  return Order[Select];
5413}
5414
5415static inline unsigned DPair_with_ssub_0AltOrderSelect(const MachineFunction &MF) { return 1; }
5416
5417static ArrayRef<MCPhysReg> DPair_with_ssub_0GetRawAllocationOrder(const MachineFunction &MF) {
5418  static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14, ARM::D15_D16 };
5419  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_ssub_0RegClassID];
5420  const ArrayRef<MCPhysReg> Order[] = {
5421    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5422    makeArrayRef(AltOrder1)
5423  };
5424  const unsigned Select = DPair_with_ssub_0AltOrderSelect(MF);
5425  assert(Select < 2);
5426  return Order[Select];
5427}
5428
5429static inline unsigned QPRAltOrderSelect(const MachineFunction &MF) { return 1; }
5430
5431static ArrayRef<MCPhysReg> QPRGetRawAllocationOrder(const MachineFunction &MF) {
5432  static const MCPhysReg AltOrder1[] = { ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7 };
5433  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QPRRegClassID];
5434  const ArrayRef<MCPhysReg> Order[] = {
5435    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5436    makeArrayRef(AltOrder1)
5437  };
5438  const unsigned Select = QPRAltOrderSelect(MF);
5439  assert(Select < 2);
5440  return Order[Select];
5441}
5442
5443static inline unsigned DPair_with_ssub_2AltOrderSelect(const MachineFunction &MF) { return 1; }
5444
5445static ArrayRef<MCPhysReg> DPair_with_ssub_2GetRawAllocationOrder(const MachineFunction &MF) {
5446  static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14 };
5447  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_ssub_2RegClassID];
5448  const ArrayRef<MCPhysReg> Order[] = {
5449    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5450    makeArrayRef(AltOrder1)
5451  };
5452  const unsigned Select = DPair_with_ssub_2AltOrderSelect(MF);
5453  assert(Select < 2);
5454  return Order[Select];
5455}
5456
5457static inline unsigned DPair_with_dsub_0_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
5458
5459static ArrayRef<MCPhysReg> DPair_with_dsub_0_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
5460  static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8 };
5461  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_dsub_0_in_DPR_8RegClassID];
5462  const ArrayRef<MCPhysReg> Order[] = {
5463    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5464    makeArrayRef(AltOrder1)
5465  };
5466  const unsigned Select = DPair_with_dsub_0_in_DPR_8AltOrderSelect(MF);
5467  assert(Select < 2);
5468  return Order[Select];
5469}
5470
5471static inline unsigned DPair_with_dsub_1_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
5472
5473static ArrayRef<MCPhysReg> DPair_with_dsub_1_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
5474  static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6 };
5475  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_dsub_1_in_DPR_8RegClassID];
5476  const ArrayRef<MCPhysReg> Order[] = {
5477    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5478    makeArrayRef(AltOrder1)
5479  };
5480  const unsigned Select = DPair_with_dsub_1_in_DPR_8AltOrderSelect(MF);
5481  assert(Select < 2);
5482  return Order[Select];
5483}
5484
5485static inline unsigned QQPRAltOrderSelect(const MachineFunction &MF) { return 1; }
5486
5487static ArrayRef<MCPhysReg> QQPRGetRawAllocationOrder(const MachineFunction &MF) {
5488  static const MCPhysReg AltOrder1[] = { ARM::Q8_Q9, ARM::Q9_Q10, ARM::Q10_Q11, ARM::Q11_Q12, ARM::Q12_Q13, ARM::Q13_Q14, ARM::Q14_Q15, ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8 };
5489  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQPRRegClassID];
5490  const ArrayRef<MCPhysReg> Order[] = {
5491    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5492    makeArrayRef(AltOrder1)
5493  };
5494  const unsigned Select = QQPRAltOrderSelect(MF);
5495  assert(Select < 2);
5496  return Order[Select];
5497}
5498
5499static inline unsigned DQuad_with_qsub_0_in_QPR_VFP2AltOrderSelect(const MachineFunction &MF) { return 1; }
5500
5501static ArrayRef<MCPhysReg> DQuad_with_qsub_0_in_QPR_VFP2GetRawAllocationOrder(const MachineFunction &MF) {
5502  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8 };
5503  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClassID];
5504  const ArrayRef<MCPhysReg> Order[] = {
5505    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5506    makeArrayRef(AltOrder1)
5507  };
5508  const unsigned Select = DQuad_with_qsub_0_in_QPR_VFP2AltOrderSelect(MF);
5509  assert(Select < 2);
5510  return Order[Select];
5511}
5512
5513static inline unsigned DQuad_with_qsub_1_in_QPR_VFP2AltOrderSelect(const MachineFunction &MF) { return 1; }
5514
5515static ArrayRef<MCPhysReg> DQuad_with_qsub_1_in_QPR_VFP2GetRawAllocationOrder(const MachineFunction &MF) {
5516  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 };
5517  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClassID];
5518  const ArrayRef<MCPhysReg> Order[] = {
5519    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5520    makeArrayRef(AltOrder1)
5521  };
5522  const unsigned Select = DQuad_with_qsub_1_in_QPR_VFP2AltOrderSelect(MF);
5523  assert(Select < 2);
5524  return Order[Select];
5525}
5526
5527static inline unsigned DQuad_with_qsub_0_in_QPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
5528
5529static ArrayRef<MCPhysReg> DQuad_with_qsub_0_in_QPR_8GetRawAllocationOrder(const MachineFunction &MF) {
5530  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4 };
5531  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_0_in_QPR_8RegClassID];
5532  const ArrayRef<MCPhysReg> Order[] = {
5533    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5534    makeArrayRef(AltOrder1)
5535  };
5536  const unsigned Select = DQuad_with_qsub_0_in_QPR_8AltOrderSelect(MF);
5537  assert(Select < 2);
5538  return Order[Select];
5539}
5540
5541static inline unsigned DQuad_with_qsub_1_in_QPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
5542
5543static ArrayRef<MCPhysReg> DQuad_with_qsub_1_in_QPR_8GetRawAllocationOrder(const MachineFunction &MF) {
5544  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3 };
5545  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_1_in_QPR_8RegClassID];
5546  const ArrayRef<MCPhysReg> Order[] = {
5547    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5548    makeArrayRef(AltOrder1)
5549  };
5550  const unsigned Select = DQuad_with_qsub_1_in_QPR_8AltOrderSelect(MF);
5551  assert(Select < 2);
5552  return Order[Select];
5553}
5554
5555static inline unsigned QQQQPRAltOrderSelect(const MachineFunction &MF) { return 1; }
5556
5557static ArrayRef<MCPhysReg> QQQQPRGetRawAllocationOrder(const MachineFunction &MF) {
5558  static const MCPhysReg AltOrder1[] = { ARM::Q8_Q9_Q10_Q11, ARM::Q9_Q10_Q11_Q12, ARM::Q10_Q11_Q12_Q13, ARM::Q11_Q12_Q13_Q14, ARM::Q12_Q13_Q14_Q15, ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10 };
5559  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPRRegClassID];
5560  const ArrayRef<MCPhysReg> Order[] = {
5561    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5562    makeArrayRef(AltOrder1)
5563  };
5564  const unsigned Select = QQQQPRAltOrderSelect(MF);
5565  assert(Select < 2);
5566  return Order[Select];
5567}
5568
5569static inline unsigned QQQQPR_with_ssub_0AltOrderSelect(const MachineFunction &MF) { return 1; }
5570
5571static ArrayRef<MCPhysReg> QQQQPR_with_ssub_0GetRawAllocationOrder(const MachineFunction &MF) {
5572  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10 };
5573  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_0RegClassID];
5574  const ArrayRef<MCPhysReg> Order[] = {
5575    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5576    makeArrayRef(AltOrder1)
5577  };
5578  const unsigned Select = QQQQPR_with_ssub_0AltOrderSelect(MF);
5579  assert(Select < 2);
5580  return Order[Select];
5581}
5582
5583static inline unsigned QQQQPR_with_ssub_4AltOrderSelect(const MachineFunction &MF) { return 1; }
5584
5585static ArrayRef<MCPhysReg> QQQQPR_with_ssub_4GetRawAllocationOrder(const MachineFunction &MF) {
5586  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9 };
5587  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_4RegClassID];
5588  const ArrayRef<MCPhysReg> Order[] = {
5589    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5590    makeArrayRef(AltOrder1)
5591  };
5592  const unsigned Select = QQQQPR_with_ssub_4AltOrderSelect(MF);
5593  assert(Select < 2);
5594  return Order[Select];
5595}
5596
5597static inline unsigned QQQQPR_with_ssub_8AltOrderSelect(const MachineFunction &MF) { return 1; }
5598
5599static ArrayRef<MCPhysReg> QQQQPR_with_ssub_8GetRawAllocationOrder(const MachineFunction &MF) {
5600  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8 };
5601  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_8RegClassID];
5602  const ArrayRef<MCPhysReg> Order[] = {
5603    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5604    makeArrayRef(AltOrder1)
5605  };
5606  const unsigned Select = QQQQPR_with_ssub_8AltOrderSelect(MF);
5607  assert(Select < 2);
5608  return Order[Select];
5609}
5610
5611static inline unsigned QQQQPR_with_ssub_12AltOrderSelect(const MachineFunction &MF) { return 1; }
5612
5613static ArrayRef<MCPhysReg> QQQQPR_with_ssub_12GetRawAllocationOrder(const MachineFunction &MF) {
5614  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 };
5615  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_12RegClassID];
5616  const ArrayRef<MCPhysReg> Order[] = {
5617    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5618    makeArrayRef(AltOrder1)
5619  };
5620  const unsigned Select = QQQQPR_with_ssub_12AltOrderSelect(MF);
5621  assert(Select < 2);
5622  return Order[Select];
5623}
5624
5625static inline unsigned QQQQPR_with_dsub_0_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
5626
5627static ArrayRef<MCPhysReg> QQQQPR_with_dsub_0_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
5628  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6 };
5629  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_0_in_DPR_8RegClassID];
5630  const ArrayRef<MCPhysReg> Order[] = {
5631    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5632    makeArrayRef(AltOrder1)
5633  };
5634  const unsigned Select = QQQQPR_with_dsub_0_in_DPR_8AltOrderSelect(MF);
5635  assert(Select < 2);
5636  return Order[Select];
5637}
5638
5639static inline unsigned QQQQPR_with_dsub_2_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
5640
5641static ArrayRef<MCPhysReg> QQQQPR_with_dsub_2_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
5642  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5 };
5643  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_2_in_DPR_8RegClassID];
5644  const ArrayRef<MCPhysReg> Order[] = {
5645    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5646    makeArrayRef(AltOrder1)
5647  };
5648  const unsigned Select = QQQQPR_with_dsub_2_in_DPR_8AltOrderSelect(MF);
5649  assert(Select < 2);
5650  return Order[Select];
5651}
5652
5653static inline unsigned QQQQPR_with_dsub_4_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
5654
5655static ArrayRef<MCPhysReg> QQQQPR_with_dsub_4_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
5656  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4 };
5657  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_4_in_DPR_8RegClassID];
5658  const ArrayRef<MCPhysReg> Order[] = {
5659    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5660    makeArrayRef(AltOrder1)
5661  };
5662  const unsigned Select = QQQQPR_with_dsub_4_in_DPR_8AltOrderSelect(MF);
5663  assert(Select < 2);
5664  return Order[Select];
5665}
5666
5667static inline unsigned QQQQPR_with_dsub_6_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }
5668
5669static ArrayRef<MCPhysReg> QQQQPR_with_dsub_6_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
5670  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3 };
5671  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_6_in_DPR_8RegClassID];
5672  const ArrayRef<MCPhysReg> Order[] = {
5673    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5674    makeArrayRef(AltOrder1)
5675  };
5676  const unsigned Select = QQQQPR_with_dsub_6_in_DPR_8AltOrderSelect(MF);
5677  assert(Select < 2);
5678  return Order[Select];
5679}
5680
5681namespace ARM {   // Register class instances
5682  extern const TargetRegisterClass HPRRegClass = {
5683    &ARMMCRegisterClasses[HPRRegClassID],
5684    HPRSubClassMask,
5685    SuperRegIdxSeqs + 14,
5686    LaneBitmask(0x00000001),
5687    0,
5688    false, /* HasDisjunctSubRegs */
5689    false, /* CoveredBySubRegs */
5690    NullRegClasses,
5691    HPRGetRawAllocationOrder
5692  };
5693
5694  extern const TargetRegisterClass SPRRegClass = {
5695    &ARMMCRegisterClasses[SPRRegClassID],
5696    SPRSubClassMask,
5697    SuperRegIdxSeqs + 14,
5698    LaneBitmask(0x00000001),
5699    0,
5700    false, /* HasDisjunctSubRegs */
5701    false, /* CoveredBySubRegs */
5702    SPRSuperclasses,
5703    SPRGetRawAllocationOrder
5704  };
5705
5706  extern const TargetRegisterClass GPRRegClass = {
5707    &ARMMCRegisterClasses[GPRRegClassID],
5708    GPRSubClassMask,
5709    SuperRegIdxSeqs + 11,
5710    LaneBitmask(0x00000001),
5711    0,
5712    false, /* HasDisjunctSubRegs */
5713    true, /* CoveredBySubRegs */
5714    NullRegClasses,
5715    GPRGetRawAllocationOrder
5716  };
5717
5718  extern const TargetRegisterClass GPRwithAPSRRegClass = {
5719    &ARMMCRegisterClasses[GPRwithAPSRRegClassID],
5720    GPRwithAPSRSubClassMask,
5721    SuperRegIdxSeqs + 11,
5722    LaneBitmask(0x00000001),
5723    0,
5724    false, /* HasDisjunctSubRegs */
5725    true, /* CoveredBySubRegs */
5726    NullRegClasses,
5727    GPRwithAPSRGetRawAllocationOrder
5728  };
5729
5730  extern const TargetRegisterClass SPR_8RegClass = {
5731    &ARMMCRegisterClasses[SPR_8RegClassID],
5732    SPR_8SubClassMask,
5733    SuperRegIdxSeqs + 14,
5734    LaneBitmask(0x00000001),
5735    0,
5736    false, /* HasDisjunctSubRegs */
5737    false, /* CoveredBySubRegs */
5738    SPR_8Superclasses,
5739    nullptr
5740  };
5741
5742  extern const TargetRegisterClass GPRnopcRegClass = {
5743    &ARMMCRegisterClasses[GPRnopcRegClassID],
5744    GPRnopcSubClassMask,
5745    SuperRegIdxSeqs + 11,
5746    LaneBitmask(0x00000001),
5747    0,
5748    false, /* HasDisjunctSubRegs */
5749    true, /* CoveredBySubRegs */
5750    GPRnopcSuperclasses,
5751    GPRnopcGetRawAllocationOrder
5752  };
5753
5754  extern const TargetRegisterClass rGPRRegClass = {
5755    &ARMMCRegisterClasses[rGPRRegClassID],
5756    rGPRSubClassMask,
5757    SuperRegIdxSeqs + 11,
5758    LaneBitmask(0x00000001),
5759    0,
5760    false, /* HasDisjunctSubRegs */
5761    true, /* CoveredBySubRegs */
5762    rGPRSuperclasses,
5763    rGPRGetRawAllocationOrder
5764  };
5765
5766  extern const TargetRegisterClass tGPRwithpcRegClass = {
5767    &ARMMCRegisterClasses[tGPRwithpcRegClassID],
5768    tGPRwithpcSubClassMask,
5769    SuperRegIdxSeqs + 11,
5770    LaneBitmask(0x00000001),
5771    0,
5772    false, /* HasDisjunctSubRegs */
5773    true, /* CoveredBySubRegs */
5774    tGPRwithpcSuperclasses,
5775    nullptr
5776  };
5777
5778  extern const TargetRegisterClass hGPRRegClass = {
5779    &ARMMCRegisterClasses[hGPRRegClassID],
5780    hGPRSubClassMask,
5781    SuperRegIdxSeqs + 11,
5782    LaneBitmask(0x00000001),
5783    0,
5784    false, /* HasDisjunctSubRegs */
5785    true, /* CoveredBySubRegs */
5786    hGPRSuperclasses,
5787    nullptr
5788  };
5789
5790  extern const TargetRegisterClass tGPRRegClass = {
5791    &ARMMCRegisterClasses[tGPRRegClassID],
5792    tGPRSubClassMask,
5793    SuperRegIdxSeqs + 11,
5794    LaneBitmask(0x00000001),
5795    0,
5796    false, /* HasDisjunctSubRegs */
5797    true, /* CoveredBySubRegs */
5798    tGPRSuperclasses,
5799    nullptr
5800  };
5801
5802  extern const TargetRegisterClass GPRnopc_and_hGPRRegClass = {
5803    &ARMMCRegisterClasses[GPRnopc_and_hGPRRegClassID],
5804    GPRnopc_and_hGPRSubClassMask,
5805    SuperRegIdxSeqs + 11,
5806    LaneBitmask(0x00000001),
5807    0,
5808    false, /* HasDisjunctSubRegs */
5809    true, /* CoveredBySubRegs */
5810    GPRnopc_and_hGPRSuperclasses,
5811    nullptr
5812  };
5813
5814  extern const TargetRegisterClass hGPR_and_rGPRRegClass = {
5815    &ARMMCRegisterClasses[hGPR_and_rGPRRegClassID],
5816    hGPR_and_rGPRSubClassMask,
5817    SuperRegIdxSeqs + 11,
5818    LaneBitmask(0x00000001),
5819    0,
5820    false, /* HasDisjunctSubRegs */
5821    true, /* CoveredBySubRegs */
5822    hGPR_and_rGPRSuperclasses,
5823    nullptr
5824  };
5825
5826  extern const TargetRegisterClass tcGPRRegClass = {
5827    &ARMMCRegisterClasses[tcGPRRegClassID],
5828    tcGPRSubClassMask,
5829    SuperRegIdxSeqs + 11,
5830    LaneBitmask(0x00000001),
5831    0,
5832    false, /* HasDisjunctSubRegs */
5833    true, /* CoveredBySubRegs */
5834    tcGPRSuperclasses,
5835    tcGPRGetRawAllocationOrder
5836  };
5837
5838  extern const TargetRegisterClass tGPR_and_tcGPRRegClass = {
5839    &ARMMCRegisterClasses[tGPR_and_tcGPRRegClassID],
5840    tGPR_and_tcGPRSubClassMask,
5841    SuperRegIdxSeqs + 11,
5842    LaneBitmask(0x00000001),
5843    0,
5844    false, /* HasDisjunctSubRegs */
5845    true, /* CoveredBySubRegs */
5846    tGPR_and_tcGPRSuperclasses,
5847    tGPR_and_tcGPRGetRawAllocationOrder
5848  };
5849
5850  extern const TargetRegisterClass CCRRegClass = {
5851    &ARMMCRegisterClasses[CCRRegClassID],
5852    CCRSubClassMask,
5853    SuperRegIdxSeqs + 8,
5854    LaneBitmask(0x00000001),
5855    0,
5856    false, /* HasDisjunctSubRegs */
5857    true, /* CoveredBySubRegs */
5858    NullRegClasses,
5859    nullptr
5860  };
5861
5862  extern const TargetRegisterClass GPRspRegClass = {
5863    &ARMMCRegisterClasses[GPRspRegClassID],
5864    GPRspSubClassMask,
5865    SuperRegIdxSeqs + 12,
5866    LaneBitmask(0x00000001),
5867    0,
5868    false, /* HasDisjunctSubRegs */
5869    true, /* CoveredBySubRegs */
5870    GPRspSuperclasses,
5871    nullptr
5872  };
5873
5874  extern const TargetRegisterClass hGPR_and_tGPRwithpcRegClass = {
5875    &ARMMCRegisterClasses[hGPR_and_tGPRwithpcRegClassID],
5876    hGPR_and_tGPRwithpcSubClassMask,
5877    SuperRegIdxSeqs + 8,
5878    LaneBitmask(0x00000001),
5879    0,
5880    false, /* HasDisjunctSubRegs */
5881    true, /* CoveredBySubRegs */
5882    hGPR_and_tGPRwithpcSuperclasses,
5883    nullptr
5884  };
5885
5886  extern const TargetRegisterClass hGPR_and_tcGPRRegClass = {
5887    &ARMMCRegisterClasses[hGPR_and_tcGPRRegClassID],
5888    hGPR_and_tcGPRSubClassMask,
5889    SuperRegIdxSeqs + 9,
5890    LaneBitmask(0x00000001),
5891    0,
5892    false, /* HasDisjunctSubRegs */
5893    true, /* CoveredBySubRegs */
5894    hGPR_and_tcGPRSuperclasses,
5895    hGPR_and_tcGPRGetRawAllocationOrder
5896  };
5897
5898  extern const TargetRegisterClass DPRRegClass = {
5899    &ARMMCRegisterClasses[DPRRegClassID],
5900    DPRSubClassMask,
5901    SuperRegIdxSeqs + 0,
5902    LaneBitmask(0x0000000C),
5903    0,
5904    true, /* HasDisjunctSubRegs */
5905    false, /* CoveredBySubRegs */
5906    NullRegClasses,
5907    DPRGetRawAllocationOrder
5908  };
5909
5910  extern const TargetRegisterClass DPR_VFP2RegClass = {
5911    &ARMMCRegisterClasses[DPR_VFP2RegClassID],
5912    DPR_VFP2SubClassMask,
5913    SuperRegIdxSeqs + 0,
5914    LaneBitmask(0x0000000C),
5915    0,
5916    true, /* HasDisjunctSubRegs */
5917    true, /* CoveredBySubRegs */
5918    DPR_VFP2Superclasses,
5919    nullptr
5920  };
5921
5922  extern const TargetRegisterClass DPR_8RegClass = {
5923    &ARMMCRegisterClasses[DPR_8RegClassID],
5924    DPR_8SubClassMask,
5925    SuperRegIdxSeqs + 0,
5926    LaneBitmask(0x0000000C),
5927    0,
5928    true, /* HasDisjunctSubRegs */
5929    true, /* CoveredBySubRegs */
5930    DPR_8Superclasses,
5931    nullptr
5932  };
5933
5934  extern const TargetRegisterClass GPRPairRegClass = {
5935    &ARMMCRegisterClasses[GPRPairRegClassID],
5936    GPRPairSubClassMask,
5937    SuperRegIdxSeqs + 8,
5938    LaneBitmask(0x00000003),
5939    0,
5940    true, /* HasDisjunctSubRegs */
5941    true, /* CoveredBySubRegs */
5942    NullRegClasses,
5943    nullptr
5944  };
5945
5946  extern const TargetRegisterClass GPRPair_with_gsub_1_in_rGPRRegClass = {
5947    &ARMMCRegisterClasses[GPRPair_with_gsub_1_in_rGPRRegClassID],
5948    GPRPair_with_gsub_1_in_rGPRSubClassMask,
5949    SuperRegIdxSeqs + 8,
5950    LaneBitmask(0x00000003),
5951    0,
5952    true, /* HasDisjunctSubRegs */
5953    true, /* CoveredBySubRegs */
5954    GPRPair_with_gsub_1_in_rGPRSuperclasses,
5955    nullptr
5956  };
5957
5958  extern const TargetRegisterClass GPRPair_with_gsub_0_in_tGPRRegClass = {
5959    &ARMMCRegisterClasses[GPRPair_with_gsub_0_in_tGPRRegClassID],
5960    GPRPair_with_gsub_0_in_tGPRSubClassMask,
5961    SuperRegIdxSeqs + 8,
5962    LaneBitmask(0x00000003),
5963    0,
5964    true, /* HasDisjunctSubRegs */
5965    true, /* CoveredBySubRegs */
5966    GPRPair_with_gsub_0_in_tGPRSuperclasses,
5967    nullptr
5968  };
5969
5970  extern const TargetRegisterClass GPRPair_with_gsub_0_in_hGPRRegClass = {
5971    &ARMMCRegisterClasses[GPRPair_with_gsub_0_in_hGPRRegClassID],
5972    GPRPair_with_gsub_0_in_hGPRSubClassMask,
5973    SuperRegIdxSeqs + 8,
5974    LaneBitmask(0x00000003),
5975    0,
5976    true, /* HasDisjunctSubRegs */
5977    true, /* CoveredBySubRegs */
5978    GPRPair_with_gsub_0_in_hGPRSuperclasses,
5979    nullptr
5980  };
5981
5982  extern const TargetRegisterClass GPRPair_with_gsub_0_in_tcGPRRegClass = {
5983    &ARMMCRegisterClasses[GPRPair_with_gsub_0_in_tcGPRRegClassID],
5984    GPRPair_with_gsub_0_in_tcGPRSubClassMask,
5985    SuperRegIdxSeqs + 8,
5986    LaneBitmask(0x00000003),
5987    0,
5988    true, /* HasDisjunctSubRegs */
5989    true, /* CoveredBySubRegs */
5990    GPRPair_with_gsub_0_in_tcGPRSuperclasses,
5991    nullptr
5992  };
5993
5994  extern const TargetRegisterClass GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClass = {
5995    &ARMMCRegisterClasses[GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID],
5996    GPRPair_with_gsub_1_in_hGPR_and_rGPRSubClassMask,
5997    SuperRegIdxSeqs + 8,
5998    LaneBitmask(0x00000003),
5999    0,
6000    true, /* HasDisjunctSubRegs */
6001    true, /* CoveredBySubRegs */
6002    GPRPair_with_gsub_1_in_hGPR_and_rGPRSuperclasses,
6003    nullptr
6004  };
6005
6006  extern const TargetRegisterClass GPRPair_with_gsub_1_in_tcGPRRegClass = {
6007    &ARMMCRegisterClasses[GPRPair_with_gsub_1_in_tcGPRRegClassID],
6008    GPRPair_with_gsub_1_in_tcGPRSubClassMask,
6009    SuperRegIdxSeqs + 8,
6010    LaneBitmask(0x00000003),
6011    0,
6012    true, /* HasDisjunctSubRegs */
6013    true, /* CoveredBySubRegs */
6014    GPRPair_with_gsub_1_in_tcGPRSuperclasses,
6015    nullptr
6016  };
6017
6018  extern const TargetRegisterClass GPRPair_with_gsub_1_in_GPRspRegClass = {
6019    &ARMMCRegisterClasses[GPRPair_with_gsub_1_in_GPRspRegClassID],
6020    GPRPair_with_gsub_1_in_GPRspSubClassMask,
6021    SuperRegIdxSeqs + 8,
6022    LaneBitmask(0x00000003),
6023    0,
6024    true, /* HasDisjunctSubRegs */
6025    true, /* CoveredBySubRegs */
6026    GPRPair_with_gsub_1_in_GPRspSuperclasses,
6027    nullptr
6028  };
6029
6030  extern const TargetRegisterClass DPairSpcRegClass = {
6031    &ARMMCRegisterClasses[DPairSpcRegClassID],
6032    DPairSpcSubClassMask,
6033    SuperRegIdxSeqs + 50,
6034    LaneBitmask(0x000000CC),
6035    0,
6036    true, /* HasDisjunctSubRegs */
6037    true, /* CoveredBySubRegs */
6038    NullRegClasses,
6039    nullptr
6040  };
6041
6042  extern const TargetRegisterClass DPairSpc_with_ssub_0RegClass = {
6043    &ARMMCRegisterClasses[DPairSpc_with_ssub_0RegClassID],
6044    DPairSpc_with_ssub_0SubClassMask,
6045    SuperRegIdxSeqs + 50,
6046    LaneBitmask(0x000000CC),
6047    0,
6048    true, /* HasDisjunctSubRegs */
6049    true, /* CoveredBySubRegs */
6050    DPairSpc_with_ssub_0Superclasses,
6051    nullptr
6052  };
6053
6054  extern const TargetRegisterClass DPairSpc_with_ssub_4RegClass = {
6055    &ARMMCRegisterClasses[DPairSpc_with_ssub_4RegClassID],
6056    DPairSpc_with_ssub_4SubClassMask,
6057    SuperRegIdxSeqs + 50,
6058    LaneBitmask(0x000000CC),
6059    0,
6060    true, /* HasDisjunctSubRegs */
6061    true, /* CoveredBySubRegs */
6062    DPairSpc_with_ssub_4Superclasses,
6063    nullptr
6064  };
6065
6066  extern const TargetRegisterClass DPairSpc_with_dsub_0_in_DPR_8RegClass = {
6067    &ARMMCRegisterClasses[DPairSpc_with_dsub_0_in_DPR_8RegClassID],
6068    DPairSpc_with_dsub_0_in_DPR_8SubClassMask,
6069    SuperRegIdxSeqs + 50,
6070    LaneBitmask(0x000000CC),
6071    0,
6072    true, /* HasDisjunctSubRegs */
6073    true, /* CoveredBySubRegs */
6074    DPairSpc_with_dsub_0_in_DPR_8Superclasses,
6075    nullptr
6076  };
6077
6078  extern const TargetRegisterClass DPairSpc_with_dsub_2_in_DPR_8RegClass = {
6079    &ARMMCRegisterClasses[DPairSpc_with_dsub_2_in_DPR_8RegClassID],
6080    DPairSpc_with_dsub_2_in_DPR_8SubClassMask,
6081    SuperRegIdxSeqs + 50,
6082    LaneBitmask(0x000000CC),
6083    0,
6084    true, /* HasDisjunctSubRegs */
6085    true, /* CoveredBySubRegs */
6086    DPairSpc_with_dsub_2_in_DPR_8Superclasses,
6087    nullptr
6088  };
6089
6090  extern const TargetRegisterClass DPairRegClass = {
6091    &ARMMCRegisterClasses[DPairRegClassID],
6092    DPairSubClassMask,
6093    SuperRegIdxSeqs + 69,
6094    LaneBitmask(0x0000003C),
6095    0,
6096    true, /* HasDisjunctSubRegs */
6097    true, /* CoveredBySubRegs */
6098    NullRegClasses,
6099    DPairGetRawAllocationOrder
6100  };
6101
6102  extern const TargetRegisterClass DPair_with_ssub_0RegClass = {
6103    &ARMMCRegisterClasses[DPair_with_ssub_0RegClassID],
6104    DPair_with_ssub_0SubClassMask,
6105    SuperRegIdxSeqs + 69,
6106    LaneBitmask(0x0000003C),
6107    0,
6108    true, /* HasDisjunctSubRegs */
6109    true, /* CoveredBySubRegs */
6110    DPair_with_ssub_0Superclasses,
6111    DPair_with_ssub_0GetRawAllocationOrder
6112  };
6113
6114  extern const TargetRegisterClass QPRRegClass = {
6115    &ARMMCRegisterClasses[QPRRegClassID],
6116    QPRSubClassMask,
6117    SuperRegIdxSeqs + 31,
6118    LaneBitmask(0x0000003C),
6119    0,
6120    true, /* HasDisjunctSubRegs */
6121    true, /* CoveredBySubRegs */
6122    QPRSuperclasses,
6123    QPRGetRawAllocationOrder
6124  };
6125
6126  extern const TargetRegisterClass DPair_with_ssub_2RegClass = {
6127    &ARMMCRegisterClasses[DPair_with_ssub_2RegClassID],
6128    DPair_with_ssub_2SubClassMask,
6129    SuperRegIdxSeqs + 69,
6130    LaneBitmask(0x0000003C),
6131    0,
6132    true, /* HasDisjunctSubRegs */
6133    true, /* CoveredBySubRegs */
6134    DPair_with_ssub_2Superclasses,
6135    DPair_with_ssub_2GetRawAllocationOrder
6136  };
6137
6138  extern const TargetRegisterClass DPair_with_dsub_0_in_DPR_8RegClass = {
6139    &ARMMCRegisterClasses[DPair_with_dsub_0_in_DPR_8RegClassID],
6140    DPair_with_dsub_0_in_DPR_8SubClassMask,
6141    SuperRegIdxSeqs + 69,
6142    LaneBitmask(0x0000003C),
6143    0,
6144    true, /* HasDisjunctSubRegs */
6145    true, /* CoveredBySubRegs */
6146    DPair_with_dsub_0_in_DPR_8Superclasses,
6147    DPair_with_dsub_0_in_DPR_8GetRawAllocationOrder
6148  };
6149
6150  extern const TargetRegisterClass QPR_VFP2RegClass = {
6151    &ARMMCRegisterClasses[QPR_VFP2RegClassID],
6152    QPR_VFP2SubClassMask,
6153    SuperRegIdxSeqs + 31,
6154    LaneBitmask(0x0000003C),
6155    0,
6156    true, /* HasDisjunctSubRegs */
6157    true, /* CoveredBySubRegs */
6158    QPR_VFP2Superclasses,
6159    nullptr
6160  };
6161
6162  extern const TargetRegisterClass DPair_with_dsub_1_in_DPR_8RegClass = {
6163    &ARMMCRegisterClasses[DPair_with_dsub_1_in_DPR_8RegClassID],
6164    DPair_with_dsub_1_in_DPR_8SubClassMask,
6165    SuperRegIdxSeqs + 69,
6166    LaneBitmask(0x0000003C),
6167    0,
6168    true, /* HasDisjunctSubRegs */
6169    true, /* CoveredBySubRegs */
6170    DPair_with_dsub_1_in_DPR_8Superclasses,
6171    DPair_with_dsub_1_in_DPR_8GetRawAllocationOrder
6172  };
6173
6174  extern const TargetRegisterClass QPR_8RegClass = {
6175    &ARMMCRegisterClasses[QPR_8RegClassID],
6176    QPR_8SubClassMask,
6177    SuperRegIdxSeqs + 31,
6178    LaneBitmask(0x0000003C),
6179    0,
6180    true, /* HasDisjunctSubRegs */
6181    true, /* CoveredBySubRegs */
6182    QPR_8Superclasses,
6183    nullptr
6184  };
6185
6186  extern const TargetRegisterClass DTripleRegClass = {
6187    &ARMMCRegisterClasses[DTripleRegClassID],
6188    DTripleSubClassMask,
6189    SuperRegIdxSeqs + 62,
6190    LaneBitmask(0x000000FC),
6191    0,
6192    true, /* HasDisjunctSubRegs */
6193    true, /* CoveredBySubRegs */
6194    NullRegClasses,
6195    nullptr
6196  };
6197
6198  extern const TargetRegisterClass DTripleSpcRegClass = {
6199    &ARMMCRegisterClasses[DTripleSpcRegClassID],
6200    DTripleSpcSubClassMask,
6201    SuperRegIdxSeqs + 37,
6202    LaneBitmask(0x00000CCC),
6203    0,
6204    true, /* HasDisjunctSubRegs */
6205    true, /* CoveredBySubRegs */
6206    NullRegClasses,
6207    nullptr
6208  };
6209
6210  extern const TargetRegisterClass DTripleSpc_with_ssub_0RegClass = {
6211    &ARMMCRegisterClasses[DTripleSpc_with_ssub_0RegClassID],
6212    DTripleSpc_with_ssub_0SubClassMask,
6213    SuperRegIdxSeqs + 37,
6214    LaneBitmask(0x00000CCC),
6215    0,
6216    true, /* HasDisjunctSubRegs */
6217    true, /* CoveredBySubRegs */
6218    DTripleSpc_with_ssub_0Superclasses,
6219    nullptr
6220  };
6221
6222  extern const TargetRegisterClass DTriple_with_ssub_0RegClass = {
6223    &ARMMCRegisterClasses[DTriple_with_ssub_0RegClassID],
6224    DTriple_with_ssub_0SubClassMask,
6225    SuperRegIdxSeqs + 62,
6226    LaneBitmask(0x000000FC),
6227    0,
6228    true, /* HasDisjunctSubRegs */
6229    true, /* CoveredBySubRegs */
6230    DTriple_with_ssub_0Superclasses,
6231    nullptr
6232  };
6233
6234  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPRRegClass = {
6235    &ARMMCRegisterClasses[DTriple_with_qsub_0_in_QPRRegClassID],
6236    DTriple_with_qsub_0_in_QPRSubClassMask,
6237    SuperRegIdxSeqs + 45,
6238    LaneBitmask(0x000000FC),
6239    0,
6240    true, /* HasDisjunctSubRegs */
6241    true, /* CoveredBySubRegs */
6242    DTriple_with_qsub_0_in_QPRSuperclasses,
6243    nullptr
6244  };
6245
6246  extern const TargetRegisterClass DTriple_with_ssub_2RegClass = {
6247    &ARMMCRegisterClasses[DTriple_with_ssub_2RegClassID],
6248    DTriple_with_ssub_2SubClassMask,
6249    SuperRegIdxSeqs + 62,
6250    LaneBitmask(0x000000FC),
6251    0,
6252    true, /* HasDisjunctSubRegs */
6253    true, /* CoveredBySubRegs */
6254    DTriple_with_ssub_2Superclasses,
6255    nullptr
6256  };
6257
6258  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
6259    &ARMMCRegisterClasses[DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
6260    DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
6261    SuperRegIdxSeqs + 57,
6262    LaneBitmask(0x000000FC),
6263    0,
6264    true, /* HasDisjunctSubRegs */
6265    true, /* CoveredBySubRegs */
6266    DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
6267    nullptr
6268  };
6269
6270  extern const TargetRegisterClass DTripleSpc_with_ssub_4RegClass = {
6271    &ARMMCRegisterClasses[DTripleSpc_with_ssub_4RegClassID],
6272    DTripleSpc_with_ssub_4SubClassMask,
6273    SuperRegIdxSeqs + 37,
6274    LaneBitmask(0x00000CCC),
6275    0,
6276    true, /* HasDisjunctSubRegs */
6277    true, /* CoveredBySubRegs */
6278    DTripleSpc_with_ssub_4Superclasses,
6279    nullptr
6280  };
6281
6282  extern const TargetRegisterClass DTriple_with_ssub_4RegClass = {
6283    &ARMMCRegisterClasses[DTriple_with_ssub_4RegClassID],
6284    DTriple_with_ssub_4SubClassMask,
6285    SuperRegIdxSeqs + 62,
6286    LaneBitmask(0x000000FC),
6287    0,
6288    true, /* HasDisjunctSubRegs */
6289    true, /* CoveredBySubRegs */
6290    DTriple_with_ssub_4Superclasses,
6291    nullptr
6292  };
6293
6294  extern const TargetRegisterClass DTripleSpc_with_ssub_8RegClass = {
6295    &ARMMCRegisterClasses[DTripleSpc_with_ssub_8RegClassID],
6296    DTripleSpc_with_ssub_8SubClassMask,
6297    SuperRegIdxSeqs + 37,
6298    LaneBitmask(0x00000CCC),
6299    0,
6300    true, /* HasDisjunctSubRegs */
6301    true, /* CoveredBySubRegs */
6302    DTripleSpc_with_ssub_8Superclasses,
6303    nullptr
6304  };
6305
6306  extern const TargetRegisterClass DTripleSpc_with_dsub_0_in_DPR_8RegClass = {
6307    &ARMMCRegisterClasses[DTripleSpc_with_dsub_0_in_DPR_8RegClassID],
6308    DTripleSpc_with_dsub_0_in_DPR_8SubClassMask,
6309    SuperRegIdxSeqs + 37,
6310    LaneBitmask(0x00000CCC),
6311    0,
6312    true, /* HasDisjunctSubRegs */
6313    true, /* CoveredBySubRegs */
6314    DTripleSpc_with_dsub_0_in_DPR_8Superclasses,
6315    nullptr
6316  };
6317
6318  extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8RegClass = {
6319    &ARMMCRegisterClasses[DTriple_with_dsub_0_in_DPR_8RegClassID],
6320    DTriple_with_dsub_0_in_DPR_8SubClassMask,
6321    SuperRegIdxSeqs + 62,
6322    LaneBitmask(0x000000FC),
6323    0,
6324    true, /* HasDisjunctSubRegs */
6325    true, /* CoveredBySubRegs */
6326    DTriple_with_dsub_0_in_DPR_8Superclasses,
6327    nullptr
6328  };
6329
6330  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_VFP2RegClass = {
6331    &ARMMCRegisterClasses[DTriple_with_qsub_0_in_QPR_VFP2RegClassID],
6332    DTriple_with_qsub_0_in_QPR_VFP2SubClassMask,
6333    SuperRegIdxSeqs + 45,
6334    LaneBitmask(0x000000FC),
6335    0,
6336    true, /* HasDisjunctSubRegs */
6337    true, /* CoveredBySubRegs */
6338    DTriple_with_qsub_0_in_QPR_VFP2Superclasses,
6339    nullptr
6340  };
6341
6342  extern const TargetRegisterClass DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
6343    &ARMMCRegisterClasses[DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
6344    DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
6345    SuperRegIdxSeqs + 57,
6346    LaneBitmask(0x000000FC),
6347    0,
6348    true, /* HasDisjunctSubRegs */
6349    true, /* CoveredBySubRegs */
6350    DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
6351    nullptr
6352  };
6353
6354  extern const TargetRegisterClass DTriple_with_dsub_1_in_DPR_8RegClass = {
6355    &ARMMCRegisterClasses[DTriple_with_dsub_1_in_DPR_8RegClassID],
6356    DTriple_with_dsub_1_in_DPR_8SubClassMask,
6357    SuperRegIdxSeqs + 62,
6358    LaneBitmask(0x000000FC),
6359    0,
6360    true, /* HasDisjunctSubRegs */
6361    true, /* CoveredBySubRegs */
6362    DTriple_with_dsub_1_in_DPR_8Superclasses,
6363    nullptr
6364  };
6365
6366  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass = {
6367    &ARMMCRegisterClasses[DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID],
6368    DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2SubClassMask,
6369    SuperRegIdxSeqs + 57,
6370    LaneBitmask(0x000000FC),
6371    0,
6372    true, /* HasDisjunctSubRegs */
6373    true, /* CoveredBySubRegs */
6374    DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Superclasses,
6375    nullptr
6376  };
6377
6378  extern const TargetRegisterClass DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass = {
6379    &ARMMCRegisterClasses[DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClassID],
6380    DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRSubClassMask,
6381    SuperRegIdxSeqs + 45,
6382    LaneBitmask(0x000000FC),
6383    0,
6384    true, /* HasDisjunctSubRegs */
6385    true, /* CoveredBySubRegs */
6386    DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRSuperclasses,
6387    nullptr
6388  };
6389
6390  extern const TargetRegisterClass DTripleSpc_with_dsub_2_in_DPR_8RegClass = {
6391    &ARMMCRegisterClasses[DTripleSpc_with_dsub_2_in_DPR_8RegClassID],
6392    DTripleSpc_with_dsub_2_in_DPR_8SubClassMask,
6393    SuperRegIdxSeqs + 37,
6394    LaneBitmask(0x00000CCC),
6395    0,
6396    true, /* HasDisjunctSubRegs */
6397    true, /* CoveredBySubRegs */
6398    DTripleSpc_with_dsub_2_in_DPR_8Superclasses,
6399    nullptr
6400  };
6401
6402  extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8RegClass = {
6403    &ARMMCRegisterClasses[DTriple_with_dsub_2_in_DPR_8RegClassID],
6404    DTriple_with_dsub_2_in_DPR_8SubClassMask,
6405    SuperRegIdxSeqs + 62,
6406    LaneBitmask(0x000000FC),
6407    0,
6408    true, /* HasDisjunctSubRegs */
6409    true, /* CoveredBySubRegs */
6410    DTriple_with_dsub_2_in_DPR_8Superclasses,
6411    nullptr
6412  };
6413
6414  extern const TargetRegisterClass DTripleSpc_with_dsub_4_in_DPR_8RegClass = {
6415    &ARMMCRegisterClasses[DTripleSpc_with_dsub_4_in_DPR_8RegClassID],
6416    DTripleSpc_with_dsub_4_in_DPR_8SubClassMask,
6417    SuperRegIdxSeqs + 37,
6418    LaneBitmask(0x00000CCC),
6419    0,
6420    true, /* HasDisjunctSubRegs */
6421    true, /* CoveredBySubRegs */
6422    DTripleSpc_with_dsub_4_in_DPR_8Superclasses,
6423    nullptr
6424  };
6425
6426  extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
6427    &ARMMCRegisterClasses[DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
6428    DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
6429    SuperRegIdxSeqs + 57,
6430    LaneBitmask(0x000000FC),
6431    0,
6432    true, /* HasDisjunctSubRegs */
6433    true, /* CoveredBySubRegs */
6434    DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
6435    nullptr
6436  };
6437
6438  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_8RegClass = {
6439    &ARMMCRegisterClasses[DTriple_with_qsub_0_in_QPR_8RegClassID],
6440    DTriple_with_qsub_0_in_QPR_8SubClassMask,
6441    SuperRegIdxSeqs + 45,
6442    LaneBitmask(0x000000FC),
6443    0,
6444    true, /* HasDisjunctSubRegs */
6445    true, /* CoveredBySubRegs */
6446    DTriple_with_qsub_0_in_QPR_8Superclasses,
6447    nullptr
6448  };
6449
6450  extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClass = {
6451    &ARMMCRegisterClasses[DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID],
6452    DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRSubClassMask,
6453    SuperRegIdxSeqs + 45,
6454    LaneBitmask(0x000000FC),
6455    0,
6456    true, /* HasDisjunctSubRegs */
6457    true, /* CoveredBySubRegs */
6458    DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRSuperclasses,
6459    nullptr
6460  };
6461
6462  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass = {
6463    &ARMMCRegisterClasses[DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID],
6464    DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask,
6465    SuperRegIdxSeqs + 57,
6466    LaneBitmask(0x000000FC),
6467    0,
6468    true, /* HasDisjunctSubRegs */
6469    true, /* CoveredBySubRegs */
6470    DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses,
6471    nullptr
6472  };
6473
6474  extern const TargetRegisterClass DQuadSpcRegClass = {
6475    &ARMMCRegisterClasses[DQuadSpcRegClassID],
6476    DQuadSpcSubClassMask,
6477    SuperRegIdxSeqs + 37,
6478    LaneBitmask(0x00000CCC),
6479    0,
6480    true, /* HasDisjunctSubRegs */
6481    true, /* CoveredBySubRegs */
6482    DQuadSpcSuperclasses,
6483    nullptr
6484  };
6485
6486  extern const TargetRegisterClass DQuadSpc_with_ssub_0RegClass = {
6487    &ARMMCRegisterClasses[DQuadSpc_with_ssub_0RegClassID],
6488    DQuadSpc_with_ssub_0SubClassMask,
6489    SuperRegIdxSeqs + 37,
6490    LaneBitmask(0x00000CCC),
6491    0,
6492    true, /* HasDisjunctSubRegs */
6493    true, /* CoveredBySubRegs */
6494    DQuadSpc_with_ssub_0Superclasses,
6495    nullptr
6496  };
6497
6498  extern const TargetRegisterClass DQuadSpc_with_ssub_4RegClass = {
6499    &ARMMCRegisterClasses[DQuadSpc_with_ssub_4RegClassID],
6500    DQuadSpc_with_ssub_4SubClassMask,
6501    SuperRegIdxSeqs + 37,
6502    LaneBitmask(0x00000CCC),
6503    0,
6504    true, /* HasDisjunctSubRegs */
6505    true, /* CoveredBySubRegs */
6506    DQuadSpc_with_ssub_4Superclasses,
6507    nullptr
6508  };
6509
6510  extern const TargetRegisterClass DQuadSpc_with_ssub_8RegClass = {
6511    &ARMMCRegisterClasses[DQuadSpc_with_ssub_8RegClassID],
6512    DQuadSpc_with_ssub_8SubClassMask,
6513    SuperRegIdxSeqs + 37,
6514    LaneBitmask(0x00000CCC),
6515    0,
6516    true, /* HasDisjunctSubRegs */
6517    true, /* CoveredBySubRegs */
6518    DQuadSpc_with_ssub_8Superclasses,
6519    nullptr
6520  };
6521
6522  extern const TargetRegisterClass DQuadSpc_with_dsub_0_in_DPR_8RegClass = {
6523    &ARMMCRegisterClasses[DQuadSpc_with_dsub_0_in_DPR_8RegClassID],
6524    DQuadSpc_with_dsub_0_in_DPR_8SubClassMask,
6525    SuperRegIdxSeqs + 37,
6526    LaneBitmask(0x00000CCC),
6527    0,
6528    true, /* HasDisjunctSubRegs */
6529    true, /* CoveredBySubRegs */
6530    DQuadSpc_with_dsub_0_in_DPR_8Superclasses,
6531    nullptr
6532  };
6533
6534  extern const TargetRegisterClass DQuadSpc_with_dsub_2_in_DPR_8RegClass = {
6535    &ARMMCRegisterClasses[DQuadSpc_with_dsub_2_in_DPR_8RegClassID],
6536    DQuadSpc_with_dsub_2_in_DPR_8SubClassMask,
6537    SuperRegIdxSeqs + 37,
6538    LaneBitmask(0x00000CCC),
6539    0,
6540    true, /* HasDisjunctSubRegs */
6541    true, /* CoveredBySubRegs */
6542    DQuadSpc_with_dsub_2_in_DPR_8Superclasses,
6543    nullptr
6544  };
6545
6546  extern const TargetRegisterClass DQuadSpc_with_dsub_4_in_DPR_8RegClass = {
6547    &ARMMCRegisterClasses[DQuadSpc_with_dsub_4_in_DPR_8RegClassID],
6548    DQuadSpc_with_dsub_4_in_DPR_8SubClassMask,
6549    SuperRegIdxSeqs + 37,
6550    LaneBitmask(0x00000CCC),
6551    0,
6552    true, /* HasDisjunctSubRegs */
6553    true, /* CoveredBySubRegs */
6554    DQuadSpc_with_dsub_4_in_DPR_8Superclasses,
6555    nullptr
6556  };
6557
6558  extern const TargetRegisterClass DQuadRegClass = {
6559    &ARMMCRegisterClasses[DQuadRegClassID],
6560    DQuadSubClassMask,
6561    SuperRegIdxSeqs + 81,
6562    LaneBitmask(0x000003FC),
6563    0,
6564    true, /* HasDisjunctSubRegs */
6565    true, /* CoveredBySubRegs */
6566    NullRegClasses,
6567    nullptr
6568  };
6569
6570  extern const TargetRegisterClass DQuad_with_ssub_0RegClass = {
6571    &ARMMCRegisterClasses[DQuad_with_ssub_0RegClassID],
6572    DQuad_with_ssub_0SubClassMask,
6573    SuperRegIdxSeqs + 81,
6574    LaneBitmask(0x000003FC),
6575    0,
6576    true, /* HasDisjunctSubRegs */
6577    true, /* CoveredBySubRegs */
6578    DQuad_with_ssub_0Superclasses,
6579    nullptr
6580  };
6581
6582  extern const TargetRegisterClass DQuad_with_ssub_2RegClass = {
6583    &ARMMCRegisterClasses[DQuad_with_ssub_2RegClassID],
6584    DQuad_with_ssub_2SubClassMask,
6585    SuperRegIdxSeqs + 81,
6586    LaneBitmask(0x000003FC),
6587    0,
6588    true, /* HasDisjunctSubRegs */
6589    true, /* CoveredBySubRegs */
6590    DQuad_with_ssub_2Superclasses,
6591    nullptr
6592  };
6593
6594  extern const TargetRegisterClass QQPRRegClass = {
6595    &ARMMCRegisterClasses[QQPRRegClassID],
6596    QQPRSubClassMask,
6597    SuperRegIdxSeqs + 77,
6598    LaneBitmask(0x000003FC),
6599    0,
6600    true, /* HasDisjunctSubRegs */
6601    true, /* CoveredBySubRegs */
6602    QQPRSuperclasses,
6603    QQPRGetRawAllocationOrder
6604  };
6605
6606  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
6607    &ARMMCRegisterClasses[DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
6608    DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
6609    SuperRegIdxSeqs + 42,
6610    LaneBitmask(0x000003FC),
6611    0,
6612    true, /* HasDisjunctSubRegs */
6613    true, /* CoveredBySubRegs */
6614    DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
6615    nullptr
6616  };
6617
6618  extern const TargetRegisterClass DQuad_with_ssub_4RegClass = {
6619    &ARMMCRegisterClasses[DQuad_with_ssub_4RegClassID],
6620    DQuad_with_ssub_4SubClassMask,
6621    SuperRegIdxSeqs + 81,
6622    LaneBitmask(0x000003FC),
6623    0,
6624    true, /* HasDisjunctSubRegs */
6625    true, /* CoveredBySubRegs */
6626    DQuad_with_ssub_4Superclasses,
6627    nullptr
6628  };
6629
6630  extern const TargetRegisterClass DQuad_with_ssub_6RegClass = {
6631    &ARMMCRegisterClasses[DQuad_with_ssub_6RegClassID],
6632    DQuad_with_ssub_6SubClassMask,
6633    SuperRegIdxSeqs + 81,
6634    LaneBitmask(0x000003FC),
6635    0,
6636    true, /* HasDisjunctSubRegs */
6637    true, /* CoveredBySubRegs */
6638    DQuad_with_ssub_6Superclasses,
6639    nullptr
6640  };
6641
6642  extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8RegClass = {
6643    &ARMMCRegisterClasses[DQuad_with_dsub_0_in_DPR_8RegClassID],
6644    DQuad_with_dsub_0_in_DPR_8SubClassMask,
6645    SuperRegIdxSeqs + 81,
6646    LaneBitmask(0x000003FC),
6647    0,
6648    true, /* HasDisjunctSubRegs */
6649    true, /* CoveredBySubRegs */
6650    DQuad_with_dsub_0_in_DPR_8Superclasses,
6651    nullptr
6652  };
6653
6654  extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_VFP2RegClass = {
6655    &ARMMCRegisterClasses[DQuad_with_qsub_0_in_QPR_VFP2RegClassID],
6656    DQuad_with_qsub_0_in_QPR_VFP2SubClassMask,
6657    SuperRegIdxSeqs + 77,
6658    LaneBitmask(0x000003FC),
6659    0,
6660    true, /* HasDisjunctSubRegs */
6661    true, /* CoveredBySubRegs */
6662    DQuad_with_qsub_0_in_QPR_VFP2Superclasses,
6663    DQuad_with_qsub_0_in_QPR_VFP2GetRawAllocationOrder
6664  };
6665
6666  extern const TargetRegisterClass DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
6667    &ARMMCRegisterClasses[DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
6668    DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
6669    SuperRegIdxSeqs + 42,
6670    LaneBitmask(0x000003FC),
6671    0,
6672    true, /* HasDisjunctSubRegs */
6673    true, /* CoveredBySubRegs */
6674    DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
6675    nullptr
6676  };
6677
6678  extern const TargetRegisterClass DQuad_with_dsub_1_in_DPR_8RegClass = {
6679    &ARMMCRegisterClasses[DQuad_with_dsub_1_in_DPR_8RegClassID],
6680    DQuad_with_dsub_1_in_DPR_8SubClassMask,
6681    SuperRegIdxSeqs + 81,
6682    LaneBitmask(0x000003FC),
6683    0,
6684    true, /* HasDisjunctSubRegs */
6685    true, /* CoveredBySubRegs */
6686    DQuad_with_dsub_1_in_DPR_8Superclasses,
6687    nullptr
6688  };
6689
6690  extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_VFP2RegClass = {
6691    &ARMMCRegisterClasses[DQuad_with_qsub_1_in_QPR_VFP2RegClassID],
6692    DQuad_with_qsub_1_in_QPR_VFP2SubClassMask,
6693    SuperRegIdxSeqs + 77,
6694    LaneBitmask(0x000003FC),
6695    0,
6696    true, /* HasDisjunctSubRegs */
6697    true, /* CoveredBySubRegs */
6698    DQuad_with_qsub_1_in_QPR_VFP2Superclasses,
6699    DQuad_with_qsub_1_in_QPR_VFP2GetRawAllocationOrder
6700  };
6701
6702  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass = {
6703    &ARMMCRegisterClasses[DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID],
6704    DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2SubClassMask,
6705    SuperRegIdxSeqs + 42,
6706    LaneBitmask(0x000003FC),
6707    0,
6708    true, /* HasDisjunctSubRegs */
6709    true, /* CoveredBySubRegs */
6710    DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Superclasses,
6711    nullptr
6712  };
6713
6714  extern const TargetRegisterClass DQuad_with_dsub_2_in_DPR_8RegClass = {
6715    &ARMMCRegisterClasses[DQuad_with_dsub_2_in_DPR_8RegClassID],
6716    DQuad_with_dsub_2_in_DPR_8SubClassMask,
6717    SuperRegIdxSeqs + 81,
6718    LaneBitmask(0x000003FC),
6719    0,
6720    true, /* HasDisjunctSubRegs */
6721    true, /* CoveredBySubRegs */
6722    DQuad_with_dsub_2_in_DPR_8Superclasses,
6723    nullptr
6724  };
6725
6726  extern const TargetRegisterClass DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
6727    &ARMMCRegisterClasses[DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
6728    DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
6729    SuperRegIdxSeqs + 42,
6730    LaneBitmask(0x000003FC),
6731    0,
6732    true, /* HasDisjunctSubRegs */
6733    true, /* CoveredBySubRegs */
6734    DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
6735    nullptr
6736  };
6737
6738  extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8RegClass = {
6739    &ARMMCRegisterClasses[DQuad_with_dsub_3_in_DPR_8RegClassID],
6740    DQuad_with_dsub_3_in_DPR_8SubClassMask,
6741    SuperRegIdxSeqs + 81,
6742    LaneBitmask(0x000003FC),
6743    0,
6744    true, /* HasDisjunctSubRegs */
6745    true, /* CoveredBySubRegs */
6746    DQuad_with_dsub_3_in_DPR_8Superclasses,
6747    nullptr
6748  };
6749
6750  extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
6751    &ARMMCRegisterClasses[DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
6752    DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
6753    SuperRegIdxSeqs + 42,
6754    LaneBitmask(0x000003FC),
6755    0,
6756    true, /* HasDisjunctSubRegs */
6757    true, /* CoveredBySubRegs */
6758    DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
6759    nullptr
6760  };
6761
6762  extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_8RegClass = {
6763    &ARMMCRegisterClasses[DQuad_with_qsub_0_in_QPR_8RegClassID],
6764    DQuad_with_qsub_0_in_QPR_8SubClassMask,
6765    SuperRegIdxSeqs + 77,
6766    LaneBitmask(0x000003FC),
6767    0,
6768    true, /* HasDisjunctSubRegs */
6769    true, /* CoveredBySubRegs */
6770    DQuad_with_qsub_0_in_QPR_8Superclasses,
6771    DQuad_with_qsub_0_in_QPR_8GetRawAllocationOrder
6772  };
6773
6774  extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_8RegClass = {
6775    &ARMMCRegisterClasses[DQuad_with_qsub_1_in_QPR_8RegClassID],
6776    DQuad_with_qsub_1_in_QPR_8SubClassMask,
6777    SuperRegIdxSeqs + 77,
6778    LaneBitmask(0x000003FC),
6779    0,
6780    true, /* HasDisjunctSubRegs */
6781    true, /* CoveredBySubRegs */
6782    DQuad_with_qsub_1_in_QPR_8Superclasses,
6783    DQuad_with_qsub_1_in_QPR_8GetRawAllocationOrder
6784  };
6785
6786  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass = {
6787    &ARMMCRegisterClasses[DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID],
6788    DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask,
6789    SuperRegIdxSeqs + 42,
6790    LaneBitmask(0x000003FC),
6791    0,
6792    true, /* HasDisjunctSubRegs */
6793    true, /* CoveredBySubRegs */
6794    DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses,
6795    nullptr
6796  };
6797
6798  extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
6799    &ARMMCRegisterClasses[DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
6800    DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
6801    SuperRegIdxSeqs + 42,
6802    LaneBitmask(0x000003FC),
6803    0,
6804    true, /* HasDisjunctSubRegs */
6805    true, /* CoveredBySubRegs */
6806    DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
6807    nullptr
6808  };
6809
6810  extern const TargetRegisterClass QQQQPRRegClass = {
6811    &ARMMCRegisterClasses[QQQQPRRegClassID],
6812    QQQQPRSubClassMask,
6813    SuperRegIdxSeqs + 8,
6814    LaneBitmask(0x0003FFFC),
6815    0,
6816    true, /* HasDisjunctSubRegs */
6817    true, /* CoveredBySubRegs */
6818    NullRegClasses,
6819    QQQQPRGetRawAllocationOrder
6820  };
6821
6822  extern const TargetRegisterClass QQQQPR_with_ssub_0RegClass = {
6823    &ARMMCRegisterClasses[QQQQPR_with_ssub_0RegClassID],
6824    QQQQPR_with_ssub_0SubClassMask,
6825    SuperRegIdxSeqs + 8,
6826    LaneBitmask(0x0003FFFC),
6827    0,
6828    true, /* HasDisjunctSubRegs */
6829    true, /* CoveredBySubRegs */
6830    QQQQPR_with_ssub_0Superclasses,
6831    QQQQPR_with_ssub_0GetRawAllocationOrder
6832  };
6833
6834  extern const TargetRegisterClass QQQQPR_with_ssub_4RegClass = {
6835    &ARMMCRegisterClasses[QQQQPR_with_ssub_4RegClassID],
6836    QQQQPR_with_ssub_4SubClassMask,
6837    SuperRegIdxSeqs + 8,
6838    LaneBitmask(0x0003FFFC),
6839    0,
6840    true, /* HasDisjunctSubRegs */
6841    true, /* CoveredBySubRegs */
6842    QQQQPR_with_ssub_4Superclasses,
6843    QQQQPR_with_ssub_4GetRawAllocationOrder
6844  };
6845
6846  extern const TargetRegisterClass QQQQPR_with_ssub_8RegClass = {
6847    &ARMMCRegisterClasses[QQQQPR_with_ssub_8RegClassID],
6848    QQQQPR_with_ssub_8SubClassMask,
6849    SuperRegIdxSeqs + 8,
6850    LaneBitmask(0x0003FFFC),
6851    0,
6852    true, /* HasDisjunctSubRegs */
6853    true, /* CoveredBySubRegs */
6854    QQQQPR_with_ssub_8Superclasses,
6855    QQQQPR_with_ssub_8GetRawAllocationOrder
6856  };
6857
6858  extern const TargetRegisterClass QQQQPR_with_ssub_12RegClass = {
6859    &ARMMCRegisterClasses[QQQQPR_with_ssub_12RegClassID],
6860    QQQQPR_with_ssub_12SubClassMask,
6861    SuperRegIdxSeqs + 8,
6862    LaneBitmask(0x0003FFFC),
6863    0,
6864    true, /* HasDisjunctSubRegs */
6865    true, /* CoveredBySubRegs */
6866    QQQQPR_with_ssub_12Superclasses,
6867    QQQQPR_with_ssub_12GetRawAllocationOrder
6868  };
6869
6870  extern const TargetRegisterClass QQQQPR_with_dsub_0_in_DPR_8RegClass = {
6871    &ARMMCRegisterClasses[QQQQPR_with_dsub_0_in_DPR_8RegClassID],
6872    QQQQPR_with_dsub_0_in_DPR_8SubClassMask,
6873    SuperRegIdxSeqs + 8,
6874    LaneBitmask(0x0003FFFC),
6875    0,
6876    true, /* HasDisjunctSubRegs */
6877    true, /* CoveredBySubRegs */
6878    QQQQPR_with_dsub_0_in_DPR_8Superclasses,
6879    QQQQPR_with_dsub_0_in_DPR_8GetRawAllocationOrder
6880  };
6881
6882  extern const TargetRegisterClass QQQQPR_with_dsub_2_in_DPR_8RegClass = {
6883    &ARMMCRegisterClasses[QQQQPR_with_dsub_2_in_DPR_8RegClassID],
6884    QQQQPR_with_dsub_2_in_DPR_8SubClassMask,
6885    SuperRegIdxSeqs + 8,
6886    LaneBitmask(0x0003FFFC),
6887    0,
6888    true, /* HasDisjunctSubRegs */
6889    true, /* CoveredBySubRegs */
6890    QQQQPR_with_dsub_2_in_DPR_8Superclasses,
6891    QQQQPR_with_dsub_2_in_DPR_8GetRawAllocationOrder
6892  };
6893
6894  extern const TargetRegisterClass QQQQPR_with_dsub_4_in_DPR_8RegClass = {
6895    &ARMMCRegisterClasses[QQQQPR_with_dsub_4_in_DPR_8RegClassID],
6896    QQQQPR_with_dsub_4_in_DPR_8SubClassMask,
6897    SuperRegIdxSeqs + 8,
6898    LaneBitmask(0x0003FFFC),
6899    0,
6900    true, /* HasDisjunctSubRegs */
6901    true, /* CoveredBySubRegs */
6902    QQQQPR_with_dsub_4_in_DPR_8Superclasses,
6903    QQQQPR_with_dsub_4_in_DPR_8GetRawAllocationOrder
6904  };
6905
6906  extern const TargetRegisterClass QQQQPR_with_dsub_6_in_DPR_8RegClass = {
6907    &ARMMCRegisterClasses[QQQQPR_with_dsub_6_in_DPR_8RegClassID],
6908    QQQQPR_with_dsub_6_in_DPR_8SubClassMask,
6909    SuperRegIdxSeqs + 8,
6910    LaneBitmask(0x0003FFFC),
6911    0,
6912    true, /* HasDisjunctSubRegs */
6913    true, /* CoveredBySubRegs */
6914    QQQQPR_with_dsub_6_in_DPR_8Superclasses,
6915    QQQQPR_with_dsub_6_in_DPR_8GetRawAllocationOrder
6916  };
6917
6918} // end namespace ARM
6919
6920namespace {
6921  const TargetRegisterClass* const RegisterClasses[] = {
6922    &ARM::HPRRegClass,
6923    &ARM::SPRRegClass,
6924    &ARM::GPRRegClass,
6925    &ARM::GPRwithAPSRRegClass,
6926    &ARM::SPR_8RegClass,
6927    &ARM::GPRnopcRegClass,
6928    &ARM::rGPRRegClass,
6929    &ARM::tGPRwithpcRegClass,
6930    &ARM::hGPRRegClass,
6931    &ARM::tGPRRegClass,
6932    &ARM::GPRnopc_and_hGPRRegClass,
6933    &ARM::hGPR_and_rGPRRegClass,
6934    &ARM::tcGPRRegClass,
6935    &ARM::tGPR_and_tcGPRRegClass,
6936    &ARM::CCRRegClass,
6937    &ARM::GPRspRegClass,
6938    &ARM::hGPR_and_tGPRwithpcRegClass,
6939    &ARM::hGPR_and_tcGPRRegClass,
6940    &ARM::DPRRegClass,
6941    &ARM::DPR_VFP2RegClass,
6942    &ARM::DPR_8RegClass,
6943    &ARM::GPRPairRegClass,
6944    &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
6945    &ARM::GPRPair_with_gsub_0_in_tGPRRegClass,
6946    &ARM::GPRPair_with_gsub_0_in_hGPRRegClass,
6947    &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass,
6948    &ARM::GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClass,
6949    &ARM::GPRPair_with_gsub_1_in_tcGPRRegClass,
6950    &ARM::GPRPair_with_gsub_1_in_GPRspRegClass,
6951    &ARM::DPairSpcRegClass,
6952    &ARM::DPairSpc_with_ssub_0RegClass,
6953    &ARM::DPairSpc_with_ssub_4RegClass,
6954    &ARM::DPairSpc_with_dsub_0_in_DPR_8RegClass,
6955    &ARM::DPairSpc_with_dsub_2_in_DPR_8RegClass,
6956    &ARM::DPairRegClass,
6957    &ARM::DPair_with_ssub_0RegClass,
6958    &ARM::QPRRegClass,
6959    &ARM::DPair_with_ssub_2RegClass,
6960    &ARM::DPair_with_dsub_0_in_DPR_8RegClass,
6961    &ARM::QPR_VFP2RegClass,
6962    &ARM::DPair_with_dsub_1_in_DPR_8RegClass,
6963    &ARM::QPR_8RegClass,
6964    &ARM::DTripleRegClass,
6965    &ARM::DTripleSpcRegClass,
6966    &ARM::DTripleSpc_with_ssub_0RegClass,
6967    &ARM::DTriple_with_ssub_0RegClass,
6968    &ARM::DTriple_with_qsub_0_in_QPRRegClass,
6969    &ARM::DTriple_with_ssub_2RegClass,
6970    &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
6971    &ARM::DTripleSpc_with_ssub_4RegClass,
6972    &ARM::DTriple_with_ssub_4RegClass,
6973    &ARM::DTripleSpc_with_ssub_8RegClass,
6974    &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
6975    &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
6976    &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
6977    &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
6978    &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
6979    &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
6980    &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass,
6981    &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
6982    &ARM::DTriple_with_dsub_2_in_DPR_8RegClass,
6983    &ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClass,
6984    &ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
6985    &ARM::DTriple_with_qsub_0_in_QPR_8RegClass,
6986    &ARM::DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClass,
6987    &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass,
6988    &ARM::DQuadSpcRegClass,
6989    &ARM::DQuadSpc_with_ssub_0RegClass,
6990    &ARM::DQuadSpc_with_ssub_4RegClass,
6991    &ARM::DQuadSpc_with_ssub_8RegClass,
6992    &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass,
6993    &ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClass,
6994    &ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClass,
6995    &ARM::DQuadRegClass,
6996    &ARM::DQuad_with_ssub_0RegClass,
6997    &ARM::DQuad_with_ssub_2RegClass,
6998    &ARM::QQPRRegClass,
6999    &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
7000    &ARM::DQuad_with_ssub_4RegClass,
7001    &ARM::DQuad_with_ssub_6RegClass,
7002    &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
7003    &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
7004    &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
7005    &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
7006    &ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClass,
7007    &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
7008    &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
7009    &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
7010    &ARM::DQuad_with_dsub_3_in_DPR_8RegClass,
7011    &ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
7012    &ARM::DQuad_with_qsub_0_in_QPR_8RegClass,
7013    &ARM::DQuad_with_qsub_1_in_QPR_8RegClass,
7014    &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass,
7015    &ARM::DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
7016    &ARM::QQQQPRRegClass,
7017    &ARM::QQQQPR_with_ssub_0RegClass,
7018    &ARM::QQQQPR_with_ssub_4RegClass,
7019    &ARM::QQQQPR_with_ssub_8RegClass,
7020    &ARM::QQQQPR_with_ssub_12RegClass,
7021    &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass,
7022    &ARM::QQQQPR_with_dsub_2_in_DPR_8RegClass,
7023    &ARM::QQQQPR_with_dsub_4_in_DPR_8RegClass,
7024    &ARM::QQQQPR_with_dsub_6_in_DPR_8RegClass,
7025  };
7026} // end anonymous namespace
7027
7028static const TargetRegisterInfoDesc ARMRegInfoDesc[] = { // Extra Descriptors
7029  { 0, false },
7030  { 0, false },
7031  { 0, true },
7032  { 0, false },
7033  { 0, false },
7034  { 0, false },
7035  { 0, false },
7036  { 0, false },
7037  { 0, false },
7038  { 0, false },
7039  { 1, true },
7040  { 1, true },
7041  { 1, true },
7042  { 0, false },
7043  { 0, true },
7044  { 0, true },
7045  { 0, true },
7046  { 0, true },
7047  { 0, true },
7048  { 0, true },
7049  { 0, true },
7050  { 0, true },
7051  { 0, true },
7052  { 0, true },
7053  { 0, true },
7054  { 0, true },
7055  { 0, true },
7056  { 0, true },
7057  { 0, true },
7058  { 0, true },
7059  { 0, true },
7060  { 0, true },
7061  { 0, true },
7062  { 0, true },
7063  { 0, true },
7064  { 0, true },
7065  { 0, true },
7066  { 0, true },
7067  { 0, true },
7068  { 0, true },
7069  { 0, true },
7070  { 0, true },
7071  { 0, true },
7072  { 0, true },
7073  { 0, true },
7074  { 0, true },
7075  { 0, false },
7076  { 0, false },
7077  { 0, false },
7078  { 0, false },
7079  { 0, true },
7080  { 0, true },
7081  { 0, true },
7082  { 0, true },
7083  { 0, true },
7084  { 0, true },
7085  { 0, true },
7086  { 0, true },
7087  { 0, true },
7088  { 0, true },
7089  { 0, true },
7090  { 0, true },
7091  { 0, true },
7092  { 0, true },
7093  { 0, true },
7094  { 0, true },
7095  { 0, true },
7096  { 0, true },
7097  { 0, true },
7098  { 0, true },
7099  { 0, true },
7100  { 0, true },
7101  { 0, true },
7102  { 0, true },
7103  { 1, true },
7104  { 1, true },
7105  { 1, true },
7106  { 1, true },
7107  { 1, true },
7108  { 0, true },
7109  { 0, true },
7110  { 0, true },
7111  { 0, true },
7112  { 0, true },
7113  { 0, true },
7114  { 0, true },
7115  { 0, true },
7116  { 0, true },
7117  { 0, true },
7118  { 0, true },
7119  { 0, true },
7120  { 0, true },
7121  { 0, true },
7122  { 0, true },
7123  { 0, true },
7124  { 0, true },
7125  { 0, true },
7126  { 0, true },
7127  { 0, true },
7128  { 0, true },
7129  { 0, true },
7130  { 0, true },
7131  { 0, true },
7132  { 0, true },
7133  { 0, true },
7134  { 0, true },
7135  { 0, true },
7136  { 0, true },
7137  { 0, true },
7138  { 0, true },
7139  { 0, true },
7140  { 0, true },
7141  { 0, true },
7142  { 0, true },
7143  { 0, true },
7144  { 0, true },
7145  { 0, true },
7146  { 0, true },
7147  { 0, true },
7148  { 0, true },
7149  { 0, true },
7150  { 0, true },
7151  { 0, true },
7152  { 0, true },
7153  { 0, true },
7154  { 0, true },
7155  { 0, true },
7156  { 0, true },
7157  { 0, true },
7158  { 0, true },
7159  { 0, true },
7160  { 0, true },
7161  { 0, true },
7162  { 0, true },
7163  { 0, true },
7164  { 0, true },
7165  { 0, true },
7166  { 0, true },
7167  { 0, true },
7168  { 0, true },
7169  { 0, true },
7170  { 0, true },
7171  { 0, true },
7172  { 0, true },
7173  { 0, true },
7174  { 0, true },
7175  { 0, true },
7176  { 0, true },
7177  { 0, true },
7178  { 0, true },
7179  { 0, true },
7180  { 0, true },
7181  { 0, true },
7182  { 0, true },
7183  { 0, true },
7184  { 0, true },
7185  { 0, true },
7186  { 0, true },
7187  { 0, true },
7188  { 0, true },
7189  { 0, true },
7190  { 0, true },
7191  { 0, true },
7192  { 0, true },
7193  { 0, true },
7194  { 0, true },
7195  { 0, true },
7196  { 0, true },
7197  { 0, true },
7198  { 1, true },
7199  { 0, true },
7200  { 0, true },
7201  { 0, true },
7202  { 0, true },
7203  { 1, true },
7204  { 1, true },
7205  { 0, true },
7206  { 0, true },
7207  { 0, true },
7208  { 0, true },
7209  { 0, true },
7210  { 0, true },
7211  { 0, true },
7212  { 0, true },
7213  { 0, true },
7214  { 0, true },
7215  { 0, true },
7216  { 0, true },
7217  { 0, true },
7218  { 0, true },
7219  { 0, true },
7220  { 0, true },
7221  { 0, true },
7222  { 0, true },
7223  { 0, true },
7224  { 0, true },
7225  { 0, true },
7226  { 0, true },
7227  { 0, true },
7228  { 0, true },
7229  { 0, true },
7230  { 0, true },
7231  { 0, true },
7232  { 0, true },
7233  { 0, true },
7234  { 0, true },
7235  { 0, true },
7236  { 0, true },
7237  { 0, true },
7238  { 0, true },
7239  { 0, true },
7240  { 0, true },
7241  { 0, true },
7242  { 0, true },
7243  { 0, true },
7244  { 0, true },
7245  { 0, true },
7246  { 0, true },
7247  { 0, true },
7248  { 0, true },
7249  { 0, true },
7250  { 0, true },
7251  { 0, true },
7252  { 0, true },
7253  { 0, true },
7254  { 0, true },
7255  { 0, true },
7256  { 0, true },
7257  { 0, true },
7258  { 0, true },
7259  { 0, true },
7260  { 0, true },
7261  { 0, true },
7262  { 0, true },
7263  { 0, false },
7264  { 0, false },
7265  { 0, false },
7266  { 0, false },
7267  { 0, false },
7268  { 0, false },
7269  { 0, false },
7270  { 0, false },
7271  { 0, false },
7272  { 0, false },
7273  { 0, false },
7274  { 0, false },
7275  { 0, false },
7276  { 0, false },
7277  { 0, false },
7278  { 0, false },
7279  { 0, false },
7280  { 0, false },
7281  { 0, false },
7282  { 0, false },
7283  { 0, false },
7284  { 0, false },
7285  { 0, false },
7286  { 0, false },
7287  { 0, false },
7288  { 0, false },
7289  { 0, true },
7290  { 0, true },
7291  { 0, true },
7292  { 0, true },
7293  { 0, true },
7294  { 0, true },
7295  { 0, true },
7296  { 0, true },
7297  { 0, true },
7298  { 0, true },
7299  { 0, true },
7300  { 0, true },
7301  { 0, true },
7302  { 0, true },
7303  { 0, true },
7304  { 0, true },
7305  { 0, true },
7306  { 0, true },
7307  { 0, true },
7308  { 0, true },
7309  { 0, true },
7310  { 0, true },
7311  { 0, true },
7312  { 0, true },
7313  { 0, true },
7314  { 0, true },
7315  { 0, true },
7316  { 0, true },
7317  { 0, true },
7318};
7319unsigned ARMGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
7320  static const uint8_t RowMap[56] = {
7321    0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 4, 0, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 5, 5, 5, 2,
7322  };
7323  static const uint8_t Rows[8][56] = {
7324    { 1, 2, 3, 4, 5, 0, 7, 0, 0, 0, 0, 0, 13, 14, 0, 0, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 0, 0, 29, 30, 0, 0, 33, 34, 35, 36, 37, 38, 0, 0, 0, 0, 43, 0, 45, 0, 0, 0, 0, 0, 51, 0, 0, 0, 0, 0, },
7325    { 2, 3, 4, 5, 6, 0, 8, 0, 0, 0, 0, 0, 37, 49, 0, 0, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 0, 0, 31, 32, 0, 0, 35, 36, 43, 44, 14, 40, 0, 0, 0, 0, 46, 0, 48, 0, 0, 0, 0, 0, 53, 0, 0, 0, 0, 0, },
7326    { 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 14, 15, 0, 0, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 0, 0, 0, 0, 0, 0, 43, 44, 46, 47, 49, 0, 0, 0, 0, 0, 51, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7327    { 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 49, 55, 0, 0, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 0, 0, 0, 0, 0, 0, 46, 47, 51, 52, 15, 0, 0, 0, 0, 0, 53, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7328    { 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 0, 15, 16, 0, 0, 25, 26, 27, 28, 29, 30, 31, 32, 0, 0, 0, 0, 0, 0, 0, 0, 51, 52, 53, 54, 55, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7329    { 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 55, 0, 0, 0, 27, 28, 29, 30, 31, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 53, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7330    { 7, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 29, 30, 31, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7331    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7332  };
7333
7334  --IdxA; assert(IdxA < 56);
7335  --IdxB; assert(IdxB < 56);
7336  return Rows[RowMap[IdxA]][IdxB];
7337}
7338
7339  struct MaskRolOp {
7340    LaneBitmask Mask;
7341    uint8_t  RotateLeft;
7342  };
7343  static const MaskRolOp LaneMaskComposeSequences[] = {
7344    { LaneBitmask(0xFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
7345    { LaneBitmask(0xFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
7346    { LaneBitmask(0xFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
7347    { LaneBitmask(0xFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
7348    { LaneBitmask(0xFFFFFFFF),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 8
7349    { LaneBitmask(0xFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 },   // Sequence 10
7350    { LaneBitmask(0xFFFFFFFF), 12 }, { LaneBitmask::getNone(), 0 },   // Sequence 12
7351    { LaneBitmask(0xFFFFFFFF), 14 }, { LaneBitmask::getNone(), 0 },   // Sequence 14
7352    { LaneBitmask(0xFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 16
7353    { LaneBitmask(0xFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 18
7354    { LaneBitmask(0xFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 20
7355    { LaneBitmask(0xFFFFFFFF),  7 }, { LaneBitmask::getNone(), 0 },   // Sequence 22
7356    { LaneBitmask(0xFFFFFFFF),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 24
7357    { LaneBitmask(0xFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 },   // Sequence 26
7358    { LaneBitmask(0xFFFFFFFF), 13 }, { LaneBitmask::getNone(), 0 },   // Sequence 28
7359    { LaneBitmask(0xFFFFFFFF), 15 }, { LaneBitmask::getNone(), 0 },   // Sequence 30
7360    { LaneBitmask(0xFFFFFFFF), 16 }, { LaneBitmask::getNone(), 0 },   // Sequence 32
7361    { LaneBitmask(0xFFFFFFFF), 17 }, { LaneBitmask::getNone(), 0 }  // Sequence 34
7362  };
7363  static const MaskRolOp *const CompositeSequences[] = {
7364    &LaneMaskComposeSequences[0], // to dsub_0
7365    &LaneMaskComposeSequences[2], // to dsub_1
7366    &LaneMaskComposeSequences[4], // to dsub_2
7367    &LaneMaskComposeSequences[6], // to dsub_3
7368    &LaneMaskComposeSequences[8], // to dsub_4
7369    &LaneMaskComposeSequences[10], // to dsub_5
7370    &LaneMaskComposeSequences[12], // to dsub_6
7371    &LaneMaskComposeSequences[14], // to dsub_7
7372    &LaneMaskComposeSequences[0], // to gsub_0
7373    &LaneMaskComposeSequences[16], // to gsub_1
7374    &LaneMaskComposeSequences[0], // to qqsub_0
7375    &LaneMaskComposeSequences[8], // to qqsub_1
7376    &LaneMaskComposeSequences[0], // to qsub_0
7377    &LaneMaskComposeSequences[4], // to qsub_1
7378    &LaneMaskComposeSequences[8], // to qsub_2
7379    &LaneMaskComposeSequences[12], // to qsub_3
7380    &LaneMaskComposeSequences[2], // to ssub_0
7381    &LaneMaskComposeSequences[18], // to ssub_1
7382    &LaneMaskComposeSequences[4], // to ssub_2
7383    &LaneMaskComposeSequences[20], // to ssub_3
7384    &LaneMaskComposeSequences[6], // to ssub_4
7385    &LaneMaskComposeSequences[22], // to ssub_5
7386    &LaneMaskComposeSequences[8], // to ssub_6
7387    &LaneMaskComposeSequences[24], // to ssub_7
7388    &LaneMaskComposeSequences[10], // to ssub_8
7389    &LaneMaskComposeSequences[26], // to ssub_9
7390    &LaneMaskComposeSequences[12], // to ssub_10
7391    &LaneMaskComposeSequences[28], // to ssub_11
7392    &LaneMaskComposeSequences[14], // to ssub_12
7393    &LaneMaskComposeSequences[30], // to ssub_13
7394    &LaneMaskComposeSequences[32], // to dsub_7_then_ssub_0
7395    &LaneMaskComposeSequences[34], // to dsub_7_then_ssub_1
7396    &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_4_ssub_5
7397    &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7398    &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_6_ssub_7
7399    &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7400    &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_4_ssub_5
7401    &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7402    &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7403    &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7404    &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7405    &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7406    &LaneMaskComposeSequences[4], // to ssub_4_ssub_5_ssub_8_ssub_9
7407    &LaneMaskComposeSequences[4], // to ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7408    &LaneMaskComposeSequences[4], // to ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7409    &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_dsub_5
7410    &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7411    &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_dsub_5_dsub_7
7412    &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_ssub_8_ssub_9
7413    &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7414    &LaneMaskComposeSequences[8], // to ssub_8_ssub_9_ssub_12_ssub_13
7415    &LaneMaskComposeSequences[8], // to ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7416    &LaneMaskComposeSequences[10], // to dsub_5_dsub_7
7417    &LaneMaskComposeSequences[10], // to dsub_5_ssub_12_ssub_13_dsub_7
7418    &LaneMaskComposeSequences[10], // to dsub_5_ssub_12_ssub_13
7419    &LaneMaskComposeSequences[4] // to ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7420  };
7421
7422LaneBitmask ARMGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
7423  --IdxA; assert(IdxA < 56 && "Subregister index out of bounds");
7424  LaneBitmask Result;
7425  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
7426    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
7427    if (unsigned S = Ops->RotateLeft)
7428      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
7429    else
7430      Result |= LaneBitmask(M);
7431  }
7432  return Result;
7433}
7434
7435LaneBitmask ARMGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
7436  LaneMask &= getSubRegIndexLaneMask(IdxA);
7437  --IdxA; assert(IdxA < 56 && "Subregister index out of bounds");
7438  LaneBitmask Result;
7439  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
7440    LaneBitmask::Type M = LaneMask.getAsInteger();
7441    if (unsigned S = Ops->RotateLeft)
7442      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
7443    else
7444      Result |= LaneBitmask(M);
7445  }
7446  return Result;
7447}
7448
7449const TargetRegisterClass *ARMGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
7450  static const uint8_t Table[103][56] = {
7451    {	// HPR
7452      0,	// dsub_0
7453      0,	// dsub_1
7454      0,	// dsub_2
7455      0,	// dsub_3
7456      0,	// dsub_4
7457      0,	// dsub_5
7458      0,	// dsub_6
7459      0,	// dsub_7
7460      0,	// gsub_0
7461      0,	// gsub_1
7462      0,	// qqsub_0
7463      0,	// qqsub_1
7464      0,	// qsub_0
7465      0,	// qsub_1
7466      0,	// qsub_2
7467      0,	// qsub_3
7468      0,	// ssub_0
7469      0,	// ssub_1
7470      0,	// ssub_2
7471      0,	// ssub_3
7472      0,	// ssub_4
7473      0,	// ssub_5
7474      0,	// ssub_6
7475      0,	// ssub_7
7476      0,	// ssub_8
7477      0,	// ssub_9
7478      0,	// ssub_10
7479      0,	// ssub_11
7480      0,	// ssub_12
7481      0,	// ssub_13
7482      0,	// dsub_7_then_ssub_0
7483      0,	// dsub_7_then_ssub_1
7484      0,	// ssub_0_ssub_1_ssub_4_ssub_5
7485      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7486      0,	// ssub_2_ssub_3_ssub_6_ssub_7
7487      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7488      0,	// ssub_2_ssub_3_ssub_4_ssub_5
7489      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7490      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7491      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7492      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7493      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7494      0,	// ssub_4_ssub_5_ssub_8_ssub_9
7495      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7496      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7497      0,	// ssub_6_ssub_7_dsub_5
7498      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7499      0,	// ssub_6_ssub_7_dsub_5_dsub_7
7500      0,	// ssub_6_ssub_7_ssub_8_ssub_9
7501      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7502      0,	// ssub_8_ssub_9_ssub_12_ssub_13
7503      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7504      0,	// dsub_5_dsub_7
7505      0,	// dsub_5_ssub_12_ssub_13_dsub_7
7506      0,	// dsub_5_ssub_12_ssub_13
7507      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7508    },
7509    {	// SPR
7510      0,	// dsub_0
7511      0,	// dsub_1
7512      0,	// dsub_2
7513      0,	// dsub_3
7514      0,	// dsub_4
7515      0,	// dsub_5
7516      0,	// dsub_6
7517      0,	// dsub_7
7518      0,	// gsub_0
7519      0,	// gsub_1
7520      0,	// qqsub_0
7521      0,	// qqsub_1
7522      0,	// qsub_0
7523      0,	// qsub_1
7524      0,	// qsub_2
7525      0,	// qsub_3
7526      0,	// ssub_0
7527      0,	// ssub_1
7528      0,	// ssub_2
7529      0,	// ssub_3
7530      0,	// ssub_4
7531      0,	// ssub_5
7532      0,	// ssub_6
7533      0,	// ssub_7
7534      0,	// ssub_8
7535      0,	// ssub_9
7536      0,	// ssub_10
7537      0,	// ssub_11
7538      0,	// ssub_12
7539      0,	// ssub_13
7540      0,	// dsub_7_then_ssub_0
7541      0,	// dsub_7_then_ssub_1
7542      0,	// ssub_0_ssub_1_ssub_4_ssub_5
7543      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7544      0,	// ssub_2_ssub_3_ssub_6_ssub_7
7545      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7546      0,	// ssub_2_ssub_3_ssub_4_ssub_5
7547      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7548      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7549      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7550      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7551      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7552      0,	// ssub_4_ssub_5_ssub_8_ssub_9
7553      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7554      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7555      0,	// ssub_6_ssub_7_dsub_5
7556      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7557      0,	// ssub_6_ssub_7_dsub_5_dsub_7
7558      0,	// ssub_6_ssub_7_ssub_8_ssub_9
7559      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7560      0,	// ssub_8_ssub_9_ssub_12_ssub_13
7561      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7562      0,	// dsub_5_dsub_7
7563      0,	// dsub_5_ssub_12_ssub_13_dsub_7
7564      0,	// dsub_5_ssub_12_ssub_13
7565      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7566    },
7567    {	// GPR
7568      0,	// dsub_0
7569      0,	// dsub_1
7570      0,	// dsub_2
7571      0,	// dsub_3
7572      0,	// dsub_4
7573      0,	// dsub_5
7574      0,	// dsub_6
7575      0,	// dsub_7
7576      0,	// gsub_0
7577      0,	// gsub_1
7578      0,	// qqsub_0
7579      0,	// qqsub_1
7580      0,	// qsub_0
7581      0,	// qsub_1
7582      0,	// qsub_2
7583      0,	// qsub_3
7584      0,	// ssub_0
7585      0,	// ssub_1
7586      0,	// ssub_2
7587      0,	// ssub_3
7588      0,	// ssub_4
7589      0,	// ssub_5
7590      0,	// ssub_6
7591      0,	// ssub_7
7592      0,	// ssub_8
7593      0,	// ssub_9
7594      0,	// ssub_10
7595      0,	// ssub_11
7596      0,	// ssub_12
7597      0,	// ssub_13
7598      0,	// dsub_7_then_ssub_0
7599      0,	// dsub_7_then_ssub_1
7600      0,	// ssub_0_ssub_1_ssub_4_ssub_5
7601      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7602      0,	// ssub_2_ssub_3_ssub_6_ssub_7
7603      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7604      0,	// ssub_2_ssub_3_ssub_4_ssub_5
7605      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7606      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7607      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7608      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7609      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7610      0,	// ssub_4_ssub_5_ssub_8_ssub_9
7611      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7612      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7613      0,	// ssub_6_ssub_7_dsub_5
7614      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7615      0,	// ssub_6_ssub_7_dsub_5_dsub_7
7616      0,	// ssub_6_ssub_7_ssub_8_ssub_9
7617      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7618      0,	// ssub_8_ssub_9_ssub_12_ssub_13
7619      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7620      0,	// dsub_5_dsub_7
7621      0,	// dsub_5_ssub_12_ssub_13_dsub_7
7622      0,	// dsub_5_ssub_12_ssub_13
7623      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7624    },
7625    {	// GPRwithAPSR
7626      0,	// dsub_0
7627      0,	// dsub_1
7628      0,	// dsub_2
7629      0,	// dsub_3
7630      0,	// dsub_4
7631      0,	// dsub_5
7632      0,	// dsub_6
7633      0,	// dsub_7
7634      0,	// gsub_0
7635      0,	// gsub_1
7636      0,	// qqsub_0
7637      0,	// qqsub_1
7638      0,	// qsub_0
7639      0,	// qsub_1
7640      0,	// qsub_2
7641      0,	// qsub_3
7642      0,	// ssub_0
7643      0,	// ssub_1
7644      0,	// ssub_2
7645      0,	// ssub_3
7646      0,	// ssub_4
7647      0,	// ssub_5
7648      0,	// ssub_6
7649      0,	// ssub_7
7650      0,	// ssub_8
7651      0,	// ssub_9
7652      0,	// ssub_10
7653      0,	// ssub_11
7654      0,	// ssub_12
7655      0,	// ssub_13
7656      0,	// dsub_7_then_ssub_0
7657      0,	// dsub_7_then_ssub_1
7658      0,	// ssub_0_ssub_1_ssub_4_ssub_5
7659      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7660      0,	// ssub_2_ssub_3_ssub_6_ssub_7
7661      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7662      0,	// ssub_2_ssub_3_ssub_4_ssub_5
7663      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7664      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7665      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7666      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7667      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7668      0,	// ssub_4_ssub_5_ssub_8_ssub_9
7669      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7670      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7671      0,	// ssub_6_ssub_7_dsub_5
7672      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7673      0,	// ssub_6_ssub_7_dsub_5_dsub_7
7674      0,	// ssub_6_ssub_7_ssub_8_ssub_9
7675      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7676      0,	// ssub_8_ssub_9_ssub_12_ssub_13
7677      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7678      0,	// dsub_5_dsub_7
7679      0,	// dsub_5_ssub_12_ssub_13_dsub_7
7680      0,	// dsub_5_ssub_12_ssub_13
7681      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7682    },
7683    {	// SPR_8
7684      0,	// dsub_0
7685      0,	// dsub_1
7686      0,	// dsub_2
7687      0,	// dsub_3
7688      0,	// dsub_4
7689      0,	// dsub_5
7690      0,	// dsub_6
7691      0,	// dsub_7
7692      0,	// gsub_0
7693      0,	// gsub_1
7694      0,	// qqsub_0
7695      0,	// qqsub_1
7696      0,	// qsub_0
7697      0,	// qsub_1
7698      0,	// qsub_2
7699      0,	// qsub_3
7700      0,	// ssub_0
7701      0,	// ssub_1
7702      0,	// ssub_2
7703      0,	// ssub_3
7704      0,	// ssub_4
7705      0,	// ssub_5
7706      0,	// ssub_6
7707      0,	// ssub_7
7708      0,	// ssub_8
7709      0,	// ssub_9
7710      0,	// ssub_10
7711      0,	// ssub_11
7712      0,	// ssub_12
7713      0,	// ssub_13
7714      0,	// dsub_7_then_ssub_0
7715      0,	// dsub_7_then_ssub_1
7716      0,	// ssub_0_ssub_1_ssub_4_ssub_5
7717      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7718      0,	// ssub_2_ssub_3_ssub_6_ssub_7
7719      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7720      0,	// ssub_2_ssub_3_ssub_4_ssub_5
7721      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7722      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7723      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7724      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7725      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7726      0,	// ssub_4_ssub_5_ssub_8_ssub_9
7727      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7728      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7729      0,	// ssub_6_ssub_7_dsub_5
7730      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7731      0,	// ssub_6_ssub_7_dsub_5_dsub_7
7732      0,	// ssub_6_ssub_7_ssub_8_ssub_9
7733      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7734      0,	// ssub_8_ssub_9_ssub_12_ssub_13
7735      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7736      0,	// dsub_5_dsub_7
7737      0,	// dsub_5_ssub_12_ssub_13_dsub_7
7738      0,	// dsub_5_ssub_12_ssub_13
7739      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7740    },
7741    {	// GPRnopc
7742      0,	// dsub_0
7743      0,	// dsub_1
7744      0,	// dsub_2
7745      0,	// dsub_3
7746      0,	// dsub_4
7747      0,	// dsub_5
7748      0,	// dsub_6
7749      0,	// dsub_7
7750      0,	// gsub_0
7751      0,	// gsub_1
7752      0,	// qqsub_0
7753      0,	// qqsub_1
7754      0,	// qsub_0
7755      0,	// qsub_1
7756      0,	// qsub_2
7757      0,	// qsub_3
7758      0,	// ssub_0
7759      0,	// ssub_1
7760      0,	// ssub_2
7761      0,	// ssub_3
7762      0,	// ssub_4
7763      0,	// ssub_5
7764      0,	// ssub_6
7765      0,	// ssub_7
7766      0,	// ssub_8
7767      0,	// ssub_9
7768      0,	// ssub_10
7769      0,	// ssub_11
7770      0,	// ssub_12
7771      0,	// ssub_13
7772      0,	// dsub_7_then_ssub_0
7773      0,	// dsub_7_then_ssub_1
7774      0,	// ssub_0_ssub_1_ssub_4_ssub_5
7775      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7776      0,	// ssub_2_ssub_3_ssub_6_ssub_7
7777      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7778      0,	// ssub_2_ssub_3_ssub_4_ssub_5
7779      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7780      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7781      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7782      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7783      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7784      0,	// ssub_4_ssub_5_ssub_8_ssub_9
7785      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7786      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7787      0,	// ssub_6_ssub_7_dsub_5
7788      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7789      0,	// ssub_6_ssub_7_dsub_5_dsub_7
7790      0,	// ssub_6_ssub_7_ssub_8_ssub_9
7791      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7792      0,	// ssub_8_ssub_9_ssub_12_ssub_13
7793      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7794      0,	// dsub_5_dsub_7
7795      0,	// dsub_5_ssub_12_ssub_13_dsub_7
7796      0,	// dsub_5_ssub_12_ssub_13
7797      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7798    },
7799    {	// rGPR
7800      0,	// dsub_0
7801      0,	// dsub_1
7802      0,	// dsub_2
7803      0,	// dsub_3
7804      0,	// dsub_4
7805      0,	// dsub_5
7806      0,	// dsub_6
7807      0,	// dsub_7
7808      0,	// gsub_0
7809      0,	// gsub_1
7810      0,	// qqsub_0
7811      0,	// qqsub_1
7812      0,	// qsub_0
7813      0,	// qsub_1
7814      0,	// qsub_2
7815      0,	// qsub_3
7816      0,	// ssub_0
7817      0,	// ssub_1
7818      0,	// ssub_2
7819      0,	// ssub_3
7820      0,	// ssub_4
7821      0,	// ssub_5
7822      0,	// ssub_6
7823      0,	// ssub_7
7824      0,	// ssub_8
7825      0,	// ssub_9
7826      0,	// ssub_10
7827      0,	// ssub_11
7828      0,	// ssub_12
7829      0,	// ssub_13
7830      0,	// dsub_7_then_ssub_0
7831      0,	// dsub_7_then_ssub_1
7832      0,	// ssub_0_ssub_1_ssub_4_ssub_5
7833      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7834      0,	// ssub_2_ssub_3_ssub_6_ssub_7
7835      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7836      0,	// ssub_2_ssub_3_ssub_4_ssub_5
7837      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7838      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7839      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7840      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7841      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7842      0,	// ssub_4_ssub_5_ssub_8_ssub_9
7843      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7844      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7845      0,	// ssub_6_ssub_7_dsub_5
7846      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7847      0,	// ssub_6_ssub_7_dsub_5_dsub_7
7848      0,	// ssub_6_ssub_7_ssub_8_ssub_9
7849      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7850      0,	// ssub_8_ssub_9_ssub_12_ssub_13
7851      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7852      0,	// dsub_5_dsub_7
7853      0,	// dsub_5_ssub_12_ssub_13_dsub_7
7854      0,	// dsub_5_ssub_12_ssub_13
7855      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7856    },
7857    {	// tGPRwithpc
7858      0,	// dsub_0
7859      0,	// dsub_1
7860      0,	// dsub_2
7861      0,	// dsub_3
7862      0,	// dsub_4
7863      0,	// dsub_5
7864      0,	// dsub_6
7865      0,	// dsub_7
7866      0,	// gsub_0
7867      0,	// gsub_1
7868      0,	// qqsub_0
7869      0,	// qqsub_1
7870      0,	// qsub_0
7871      0,	// qsub_1
7872      0,	// qsub_2
7873      0,	// qsub_3
7874      0,	// ssub_0
7875      0,	// ssub_1
7876      0,	// ssub_2
7877      0,	// ssub_3
7878      0,	// ssub_4
7879      0,	// ssub_5
7880      0,	// ssub_6
7881      0,	// ssub_7
7882      0,	// ssub_8
7883      0,	// ssub_9
7884      0,	// ssub_10
7885      0,	// ssub_11
7886      0,	// ssub_12
7887      0,	// ssub_13
7888      0,	// dsub_7_then_ssub_0
7889      0,	// dsub_7_then_ssub_1
7890      0,	// ssub_0_ssub_1_ssub_4_ssub_5
7891      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7892      0,	// ssub_2_ssub_3_ssub_6_ssub_7
7893      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7894      0,	// ssub_2_ssub_3_ssub_4_ssub_5
7895      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7896      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7897      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7898      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7899      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7900      0,	// ssub_4_ssub_5_ssub_8_ssub_9
7901      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7902      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7903      0,	// ssub_6_ssub_7_dsub_5
7904      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7905      0,	// ssub_6_ssub_7_dsub_5_dsub_7
7906      0,	// ssub_6_ssub_7_ssub_8_ssub_9
7907      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7908      0,	// ssub_8_ssub_9_ssub_12_ssub_13
7909      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7910      0,	// dsub_5_dsub_7
7911      0,	// dsub_5_ssub_12_ssub_13_dsub_7
7912      0,	// dsub_5_ssub_12_ssub_13
7913      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7914    },
7915    {	// hGPR
7916      0,	// dsub_0
7917      0,	// dsub_1
7918      0,	// dsub_2
7919      0,	// dsub_3
7920      0,	// dsub_4
7921      0,	// dsub_5
7922      0,	// dsub_6
7923      0,	// dsub_7
7924      0,	// gsub_0
7925      0,	// gsub_1
7926      0,	// qqsub_0
7927      0,	// qqsub_1
7928      0,	// qsub_0
7929      0,	// qsub_1
7930      0,	// qsub_2
7931      0,	// qsub_3
7932      0,	// ssub_0
7933      0,	// ssub_1
7934      0,	// ssub_2
7935      0,	// ssub_3
7936      0,	// ssub_4
7937      0,	// ssub_5
7938      0,	// ssub_6
7939      0,	// ssub_7
7940      0,	// ssub_8
7941      0,	// ssub_9
7942      0,	// ssub_10
7943      0,	// ssub_11
7944      0,	// ssub_12
7945      0,	// ssub_13
7946      0,	// dsub_7_then_ssub_0
7947      0,	// dsub_7_then_ssub_1
7948      0,	// ssub_0_ssub_1_ssub_4_ssub_5
7949      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
7950      0,	// ssub_2_ssub_3_ssub_6_ssub_7
7951      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
7952      0,	// ssub_2_ssub_3_ssub_4_ssub_5
7953      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
7954      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7955      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
7956      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
7957      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7958      0,	// ssub_4_ssub_5_ssub_8_ssub_9
7959      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
7960      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
7961      0,	// ssub_6_ssub_7_dsub_5
7962      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
7963      0,	// ssub_6_ssub_7_dsub_5_dsub_7
7964      0,	// ssub_6_ssub_7_ssub_8_ssub_9
7965      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7966      0,	// ssub_8_ssub_9_ssub_12_ssub_13
7967      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
7968      0,	// dsub_5_dsub_7
7969      0,	// dsub_5_ssub_12_ssub_13_dsub_7
7970      0,	// dsub_5_ssub_12_ssub_13
7971      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
7972    },
7973    {	// tGPR
7974      0,	// dsub_0
7975      0,	// dsub_1
7976      0,	// dsub_2
7977      0,	// dsub_3
7978      0,	// dsub_4
7979      0,	// dsub_5
7980      0,	// dsub_6
7981      0,	// dsub_7
7982      0,	// gsub_0
7983      0,	// gsub_1
7984      0,	// qqsub_0
7985      0,	// qqsub_1
7986      0,	// qsub_0
7987      0,	// qsub_1
7988      0,	// qsub_2
7989      0,	// qsub_3
7990      0,	// ssub_0
7991      0,	// ssub_1
7992      0,	// ssub_2
7993      0,	// ssub_3
7994      0,	// ssub_4
7995      0,	// ssub_5
7996      0,	// ssub_6
7997      0,	// ssub_7
7998      0,	// ssub_8
7999      0,	// ssub_9
8000      0,	// ssub_10
8001      0,	// ssub_11
8002      0,	// ssub_12
8003      0,	// ssub_13
8004      0,	// dsub_7_then_ssub_0
8005      0,	// dsub_7_then_ssub_1
8006      0,	// ssub_0_ssub_1_ssub_4_ssub_5
8007      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8008      0,	// ssub_2_ssub_3_ssub_6_ssub_7
8009      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8010      0,	// ssub_2_ssub_3_ssub_4_ssub_5
8011      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8012      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8013      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8014      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8015      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8016      0,	// ssub_4_ssub_5_ssub_8_ssub_9
8017      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8018      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8019      0,	// ssub_6_ssub_7_dsub_5
8020      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8021      0,	// ssub_6_ssub_7_dsub_5_dsub_7
8022      0,	// ssub_6_ssub_7_ssub_8_ssub_9
8023      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8024      0,	// ssub_8_ssub_9_ssub_12_ssub_13
8025      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8026      0,	// dsub_5_dsub_7
8027      0,	// dsub_5_ssub_12_ssub_13_dsub_7
8028      0,	// dsub_5_ssub_12_ssub_13
8029      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8030    },
8031    {	// GPRnopc_and_hGPR
8032      0,	// dsub_0
8033      0,	// dsub_1
8034      0,	// dsub_2
8035      0,	// dsub_3
8036      0,	// dsub_4
8037      0,	// dsub_5
8038      0,	// dsub_6
8039      0,	// dsub_7
8040      0,	// gsub_0
8041      0,	// gsub_1
8042      0,	// qqsub_0
8043      0,	// qqsub_1
8044      0,	// qsub_0
8045      0,	// qsub_1
8046      0,	// qsub_2
8047      0,	// qsub_3
8048      0,	// ssub_0
8049      0,	// ssub_1
8050      0,	// ssub_2
8051      0,	// ssub_3
8052      0,	// ssub_4
8053      0,	// ssub_5
8054      0,	// ssub_6
8055      0,	// ssub_7
8056      0,	// ssub_8
8057      0,	// ssub_9
8058      0,	// ssub_10
8059      0,	// ssub_11
8060      0,	// ssub_12
8061      0,	// ssub_13
8062      0,	// dsub_7_then_ssub_0
8063      0,	// dsub_7_then_ssub_1
8064      0,	// ssub_0_ssub_1_ssub_4_ssub_5
8065      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8066      0,	// ssub_2_ssub_3_ssub_6_ssub_7
8067      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8068      0,	// ssub_2_ssub_3_ssub_4_ssub_5
8069      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8070      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8071      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8072      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8073      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8074      0,	// ssub_4_ssub_5_ssub_8_ssub_9
8075      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8076      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8077      0,	// ssub_6_ssub_7_dsub_5
8078      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8079      0,	// ssub_6_ssub_7_dsub_5_dsub_7
8080      0,	// ssub_6_ssub_7_ssub_8_ssub_9
8081      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8082      0,	// ssub_8_ssub_9_ssub_12_ssub_13
8083      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8084      0,	// dsub_5_dsub_7
8085      0,	// dsub_5_ssub_12_ssub_13_dsub_7
8086      0,	// dsub_5_ssub_12_ssub_13
8087      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8088    },
8089    {	// hGPR_and_rGPR
8090      0,	// dsub_0
8091      0,	// dsub_1
8092      0,	// dsub_2
8093      0,	// dsub_3
8094      0,	// dsub_4
8095      0,	// dsub_5
8096      0,	// dsub_6
8097      0,	// dsub_7
8098      0,	// gsub_0
8099      0,	// gsub_1
8100      0,	// qqsub_0
8101      0,	// qqsub_1
8102      0,	// qsub_0
8103      0,	// qsub_1
8104      0,	// qsub_2
8105      0,	// qsub_3
8106      0,	// ssub_0
8107      0,	// ssub_1
8108      0,	// ssub_2
8109      0,	// ssub_3
8110      0,	// ssub_4
8111      0,	// ssub_5
8112      0,	// ssub_6
8113      0,	// ssub_7
8114      0,	// ssub_8
8115      0,	// ssub_9
8116      0,	// ssub_10
8117      0,	// ssub_11
8118      0,	// ssub_12
8119      0,	// ssub_13
8120      0,	// dsub_7_then_ssub_0
8121      0,	// dsub_7_then_ssub_1
8122      0,	// ssub_0_ssub_1_ssub_4_ssub_5
8123      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8124      0,	// ssub_2_ssub_3_ssub_6_ssub_7
8125      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8126      0,	// ssub_2_ssub_3_ssub_4_ssub_5
8127      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8128      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8129      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8130      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8131      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8132      0,	// ssub_4_ssub_5_ssub_8_ssub_9
8133      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8134      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8135      0,	// ssub_6_ssub_7_dsub_5
8136      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8137      0,	// ssub_6_ssub_7_dsub_5_dsub_7
8138      0,	// ssub_6_ssub_7_ssub_8_ssub_9
8139      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8140      0,	// ssub_8_ssub_9_ssub_12_ssub_13
8141      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8142      0,	// dsub_5_dsub_7
8143      0,	// dsub_5_ssub_12_ssub_13_dsub_7
8144      0,	// dsub_5_ssub_12_ssub_13
8145      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8146    },
8147    {	// tcGPR
8148      0,	// dsub_0
8149      0,	// dsub_1
8150      0,	// dsub_2
8151      0,	// dsub_3
8152      0,	// dsub_4
8153      0,	// dsub_5
8154      0,	// dsub_6
8155      0,	// dsub_7
8156      0,	// gsub_0
8157      0,	// gsub_1
8158      0,	// qqsub_0
8159      0,	// qqsub_1
8160      0,	// qsub_0
8161      0,	// qsub_1
8162      0,	// qsub_2
8163      0,	// qsub_3
8164      0,	// ssub_0
8165      0,	// ssub_1
8166      0,	// ssub_2
8167      0,	// ssub_3
8168      0,	// ssub_4
8169      0,	// ssub_5
8170      0,	// ssub_6
8171      0,	// ssub_7
8172      0,	// ssub_8
8173      0,	// ssub_9
8174      0,	// ssub_10
8175      0,	// ssub_11
8176      0,	// ssub_12
8177      0,	// ssub_13
8178      0,	// dsub_7_then_ssub_0
8179      0,	// dsub_7_then_ssub_1
8180      0,	// ssub_0_ssub_1_ssub_4_ssub_5
8181      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8182      0,	// ssub_2_ssub_3_ssub_6_ssub_7
8183      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8184      0,	// ssub_2_ssub_3_ssub_4_ssub_5
8185      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8186      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8187      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8188      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8189      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8190      0,	// ssub_4_ssub_5_ssub_8_ssub_9
8191      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8192      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8193      0,	// ssub_6_ssub_7_dsub_5
8194      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8195      0,	// ssub_6_ssub_7_dsub_5_dsub_7
8196      0,	// ssub_6_ssub_7_ssub_8_ssub_9
8197      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8198      0,	// ssub_8_ssub_9_ssub_12_ssub_13
8199      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8200      0,	// dsub_5_dsub_7
8201      0,	// dsub_5_ssub_12_ssub_13_dsub_7
8202      0,	// dsub_5_ssub_12_ssub_13
8203      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8204    },
8205    {	// tGPR_and_tcGPR
8206      0,	// dsub_0
8207      0,	// dsub_1
8208      0,	// dsub_2
8209      0,	// dsub_3
8210      0,	// dsub_4
8211      0,	// dsub_5
8212      0,	// dsub_6
8213      0,	// dsub_7
8214      0,	// gsub_0
8215      0,	// gsub_1
8216      0,	// qqsub_0
8217      0,	// qqsub_1
8218      0,	// qsub_0
8219      0,	// qsub_1
8220      0,	// qsub_2
8221      0,	// qsub_3
8222      0,	// ssub_0
8223      0,	// ssub_1
8224      0,	// ssub_2
8225      0,	// ssub_3
8226      0,	// ssub_4
8227      0,	// ssub_5
8228      0,	// ssub_6
8229      0,	// ssub_7
8230      0,	// ssub_8
8231      0,	// ssub_9
8232      0,	// ssub_10
8233      0,	// ssub_11
8234      0,	// ssub_12
8235      0,	// ssub_13
8236      0,	// dsub_7_then_ssub_0
8237      0,	// dsub_7_then_ssub_1
8238      0,	// ssub_0_ssub_1_ssub_4_ssub_5
8239      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8240      0,	// ssub_2_ssub_3_ssub_6_ssub_7
8241      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8242      0,	// ssub_2_ssub_3_ssub_4_ssub_5
8243      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8244      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8245      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8246      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8247      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8248      0,	// ssub_4_ssub_5_ssub_8_ssub_9
8249      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8250      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8251      0,	// ssub_6_ssub_7_dsub_5
8252      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8253      0,	// ssub_6_ssub_7_dsub_5_dsub_7
8254      0,	// ssub_6_ssub_7_ssub_8_ssub_9
8255      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8256      0,	// ssub_8_ssub_9_ssub_12_ssub_13
8257      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8258      0,	// dsub_5_dsub_7
8259      0,	// dsub_5_ssub_12_ssub_13_dsub_7
8260      0,	// dsub_5_ssub_12_ssub_13
8261      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8262    },
8263    {	// CCR
8264      0,	// dsub_0
8265      0,	// dsub_1
8266      0,	// dsub_2
8267      0,	// dsub_3
8268      0,	// dsub_4
8269      0,	// dsub_5
8270      0,	// dsub_6
8271      0,	// dsub_7
8272      0,	// gsub_0
8273      0,	// gsub_1
8274      0,	// qqsub_0
8275      0,	// qqsub_1
8276      0,	// qsub_0
8277      0,	// qsub_1
8278      0,	// qsub_2
8279      0,	// qsub_3
8280      0,	// ssub_0
8281      0,	// ssub_1
8282      0,	// ssub_2
8283      0,	// ssub_3
8284      0,	// ssub_4
8285      0,	// ssub_5
8286      0,	// ssub_6
8287      0,	// ssub_7
8288      0,	// ssub_8
8289      0,	// ssub_9
8290      0,	// ssub_10
8291      0,	// ssub_11
8292      0,	// ssub_12
8293      0,	// ssub_13
8294      0,	// dsub_7_then_ssub_0
8295      0,	// dsub_7_then_ssub_1
8296      0,	// ssub_0_ssub_1_ssub_4_ssub_5
8297      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8298      0,	// ssub_2_ssub_3_ssub_6_ssub_7
8299      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8300      0,	// ssub_2_ssub_3_ssub_4_ssub_5
8301      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8302      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8303      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8304      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8305      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8306      0,	// ssub_4_ssub_5_ssub_8_ssub_9
8307      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8308      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8309      0,	// ssub_6_ssub_7_dsub_5
8310      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8311      0,	// ssub_6_ssub_7_dsub_5_dsub_7
8312      0,	// ssub_6_ssub_7_ssub_8_ssub_9
8313      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8314      0,	// ssub_8_ssub_9_ssub_12_ssub_13
8315      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8316      0,	// dsub_5_dsub_7
8317      0,	// dsub_5_ssub_12_ssub_13_dsub_7
8318      0,	// dsub_5_ssub_12_ssub_13
8319      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8320    },
8321    {	// GPRsp
8322      0,	// dsub_0
8323      0,	// dsub_1
8324      0,	// dsub_2
8325      0,	// dsub_3
8326      0,	// dsub_4
8327      0,	// dsub_5
8328      0,	// dsub_6
8329      0,	// dsub_7
8330      0,	// gsub_0
8331      0,	// gsub_1
8332      0,	// qqsub_0
8333      0,	// qqsub_1
8334      0,	// qsub_0
8335      0,	// qsub_1
8336      0,	// qsub_2
8337      0,	// qsub_3
8338      0,	// ssub_0
8339      0,	// ssub_1
8340      0,	// ssub_2
8341      0,	// ssub_3
8342      0,	// ssub_4
8343      0,	// ssub_5
8344      0,	// ssub_6
8345      0,	// ssub_7
8346      0,	// ssub_8
8347      0,	// ssub_9
8348      0,	// ssub_10
8349      0,	// ssub_11
8350      0,	// ssub_12
8351      0,	// ssub_13
8352      0,	// dsub_7_then_ssub_0
8353      0,	// dsub_7_then_ssub_1
8354      0,	// ssub_0_ssub_1_ssub_4_ssub_5
8355      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8356      0,	// ssub_2_ssub_3_ssub_6_ssub_7
8357      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8358      0,	// ssub_2_ssub_3_ssub_4_ssub_5
8359      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8360      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8361      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8362      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8363      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8364      0,	// ssub_4_ssub_5_ssub_8_ssub_9
8365      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8366      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8367      0,	// ssub_6_ssub_7_dsub_5
8368      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8369      0,	// ssub_6_ssub_7_dsub_5_dsub_7
8370      0,	// ssub_6_ssub_7_ssub_8_ssub_9
8371      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8372      0,	// ssub_8_ssub_9_ssub_12_ssub_13
8373      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8374      0,	// dsub_5_dsub_7
8375      0,	// dsub_5_ssub_12_ssub_13_dsub_7
8376      0,	// dsub_5_ssub_12_ssub_13
8377      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8378    },
8379    {	// hGPR_and_tGPRwithpc
8380      0,	// dsub_0
8381      0,	// dsub_1
8382      0,	// dsub_2
8383      0,	// dsub_3
8384      0,	// dsub_4
8385      0,	// dsub_5
8386      0,	// dsub_6
8387      0,	// dsub_7
8388      0,	// gsub_0
8389      0,	// gsub_1
8390      0,	// qqsub_0
8391      0,	// qqsub_1
8392      0,	// qsub_0
8393      0,	// qsub_1
8394      0,	// qsub_2
8395      0,	// qsub_3
8396      0,	// ssub_0
8397      0,	// ssub_1
8398      0,	// ssub_2
8399      0,	// ssub_3
8400      0,	// ssub_4
8401      0,	// ssub_5
8402      0,	// ssub_6
8403      0,	// ssub_7
8404      0,	// ssub_8
8405      0,	// ssub_9
8406      0,	// ssub_10
8407      0,	// ssub_11
8408      0,	// ssub_12
8409      0,	// ssub_13
8410      0,	// dsub_7_then_ssub_0
8411      0,	// dsub_7_then_ssub_1
8412      0,	// ssub_0_ssub_1_ssub_4_ssub_5
8413      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8414      0,	// ssub_2_ssub_3_ssub_6_ssub_7
8415      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8416      0,	// ssub_2_ssub_3_ssub_4_ssub_5
8417      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8418      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8419      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8420      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8421      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8422      0,	// ssub_4_ssub_5_ssub_8_ssub_9
8423      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8424      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8425      0,	// ssub_6_ssub_7_dsub_5
8426      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8427      0,	// ssub_6_ssub_7_dsub_5_dsub_7
8428      0,	// ssub_6_ssub_7_ssub_8_ssub_9
8429      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8430      0,	// ssub_8_ssub_9_ssub_12_ssub_13
8431      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8432      0,	// dsub_5_dsub_7
8433      0,	// dsub_5_ssub_12_ssub_13_dsub_7
8434      0,	// dsub_5_ssub_12_ssub_13
8435      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8436    },
8437    {	// hGPR_and_tcGPR
8438      0,	// dsub_0
8439      0,	// dsub_1
8440      0,	// dsub_2
8441      0,	// dsub_3
8442      0,	// dsub_4
8443      0,	// dsub_5
8444      0,	// dsub_6
8445      0,	// dsub_7
8446      0,	// gsub_0
8447      0,	// gsub_1
8448      0,	// qqsub_0
8449      0,	// qqsub_1
8450      0,	// qsub_0
8451      0,	// qsub_1
8452      0,	// qsub_2
8453      0,	// qsub_3
8454      0,	// ssub_0
8455      0,	// ssub_1
8456      0,	// ssub_2
8457      0,	// ssub_3
8458      0,	// ssub_4
8459      0,	// ssub_5
8460      0,	// ssub_6
8461      0,	// ssub_7
8462      0,	// ssub_8
8463      0,	// ssub_9
8464      0,	// ssub_10
8465      0,	// ssub_11
8466      0,	// ssub_12
8467      0,	// ssub_13
8468      0,	// dsub_7_then_ssub_0
8469      0,	// dsub_7_then_ssub_1
8470      0,	// ssub_0_ssub_1_ssub_4_ssub_5
8471      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8472      0,	// ssub_2_ssub_3_ssub_6_ssub_7
8473      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8474      0,	// ssub_2_ssub_3_ssub_4_ssub_5
8475      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8476      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8477      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8478      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8479      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8480      0,	// ssub_4_ssub_5_ssub_8_ssub_9
8481      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8482      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8483      0,	// ssub_6_ssub_7_dsub_5
8484      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8485      0,	// ssub_6_ssub_7_dsub_5_dsub_7
8486      0,	// ssub_6_ssub_7_ssub_8_ssub_9
8487      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8488      0,	// ssub_8_ssub_9_ssub_12_ssub_13
8489      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8490      0,	// dsub_5_dsub_7
8491      0,	// dsub_5_ssub_12_ssub_13_dsub_7
8492      0,	// dsub_5_ssub_12_ssub_13
8493      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8494    },
8495    {	// DPR
8496      0,	// dsub_0
8497      0,	// dsub_1
8498      0,	// dsub_2
8499      0,	// dsub_3
8500      0,	// dsub_4
8501      0,	// dsub_5
8502      0,	// dsub_6
8503      0,	// dsub_7
8504      0,	// gsub_0
8505      0,	// gsub_1
8506      0,	// qqsub_0
8507      0,	// qqsub_1
8508      0,	// qsub_0
8509      0,	// qsub_1
8510      0,	// qsub_2
8511      0,	// qsub_3
8512      20,	// ssub_0 -> DPR_VFP2
8513      20,	// ssub_1 -> DPR_VFP2
8514      0,	// ssub_2
8515      0,	// ssub_3
8516      0,	// ssub_4
8517      0,	// ssub_5
8518      0,	// ssub_6
8519      0,	// ssub_7
8520      0,	// ssub_8
8521      0,	// ssub_9
8522      0,	// ssub_10
8523      0,	// ssub_11
8524      0,	// ssub_12
8525      0,	// ssub_13
8526      0,	// dsub_7_then_ssub_0
8527      0,	// dsub_7_then_ssub_1
8528      0,	// ssub_0_ssub_1_ssub_4_ssub_5
8529      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8530      0,	// ssub_2_ssub_3_ssub_6_ssub_7
8531      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8532      0,	// ssub_2_ssub_3_ssub_4_ssub_5
8533      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8534      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8535      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8536      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8537      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8538      0,	// ssub_4_ssub_5_ssub_8_ssub_9
8539      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8540      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8541      0,	// ssub_6_ssub_7_dsub_5
8542      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8543      0,	// ssub_6_ssub_7_dsub_5_dsub_7
8544      0,	// ssub_6_ssub_7_ssub_8_ssub_9
8545      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8546      0,	// ssub_8_ssub_9_ssub_12_ssub_13
8547      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8548      0,	// dsub_5_dsub_7
8549      0,	// dsub_5_ssub_12_ssub_13_dsub_7
8550      0,	// dsub_5_ssub_12_ssub_13
8551      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8552    },
8553    {	// DPR_VFP2
8554      0,	// dsub_0
8555      0,	// dsub_1
8556      0,	// dsub_2
8557      0,	// dsub_3
8558      0,	// dsub_4
8559      0,	// dsub_5
8560      0,	// dsub_6
8561      0,	// dsub_7
8562      0,	// gsub_0
8563      0,	// gsub_1
8564      0,	// qqsub_0
8565      0,	// qqsub_1
8566      0,	// qsub_0
8567      0,	// qsub_1
8568      0,	// qsub_2
8569      0,	// qsub_3
8570      20,	// ssub_0 -> DPR_VFP2
8571      20,	// ssub_1 -> DPR_VFP2
8572      0,	// ssub_2
8573      0,	// ssub_3
8574      0,	// ssub_4
8575      0,	// ssub_5
8576      0,	// ssub_6
8577      0,	// ssub_7
8578      0,	// ssub_8
8579      0,	// ssub_9
8580      0,	// ssub_10
8581      0,	// ssub_11
8582      0,	// ssub_12
8583      0,	// ssub_13
8584      0,	// dsub_7_then_ssub_0
8585      0,	// dsub_7_then_ssub_1
8586      0,	// ssub_0_ssub_1_ssub_4_ssub_5
8587      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8588      0,	// ssub_2_ssub_3_ssub_6_ssub_7
8589      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8590      0,	// ssub_2_ssub_3_ssub_4_ssub_5
8591      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8592      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8593      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8594      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8595      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8596      0,	// ssub_4_ssub_5_ssub_8_ssub_9
8597      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8598      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8599      0,	// ssub_6_ssub_7_dsub_5
8600      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8601      0,	// ssub_6_ssub_7_dsub_5_dsub_7
8602      0,	// ssub_6_ssub_7_ssub_8_ssub_9
8603      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8604      0,	// ssub_8_ssub_9_ssub_12_ssub_13
8605      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8606      0,	// dsub_5_dsub_7
8607      0,	// dsub_5_ssub_12_ssub_13_dsub_7
8608      0,	// dsub_5_ssub_12_ssub_13
8609      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8610    },
8611    {	// DPR_8
8612      0,	// dsub_0
8613      0,	// dsub_1
8614      0,	// dsub_2
8615      0,	// dsub_3
8616      0,	// dsub_4
8617      0,	// dsub_5
8618      0,	// dsub_6
8619      0,	// dsub_7
8620      0,	// gsub_0
8621      0,	// gsub_1
8622      0,	// qqsub_0
8623      0,	// qqsub_1
8624      0,	// qsub_0
8625      0,	// qsub_1
8626      0,	// qsub_2
8627      0,	// qsub_3
8628      21,	// ssub_0 -> DPR_8
8629      21,	// ssub_1 -> DPR_8
8630      0,	// ssub_2
8631      0,	// ssub_3
8632      0,	// ssub_4
8633      0,	// ssub_5
8634      0,	// ssub_6
8635      0,	// ssub_7
8636      0,	// ssub_8
8637      0,	// ssub_9
8638      0,	// ssub_10
8639      0,	// ssub_11
8640      0,	// ssub_12
8641      0,	// ssub_13
8642      0,	// dsub_7_then_ssub_0
8643      0,	// dsub_7_then_ssub_1
8644      0,	// ssub_0_ssub_1_ssub_4_ssub_5
8645      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8646      0,	// ssub_2_ssub_3_ssub_6_ssub_7
8647      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8648      0,	// ssub_2_ssub_3_ssub_4_ssub_5
8649      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8650      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8651      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8652      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8653      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8654      0,	// ssub_4_ssub_5_ssub_8_ssub_9
8655      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8656      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8657      0,	// ssub_6_ssub_7_dsub_5
8658      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8659      0,	// ssub_6_ssub_7_dsub_5_dsub_7
8660      0,	// ssub_6_ssub_7_ssub_8_ssub_9
8661      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8662      0,	// ssub_8_ssub_9_ssub_12_ssub_13
8663      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8664      0,	// dsub_5_dsub_7
8665      0,	// dsub_5_ssub_12_ssub_13_dsub_7
8666      0,	// dsub_5_ssub_12_ssub_13
8667      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8668    },
8669    {	// GPRPair
8670      0,	// dsub_0
8671      0,	// dsub_1
8672      0,	// dsub_2
8673      0,	// dsub_3
8674      0,	// dsub_4
8675      0,	// dsub_5
8676      0,	// dsub_6
8677      0,	// dsub_7
8678      22,	// gsub_0 -> GPRPair
8679      22,	// gsub_1 -> GPRPair
8680      0,	// qqsub_0
8681      0,	// qqsub_1
8682      0,	// qsub_0
8683      0,	// qsub_1
8684      0,	// qsub_2
8685      0,	// qsub_3
8686      0,	// ssub_0
8687      0,	// ssub_1
8688      0,	// ssub_2
8689      0,	// ssub_3
8690      0,	// ssub_4
8691      0,	// ssub_5
8692      0,	// ssub_6
8693      0,	// ssub_7
8694      0,	// ssub_8
8695      0,	// ssub_9
8696      0,	// ssub_10
8697      0,	// ssub_11
8698      0,	// ssub_12
8699      0,	// ssub_13
8700      0,	// dsub_7_then_ssub_0
8701      0,	// dsub_7_then_ssub_1
8702      0,	// ssub_0_ssub_1_ssub_4_ssub_5
8703      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8704      0,	// ssub_2_ssub_3_ssub_6_ssub_7
8705      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8706      0,	// ssub_2_ssub_3_ssub_4_ssub_5
8707      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8708      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8709      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8710      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8711      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8712      0,	// ssub_4_ssub_5_ssub_8_ssub_9
8713      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8714      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8715      0,	// ssub_6_ssub_7_dsub_5
8716      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8717      0,	// ssub_6_ssub_7_dsub_5_dsub_7
8718      0,	// ssub_6_ssub_7_ssub_8_ssub_9
8719      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8720      0,	// ssub_8_ssub_9_ssub_12_ssub_13
8721      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8722      0,	// dsub_5_dsub_7
8723      0,	// dsub_5_ssub_12_ssub_13_dsub_7
8724      0,	// dsub_5_ssub_12_ssub_13
8725      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8726    },
8727    {	// GPRPair_with_gsub_1_in_rGPR
8728      0,	// dsub_0
8729      0,	// dsub_1
8730      0,	// dsub_2
8731      0,	// dsub_3
8732      0,	// dsub_4
8733      0,	// dsub_5
8734      0,	// dsub_6
8735      0,	// dsub_7
8736      23,	// gsub_0 -> GPRPair_with_gsub_1_in_rGPR
8737      23,	// gsub_1 -> GPRPair_with_gsub_1_in_rGPR
8738      0,	// qqsub_0
8739      0,	// qqsub_1
8740      0,	// qsub_0
8741      0,	// qsub_1
8742      0,	// qsub_2
8743      0,	// qsub_3
8744      0,	// ssub_0
8745      0,	// ssub_1
8746      0,	// ssub_2
8747      0,	// ssub_3
8748      0,	// ssub_4
8749      0,	// ssub_5
8750      0,	// ssub_6
8751      0,	// ssub_7
8752      0,	// ssub_8
8753      0,	// ssub_9
8754      0,	// ssub_10
8755      0,	// ssub_11
8756      0,	// ssub_12
8757      0,	// ssub_13
8758      0,	// dsub_7_then_ssub_0
8759      0,	// dsub_7_then_ssub_1
8760      0,	// ssub_0_ssub_1_ssub_4_ssub_5
8761      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8762      0,	// ssub_2_ssub_3_ssub_6_ssub_7
8763      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8764      0,	// ssub_2_ssub_3_ssub_4_ssub_5
8765      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8766      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8767      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8768      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8769      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8770      0,	// ssub_4_ssub_5_ssub_8_ssub_9
8771      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8772      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8773      0,	// ssub_6_ssub_7_dsub_5
8774      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8775      0,	// ssub_6_ssub_7_dsub_5_dsub_7
8776      0,	// ssub_6_ssub_7_ssub_8_ssub_9
8777      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8778      0,	// ssub_8_ssub_9_ssub_12_ssub_13
8779      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8780      0,	// dsub_5_dsub_7
8781      0,	// dsub_5_ssub_12_ssub_13_dsub_7
8782      0,	// dsub_5_ssub_12_ssub_13
8783      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8784    },
8785    {	// GPRPair_with_gsub_0_in_tGPR
8786      0,	// dsub_0
8787      0,	// dsub_1
8788      0,	// dsub_2
8789      0,	// dsub_3
8790      0,	// dsub_4
8791      0,	// dsub_5
8792      0,	// dsub_6
8793      0,	// dsub_7
8794      24,	// gsub_0 -> GPRPair_with_gsub_0_in_tGPR
8795      24,	// gsub_1 -> GPRPair_with_gsub_0_in_tGPR
8796      0,	// qqsub_0
8797      0,	// qqsub_1
8798      0,	// qsub_0
8799      0,	// qsub_1
8800      0,	// qsub_2
8801      0,	// qsub_3
8802      0,	// ssub_0
8803      0,	// ssub_1
8804      0,	// ssub_2
8805      0,	// ssub_3
8806      0,	// ssub_4
8807      0,	// ssub_5
8808      0,	// ssub_6
8809      0,	// ssub_7
8810      0,	// ssub_8
8811      0,	// ssub_9
8812      0,	// ssub_10
8813      0,	// ssub_11
8814      0,	// ssub_12
8815      0,	// ssub_13
8816      0,	// dsub_7_then_ssub_0
8817      0,	// dsub_7_then_ssub_1
8818      0,	// ssub_0_ssub_1_ssub_4_ssub_5
8819      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8820      0,	// ssub_2_ssub_3_ssub_6_ssub_7
8821      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8822      0,	// ssub_2_ssub_3_ssub_4_ssub_5
8823      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8824      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8825      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8826      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8827      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8828      0,	// ssub_4_ssub_5_ssub_8_ssub_9
8829      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8830      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8831      0,	// ssub_6_ssub_7_dsub_5
8832      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8833      0,	// ssub_6_ssub_7_dsub_5_dsub_7
8834      0,	// ssub_6_ssub_7_ssub_8_ssub_9
8835      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8836      0,	// ssub_8_ssub_9_ssub_12_ssub_13
8837      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8838      0,	// dsub_5_dsub_7
8839      0,	// dsub_5_ssub_12_ssub_13_dsub_7
8840      0,	// dsub_5_ssub_12_ssub_13
8841      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8842    },
8843    {	// GPRPair_with_gsub_0_in_hGPR
8844      0,	// dsub_0
8845      0,	// dsub_1
8846      0,	// dsub_2
8847      0,	// dsub_3
8848      0,	// dsub_4
8849      0,	// dsub_5
8850      0,	// dsub_6
8851      0,	// dsub_7
8852      25,	// gsub_0 -> GPRPair_with_gsub_0_in_hGPR
8853      25,	// gsub_1 -> GPRPair_with_gsub_0_in_hGPR
8854      0,	// qqsub_0
8855      0,	// qqsub_1
8856      0,	// qsub_0
8857      0,	// qsub_1
8858      0,	// qsub_2
8859      0,	// qsub_3
8860      0,	// ssub_0
8861      0,	// ssub_1
8862      0,	// ssub_2
8863      0,	// ssub_3
8864      0,	// ssub_4
8865      0,	// ssub_5
8866      0,	// ssub_6
8867      0,	// ssub_7
8868      0,	// ssub_8
8869      0,	// ssub_9
8870      0,	// ssub_10
8871      0,	// ssub_11
8872      0,	// ssub_12
8873      0,	// ssub_13
8874      0,	// dsub_7_then_ssub_0
8875      0,	// dsub_7_then_ssub_1
8876      0,	// ssub_0_ssub_1_ssub_4_ssub_5
8877      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8878      0,	// ssub_2_ssub_3_ssub_6_ssub_7
8879      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8880      0,	// ssub_2_ssub_3_ssub_4_ssub_5
8881      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8882      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8883      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8884      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8885      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8886      0,	// ssub_4_ssub_5_ssub_8_ssub_9
8887      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8888      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8889      0,	// ssub_6_ssub_7_dsub_5
8890      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8891      0,	// ssub_6_ssub_7_dsub_5_dsub_7
8892      0,	// ssub_6_ssub_7_ssub_8_ssub_9
8893      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8894      0,	// ssub_8_ssub_9_ssub_12_ssub_13
8895      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8896      0,	// dsub_5_dsub_7
8897      0,	// dsub_5_ssub_12_ssub_13_dsub_7
8898      0,	// dsub_5_ssub_12_ssub_13
8899      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8900    },
8901    {	// GPRPair_with_gsub_0_in_tcGPR
8902      0,	// dsub_0
8903      0,	// dsub_1
8904      0,	// dsub_2
8905      0,	// dsub_3
8906      0,	// dsub_4
8907      0,	// dsub_5
8908      0,	// dsub_6
8909      0,	// dsub_7
8910      26,	// gsub_0 -> GPRPair_with_gsub_0_in_tcGPR
8911      26,	// gsub_1 -> GPRPair_with_gsub_0_in_tcGPR
8912      0,	// qqsub_0
8913      0,	// qqsub_1
8914      0,	// qsub_0
8915      0,	// qsub_1
8916      0,	// qsub_2
8917      0,	// qsub_3
8918      0,	// ssub_0
8919      0,	// ssub_1
8920      0,	// ssub_2
8921      0,	// ssub_3
8922      0,	// ssub_4
8923      0,	// ssub_5
8924      0,	// ssub_6
8925      0,	// ssub_7
8926      0,	// ssub_8
8927      0,	// ssub_9
8928      0,	// ssub_10
8929      0,	// ssub_11
8930      0,	// ssub_12
8931      0,	// ssub_13
8932      0,	// dsub_7_then_ssub_0
8933      0,	// dsub_7_then_ssub_1
8934      0,	// ssub_0_ssub_1_ssub_4_ssub_5
8935      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8936      0,	// ssub_2_ssub_3_ssub_6_ssub_7
8937      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8938      0,	// ssub_2_ssub_3_ssub_4_ssub_5
8939      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8940      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8941      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
8942      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
8943      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8944      0,	// ssub_4_ssub_5_ssub_8_ssub_9
8945      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
8946      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8947      0,	// ssub_6_ssub_7_dsub_5
8948      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
8949      0,	// ssub_6_ssub_7_dsub_5_dsub_7
8950      0,	// ssub_6_ssub_7_ssub_8_ssub_9
8951      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8952      0,	// ssub_8_ssub_9_ssub_12_ssub_13
8953      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
8954      0,	// dsub_5_dsub_7
8955      0,	// dsub_5_ssub_12_ssub_13_dsub_7
8956      0,	// dsub_5_ssub_12_ssub_13
8957      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
8958    },
8959    {	// GPRPair_with_gsub_1_in_hGPR_and_rGPR
8960      0,	// dsub_0
8961      0,	// dsub_1
8962      0,	// dsub_2
8963      0,	// dsub_3
8964      0,	// dsub_4
8965      0,	// dsub_5
8966      0,	// dsub_6
8967      0,	// dsub_7
8968      27,	// gsub_0 -> GPRPair_with_gsub_1_in_hGPR_and_rGPR
8969      27,	// gsub_1 -> GPRPair_with_gsub_1_in_hGPR_and_rGPR
8970      0,	// qqsub_0
8971      0,	// qqsub_1
8972      0,	// qsub_0
8973      0,	// qsub_1
8974      0,	// qsub_2
8975      0,	// qsub_3
8976      0,	// ssub_0
8977      0,	// ssub_1
8978      0,	// ssub_2
8979      0,	// ssub_3
8980      0,	// ssub_4
8981      0,	// ssub_5
8982      0,	// ssub_6
8983      0,	// ssub_7
8984      0,	// ssub_8
8985      0,	// ssub_9
8986      0,	// ssub_10
8987      0,	// ssub_11
8988      0,	// ssub_12
8989      0,	// ssub_13
8990      0,	// dsub_7_then_ssub_0
8991      0,	// dsub_7_then_ssub_1
8992      0,	// ssub_0_ssub_1_ssub_4_ssub_5
8993      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
8994      0,	// ssub_2_ssub_3_ssub_6_ssub_7
8995      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
8996      0,	// ssub_2_ssub_3_ssub_4_ssub_5
8997      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
8998      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
8999      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9000      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9001      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9002      0,	// ssub_4_ssub_5_ssub_8_ssub_9
9003      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9004      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9005      0,	// ssub_6_ssub_7_dsub_5
9006      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9007      0,	// ssub_6_ssub_7_dsub_5_dsub_7
9008      0,	// ssub_6_ssub_7_ssub_8_ssub_9
9009      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9010      0,	// ssub_8_ssub_9_ssub_12_ssub_13
9011      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9012      0,	// dsub_5_dsub_7
9013      0,	// dsub_5_ssub_12_ssub_13_dsub_7
9014      0,	// dsub_5_ssub_12_ssub_13
9015      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9016    },
9017    {	// GPRPair_with_gsub_1_in_tcGPR
9018      0,	// dsub_0
9019      0,	// dsub_1
9020      0,	// dsub_2
9021      0,	// dsub_3
9022      0,	// dsub_4
9023      0,	// dsub_5
9024      0,	// dsub_6
9025      0,	// dsub_7
9026      28,	// gsub_0 -> GPRPair_with_gsub_1_in_tcGPR
9027      28,	// gsub_1 -> GPRPair_with_gsub_1_in_tcGPR
9028      0,	// qqsub_0
9029      0,	// qqsub_1
9030      0,	// qsub_0
9031      0,	// qsub_1
9032      0,	// qsub_2
9033      0,	// qsub_3
9034      0,	// ssub_0
9035      0,	// ssub_1
9036      0,	// ssub_2
9037      0,	// ssub_3
9038      0,	// ssub_4
9039      0,	// ssub_5
9040      0,	// ssub_6
9041      0,	// ssub_7
9042      0,	// ssub_8
9043      0,	// ssub_9
9044      0,	// ssub_10
9045      0,	// ssub_11
9046      0,	// ssub_12
9047      0,	// ssub_13
9048      0,	// dsub_7_then_ssub_0
9049      0,	// dsub_7_then_ssub_1
9050      0,	// ssub_0_ssub_1_ssub_4_ssub_5
9051      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9052      0,	// ssub_2_ssub_3_ssub_6_ssub_7
9053      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9054      0,	// ssub_2_ssub_3_ssub_4_ssub_5
9055      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9056      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9057      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9058      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9059      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9060      0,	// ssub_4_ssub_5_ssub_8_ssub_9
9061      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9062      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9063      0,	// ssub_6_ssub_7_dsub_5
9064      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9065      0,	// ssub_6_ssub_7_dsub_5_dsub_7
9066      0,	// ssub_6_ssub_7_ssub_8_ssub_9
9067      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9068      0,	// ssub_8_ssub_9_ssub_12_ssub_13
9069      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9070      0,	// dsub_5_dsub_7
9071      0,	// dsub_5_ssub_12_ssub_13_dsub_7
9072      0,	// dsub_5_ssub_12_ssub_13
9073      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9074    },
9075    {	// GPRPair_with_gsub_1_in_GPRsp
9076      0,	// dsub_0
9077      0,	// dsub_1
9078      0,	// dsub_2
9079      0,	// dsub_3
9080      0,	// dsub_4
9081      0,	// dsub_5
9082      0,	// dsub_6
9083      0,	// dsub_7
9084      29,	// gsub_0 -> GPRPair_with_gsub_1_in_GPRsp
9085      29,	// gsub_1 -> GPRPair_with_gsub_1_in_GPRsp
9086      0,	// qqsub_0
9087      0,	// qqsub_1
9088      0,	// qsub_0
9089      0,	// qsub_1
9090      0,	// qsub_2
9091      0,	// qsub_3
9092      0,	// ssub_0
9093      0,	// ssub_1
9094      0,	// ssub_2
9095      0,	// ssub_3
9096      0,	// ssub_4
9097      0,	// ssub_5
9098      0,	// ssub_6
9099      0,	// ssub_7
9100      0,	// ssub_8
9101      0,	// ssub_9
9102      0,	// ssub_10
9103      0,	// ssub_11
9104      0,	// ssub_12
9105      0,	// ssub_13
9106      0,	// dsub_7_then_ssub_0
9107      0,	// dsub_7_then_ssub_1
9108      0,	// ssub_0_ssub_1_ssub_4_ssub_5
9109      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9110      0,	// ssub_2_ssub_3_ssub_6_ssub_7
9111      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9112      0,	// ssub_2_ssub_3_ssub_4_ssub_5
9113      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9114      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9115      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9116      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9117      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9118      0,	// ssub_4_ssub_5_ssub_8_ssub_9
9119      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9120      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9121      0,	// ssub_6_ssub_7_dsub_5
9122      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9123      0,	// ssub_6_ssub_7_dsub_5_dsub_7
9124      0,	// ssub_6_ssub_7_ssub_8_ssub_9
9125      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9126      0,	// ssub_8_ssub_9_ssub_12_ssub_13
9127      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9128      0,	// dsub_5_dsub_7
9129      0,	// dsub_5_ssub_12_ssub_13_dsub_7
9130      0,	// dsub_5_ssub_12_ssub_13
9131      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9132    },
9133    {	// DPairSpc
9134      30,	// dsub_0 -> DPairSpc
9135      0,	// dsub_1
9136      30,	// dsub_2 -> DPairSpc
9137      0,	// dsub_3
9138      0,	// dsub_4
9139      0,	// dsub_5
9140      0,	// dsub_6
9141      0,	// dsub_7
9142      0,	// gsub_0
9143      0,	// gsub_1
9144      0,	// qqsub_0
9145      0,	// qqsub_1
9146      0,	// qsub_0
9147      0,	// qsub_1
9148      0,	// qsub_2
9149      0,	// qsub_3
9150      31,	// ssub_0 -> DPairSpc_with_ssub_0
9151      31,	// ssub_1 -> DPairSpc_with_ssub_0
9152      0,	// ssub_2
9153      0,	// ssub_3
9154      32,	// ssub_4 -> DPairSpc_with_ssub_4
9155      32,	// ssub_5 -> DPairSpc_with_ssub_4
9156      0,	// ssub_6
9157      0,	// ssub_7
9158      0,	// ssub_8
9159      0,	// ssub_9
9160      0,	// ssub_10
9161      0,	// ssub_11
9162      0,	// ssub_12
9163      0,	// ssub_13
9164      0,	// dsub_7_then_ssub_0
9165      0,	// dsub_7_then_ssub_1
9166      0,	// ssub_0_ssub_1_ssub_4_ssub_5
9167      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9168      0,	// ssub_2_ssub_3_ssub_6_ssub_7
9169      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9170      0,	// ssub_2_ssub_3_ssub_4_ssub_5
9171      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9172      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9173      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9174      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9175      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9176      0,	// ssub_4_ssub_5_ssub_8_ssub_9
9177      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9178      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9179      0,	// ssub_6_ssub_7_dsub_5
9180      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9181      0,	// ssub_6_ssub_7_dsub_5_dsub_7
9182      0,	// ssub_6_ssub_7_ssub_8_ssub_9
9183      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9184      0,	// ssub_8_ssub_9_ssub_12_ssub_13
9185      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9186      0,	// dsub_5_dsub_7
9187      0,	// dsub_5_ssub_12_ssub_13_dsub_7
9188      0,	// dsub_5_ssub_12_ssub_13
9189      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9190    },
9191    {	// DPairSpc_with_ssub_0
9192      31,	// dsub_0 -> DPairSpc_with_ssub_0
9193      0,	// dsub_1
9194      31,	// dsub_2 -> DPairSpc_with_ssub_0
9195      0,	// dsub_3
9196      0,	// dsub_4
9197      0,	// dsub_5
9198      0,	// dsub_6
9199      0,	// dsub_7
9200      0,	// gsub_0
9201      0,	// gsub_1
9202      0,	// qqsub_0
9203      0,	// qqsub_1
9204      0,	// qsub_0
9205      0,	// qsub_1
9206      0,	// qsub_2
9207      0,	// qsub_3
9208      31,	// ssub_0 -> DPairSpc_with_ssub_0
9209      31,	// ssub_1 -> DPairSpc_with_ssub_0
9210      0,	// ssub_2
9211      0,	// ssub_3
9212      32,	// ssub_4 -> DPairSpc_with_ssub_4
9213      32,	// ssub_5 -> DPairSpc_with_ssub_4
9214      0,	// ssub_6
9215      0,	// ssub_7
9216      0,	// ssub_8
9217      0,	// ssub_9
9218      0,	// ssub_10
9219      0,	// ssub_11
9220      0,	// ssub_12
9221      0,	// ssub_13
9222      0,	// dsub_7_then_ssub_0
9223      0,	// dsub_7_then_ssub_1
9224      0,	// ssub_0_ssub_1_ssub_4_ssub_5
9225      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9226      0,	// ssub_2_ssub_3_ssub_6_ssub_7
9227      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9228      0,	// ssub_2_ssub_3_ssub_4_ssub_5
9229      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9230      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9231      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9232      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9233      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9234      0,	// ssub_4_ssub_5_ssub_8_ssub_9
9235      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9236      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9237      0,	// ssub_6_ssub_7_dsub_5
9238      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9239      0,	// ssub_6_ssub_7_dsub_5_dsub_7
9240      0,	// ssub_6_ssub_7_ssub_8_ssub_9
9241      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9242      0,	// ssub_8_ssub_9_ssub_12_ssub_13
9243      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9244      0,	// dsub_5_dsub_7
9245      0,	// dsub_5_ssub_12_ssub_13_dsub_7
9246      0,	// dsub_5_ssub_12_ssub_13
9247      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9248    },
9249    {	// DPairSpc_with_ssub_4
9250      32,	// dsub_0 -> DPairSpc_with_ssub_4
9251      0,	// dsub_1
9252      32,	// dsub_2 -> DPairSpc_with_ssub_4
9253      0,	// dsub_3
9254      0,	// dsub_4
9255      0,	// dsub_5
9256      0,	// dsub_6
9257      0,	// dsub_7
9258      0,	// gsub_0
9259      0,	// gsub_1
9260      0,	// qqsub_0
9261      0,	// qqsub_1
9262      0,	// qsub_0
9263      0,	// qsub_1
9264      0,	// qsub_2
9265      0,	// qsub_3
9266      32,	// ssub_0 -> DPairSpc_with_ssub_4
9267      32,	// ssub_1 -> DPairSpc_with_ssub_4
9268      0,	// ssub_2
9269      0,	// ssub_3
9270      32,	// ssub_4 -> DPairSpc_with_ssub_4
9271      32,	// ssub_5 -> DPairSpc_with_ssub_4
9272      0,	// ssub_6
9273      0,	// ssub_7
9274      0,	// ssub_8
9275      0,	// ssub_9
9276      0,	// ssub_10
9277      0,	// ssub_11
9278      0,	// ssub_12
9279      0,	// ssub_13
9280      0,	// dsub_7_then_ssub_0
9281      0,	// dsub_7_then_ssub_1
9282      0,	// ssub_0_ssub_1_ssub_4_ssub_5
9283      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9284      0,	// ssub_2_ssub_3_ssub_6_ssub_7
9285      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9286      0,	// ssub_2_ssub_3_ssub_4_ssub_5
9287      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9288      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9289      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9290      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9291      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9292      0,	// ssub_4_ssub_5_ssub_8_ssub_9
9293      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9294      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9295      0,	// ssub_6_ssub_7_dsub_5
9296      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9297      0,	// ssub_6_ssub_7_dsub_5_dsub_7
9298      0,	// ssub_6_ssub_7_ssub_8_ssub_9
9299      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9300      0,	// ssub_8_ssub_9_ssub_12_ssub_13
9301      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9302      0,	// dsub_5_dsub_7
9303      0,	// dsub_5_ssub_12_ssub_13_dsub_7
9304      0,	// dsub_5_ssub_12_ssub_13
9305      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9306    },
9307    {	// DPairSpc_with_dsub_0_in_DPR_8
9308      33,	// dsub_0 -> DPairSpc_with_dsub_0_in_DPR_8
9309      0,	// dsub_1
9310      33,	// dsub_2 -> DPairSpc_with_dsub_0_in_DPR_8
9311      0,	// dsub_3
9312      0,	// dsub_4
9313      0,	// dsub_5
9314      0,	// dsub_6
9315      0,	// dsub_7
9316      0,	// gsub_0
9317      0,	// gsub_1
9318      0,	// qqsub_0
9319      0,	// qqsub_1
9320      0,	// qsub_0
9321      0,	// qsub_1
9322      0,	// qsub_2
9323      0,	// qsub_3
9324      33,	// ssub_0 -> DPairSpc_with_dsub_0_in_DPR_8
9325      33,	// ssub_1 -> DPairSpc_with_dsub_0_in_DPR_8
9326      0,	// ssub_2
9327      0,	// ssub_3
9328      33,	// ssub_4 -> DPairSpc_with_dsub_0_in_DPR_8
9329      33,	// ssub_5 -> DPairSpc_with_dsub_0_in_DPR_8
9330      0,	// ssub_6
9331      0,	// ssub_7
9332      0,	// ssub_8
9333      0,	// ssub_9
9334      0,	// ssub_10
9335      0,	// ssub_11
9336      0,	// ssub_12
9337      0,	// ssub_13
9338      0,	// dsub_7_then_ssub_0
9339      0,	// dsub_7_then_ssub_1
9340      0,	// ssub_0_ssub_1_ssub_4_ssub_5
9341      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9342      0,	// ssub_2_ssub_3_ssub_6_ssub_7
9343      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9344      0,	// ssub_2_ssub_3_ssub_4_ssub_5
9345      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9346      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9347      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9348      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9349      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9350      0,	// ssub_4_ssub_5_ssub_8_ssub_9
9351      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9352      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9353      0,	// ssub_6_ssub_7_dsub_5
9354      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9355      0,	// ssub_6_ssub_7_dsub_5_dsub_7
9356      0,	// ssub_6_ssub_7_ssub_8_ssub_9
9357      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9358      0,	// ssub_8_ssub_9_ssub_12_ssub_13
9359      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9360      0,	// dsub_5_dsub_7
9361      0,	// dsub_5_ssub_12_ssub_13_dsub_7
9362      0,	// dsub_5_ssub_12_ssub_13
9363      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9364    },
9365    {	// DPairSpc_with_dsub_2_in_DPR_8
9366      34,	// dsub_0 -> DPairSpc_with_dsub_2_in_DPR_8
9367      0,	// dsub_1
9368      34,	// dsub_2 -> DPairSpc_with_dsub_2_in_DPR_8
9369      0,	// dsub_3
9370      0,	// dsub_4
9371      0,	// dsub_5
9372      0,	// dsub_6
9373      0,	// dsub_7
9374      0,	// gsub_0
9375      0,	// gsub_1
9376      0,	// qqsub_0
9377      0,	// qqsub_1
9378      0,	// qsub_0
9379      0,	// qsub_1
9380      0,	// qsub_2
9381      0,	// qsub_3
9382      34,	// ssub_0 -> DPairSpc_with_dsub_2_in_DPR_8
9383      34,	// ssub_1 -> DPairSpc_with_dsub_2_in_DPR_8
9384      0,	// ssub_2
9385      0,	// ssub_3
9386      34,	// ssub_4 -> DPairSpc_with_dsub_2_in_DPR_8
9387      34,	// ssub_5 -> DPairSpc_with_dsub_2_in_DPR_8
9388      0,	// ssub_6
9389      0,	// ssub_7
9390      0,	// ssub_8
9391      0,	// ssub_9
9392      0,	// ssub_10
9393      0,	// ssub_11
9394      0,	// ssub_12
9395      0,	// ssub_13
9396      0,	// dsub_7_then_ssub_0
9397      0,	// dsub_7_then_ssub_1
9398      0,	// ssub_0_ssub_1_ssub_4_ssub_5
9399      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9400      0,	// ssub_2_ssub_3_ssub_6_ssub_7
9401      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9402      0,	// ssub_2_ssub_3_ssub_4_ssub_5
9403      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9404      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9405      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9406      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9407      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9408      0,	// ssub_4_ssub_5_ssub_8_ssub_9
9409      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9410      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9411      0,	// ssub_6_ssub_7_dsub_5
9412      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9413      0,	// ssub_6_ssub_7_dsub_5_dsub_7
9414      0,	// ssub_6_ssub_7_ssub_8_ssub_9
9415      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9416      0,	// ssub_8_ssub_9_ssub_12_ssub_13
9417      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9418      0,	// dsub_5_dsub_7
9419      0,	// dsub_5_ssub_12_ssub_13_dsub_7
9420      0,	// dsub_5_ssub_12_ssub_13
9421      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9422    },
9423    {	// DPair
9424      35,	// dsub_0 -> DPair
9425      35,	// dsub_1 -> DPair
9426      0,	// dsub_2
9427      0,	// dsub_3
9428      0,	// dsub_4
9429      0,	// dsub_5
9430      0,	// dsub_6
9431      0,	// dsub_7
9432      0,	// gsub_0
9433      0,	// gsub_1
9434      0,	// qqsub_0
9435      0,	// qqsub_1
9436      0,	// qsub_0
9437      0,	// qsub_1
9438      0,	// qsub_2
9439      0,	// qsub_3
9440      36,	// ssub_0 -> DPair_with_ssub_0
9441      36,	// ssub_1 -> DPair_with_ssub_0
9442      38,	// ssub_2 -> DPair_with_ssub_2
9443      38,	// ssub_3 -> DPair_with_ssub_2
9444      0,	// ssub_4
9445      0,	// ssub_5
9446      0,	// ssub_6
9447      0,	// ssub_7
9448      0,	// ssub_8
9449      0,	// ssub_9
9450      0,	// ssub_10
9451      0,	// ssub_11
9452      0,	// ssub_12
9453      0,	// ssub_13
9454      0,	// dsub_7_then_ssub_0
9455      0,	// dsub_7_then_ssub_1
9456      0,	// ssub_0_ssub_1_ssub_4_ssub_5
9457      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9458      0,	// ssub_2_ssub_3_ssub_6_ssub_7
9459      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9460      0,	// ssub_2_ssub_3_ssub_4_ssub_5
9461      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9462      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9463      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9464      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9465      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9466      0,	// ssub_4_ssub_5_ssub_8_ssub_9
9467      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9468      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9469      0,	// ssub_6_ssub_7_dsub_5
9470      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9471      0,	// ssub_6_ssub_7_dsub_5_dsub_7
9472      0,	// ssub_6_ssub_7_ssub_8_ssub_9
9473      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9474      0,	// ssub_8_ssub_9_ssub_12_ssub_13
9475      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9476      0,	// dsub_5_dsub_7
9477      0,	// dsub_5_ssub_12_ssub_13_dsub_7
9478      0,	// dsub_5_ssub_12_ssub_13
9479      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9480    },
9481    {	// DPair_with_ssub_0
9482      36,	// dsub_0 -> DPair_with_ssub_0
9483      36,	// dsub_1 -> DPair_with_ssub_0
9484      0,	// dsub_2
9485      0,	// dsub_3
9486      0,	// dsub_4
9487      0,	// dsub_5
9488      0,	// dsub_6
9489      0,	// dsub_7
9490      0,	// gsub_0
9491      0,	// gsub_1
9492      0,	// qqsub_0
9493      0,	// qqsub_1
9494      0,	// qsub_0
9495      0,	// qsub_1
9496      0,	// qsub_2
9497      0,	// qsub_3
9498      36,	// ssub_0 -> DPair_with_ssub_0
9499      36,	// ssub_1 -> DPair_with_ssub_0
9500      38,	// ssub_2 -> DPair_with_ssub_2
9501      38,	// ssub_3 -> DPair_with_ssub_2
9502      0,	// ssub_4
9503      0,	// ssub_5
9504      0,	// ssub_6
9505      0,	// ssub_7
9506      0,	// ssub_8
9507      0,	// ssub_9
9508      0,	// ssub_10
9509      0,	// ssub_11
9510      0,	// ssub_12
9511      0,	// ssub_13
9512      0,	// dsub_7_then_ssub_0
9513      0,	// dsub_7_then_ssub_1
9514      0,	// ssub_0_ssub_1_ssub_4_ssub_5
9515      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9516      0,	// ssub_2_ssub_3_ssub_6_ssub_7
9517      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9518      0,	// ssub_2_ssub_3_ssub_4_ssub_5
9519      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9520      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9521      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9522      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9523      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9524      0,	// ssub_4_ssub_5_ssub_8_ssub_9
9525      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9526      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9527      0,	// ssub_6_ssub_7_dsub_5
9528      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9529      0,	// ssub_6_ssub_7_dsub_5_dsub_7
9530      0,	// ssub_6_ssub_7_ssub_8_ssub_9
9531      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9532      0,	// ssub_8_ssub_9_ssub_12_ssub_13
9533      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9534      0,	// dsub_5_dsub_7
9535      0,	// dsub_5_ssub_12_ssub_13_dsub_7
9536      0,	// dsub_5_ssub_12_ssub_13
9537      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9538    },
9539    {	// QPR
9540      37,	// dsub_0 -> QPR
9541      37,	// dsub_1 -> QPR
9542      0,	// dsub_2
9543      0,	// dsub_3
9544      0,	// dsub_4
9545      0,	// dsub_5
9546      0,	// dsub_6
9547      0,	// dsub_7
9548      0,	// gsub_0
9549      0,	// gsub_1
9550      0,	// qqsub_0
9551      0,	// qqsub_1
9552      0,	// qsub_0
9553      0,	// qsub_1
9554      0,	// qsub_2
9555      0,	// qsub_3
9556      40,	// ssub_0 -> QPR_VFP2
9557      40,	// ssub_1 -> QPR_VFP2
9558      40,	// ssub_2 -> QPR_VFP2
9559      40,	// ssub_3 -> QPR_VFP2
9560      0,	// ssub_4
9561      0,	// ssub_5
9562      0,	// ssub_6
9563      0,	// ssub_7
9564      0,	// ssub_8
9565      0,	// ssub_9
9566      0,	// ssub_10
9567      0,	// ssub_11
9568      0,	// ssub_12
9569      0,	// ssub_13
9570      0,	// dsub_7_then_ssub_0
9571      0,	// dsub_7_then_ssub_1
9572      0,	// ssub_0_ssub_1_ssub_4_ssub_5
9573      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9574      0,	// ssub_2_ssub_3_ssub_6_ssub_7
9575      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9576      0,	// ssub_2_ssub_3_ssub_4_ssub_5
9577      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9578      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9579      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9580      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9581      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9582      0,	// ssub_4_ssub_5_ssub_8_ssub_9
9583      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9584      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9585      0,	// ssub_6_ssub_7_dsub_5
9586      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9587      0,	// ssub_6_ssub_7_dsub_5_dsub_7
9588      0,	// ssub_6_ssub_7_ssub_8_ssub_9
9589      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9590      0,	// ssub_8_ssub_9_ssub_12_ssub_13
9591      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9592      0,	// dsub_5_dsub_7
9593      0,	// dsub_5_ssub_12_ssub_13_dsub_7
9594      0,	// dsub_5_ssub_12_ssub_13
9595      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9596    },
9597    {	// DPair_with_ssub_2
9598      38,	// dsub_0 -> DPair_with_ssub_2
9599      38,	// dsub_1 -> DPair_with_ssub_2
9600      0,	// dsub_2
9601      0,	// dsub_3
9602      0,	// dsub_4
9603      0,	// dsub_5
9604      0,	// dsub_6
9605      0,	// dsub_7
9606      0,	// gsub_0
9607      0,	// gsub_1
9608      0,	// qqsub_0
9609      0,	// qqsub_1
9610      0,	// qsub_0
9611      0,	// qsub_1
9612      0,	// qsub_2
9613      0,	// qsub_3
9614      38,	// ssub_0 -> DPair_with_ssub_2
9615      38,	// ssub_1 -> DPair_with_ssub_2
9616      38,	// ssub_2 -> DPair_with_ssub_2
9617      38,	// ssub_3 -> DPair_with_ssub_2
9618      0,	// ssub_4
9619      0,	// ssub_5
9620      0,	// ssub_6
9621      0,	// ssub_7
9622      0,	// ssub_8
9623      0,	// ssub_9
9624      0,	// ssub_10
9625      0,	// ssub_11
9626      0,	// ssub_12
9627      0,	// ssub_13
9628      0,	// dsub_7_then_ssub_0
9629      0,	// dsub_7_then_ssub_1
9630      0,	// ssub_0_ssub_1_ssub_4_ssub_5
9631      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9632      0,	// ssub_2_ssub_3_ssub_6_ssub_7
9633      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9634      0,	// ssub_2_ssub_3_ssub_4_ssub_5
9635      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9636      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9637      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9638      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9639      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9640      0,	// ssub_4_ssub_5_ssub_8_ssub_9
9641      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9642      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9643      0,	// ssub_6_ssub_7_dsub_5
9644      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9645      0,	// ssub_6_ssub_7_dsub_5_dsub_7
9646      0,	// ssub_6_ssub_7_ssub_8_ssub_9
9647      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9648      0,	// ssub_8_ssub_9_ssub_12_ssub_13
9649      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9650      0,	// dsub_5_dsub_7
9651      0,	// dsub_5_ssub_12_ssub_13_dsub_7
9652      0,	// dsub_5_ssub_12_ssub_13
9653      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9654    },
9655    {	// DPair_with_dsub_0_in_DPR_8
9656      39,	// dsub_0 -> DPair_with_dsub_0_in_DPR_8
9657      39,	// dsub_1 -> DPair_with_dsub_0_in_DPR_8
9658      0,	// dsub_2
9659      0,	// dsub_3
9660      0,	// dsub_4
9661      0,	// dsub_5
9662      0,	// dsub_6
9663      0,	// dsub_7
9664      0,	// gsub_0
9665      0,	// gsub_1
9666      0,	// qqsub_0
9667      0,	// qqsub_1
9668      0,	// qsub_0
9669      0,	// qsub_1
9670      0,	// qsub_2
9671      0,	// qsub_3
9672      39,	// ssub_0 -> DPair_with_dsub_0_in_DPR_8
9673      39,	// ssub_1 -> DPair_with_dsub_0_in_DPR_8
9674      39,	// ssub_2 -> DPair_with_dsub_0_in_DPR_8
9675      39,	// ssub_3 -> DPair_with_dsub_0_in_DPR_8
9676      0,	// ssub_4
9677      0,	// ssub_5
9678      0,	// ssub_6
9679      0,	// ssub_7
9680      0,	// ssub_8
9681      0,	// ssub_9
9682      0,	// ssub_10
9683      0,	// ssub_11
9684      0,	// ssub_12
9685      0,	// ssub_13
9686      0,	// dsub_7_then_ssub_0
9687      0,	// dsub_7_then_ssub_1
9688      0,	// ssub_0_ssub_1_ssub_4_ssub_5
9689      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9690      0,	// ssub_2_ssub_3_ssub_6_ssub_7
9691      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9692      0,	// ssub_2_ssub_3_ssub_4_ssub_5
9693      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9694      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9695      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9696      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9697      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9698      0,	// ssub_4_ssub_5_ssub_8_ssub_9
9699      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9700      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9701      0,	// ssub_6_ssub_7_dsub_5
9702      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9703      0,	// ssub_6_ssub_7_dsub_5_dsub_7
9704      0,	// ssub_6_ssub_7_ssub_8_ssub_9
9705      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9706      0,	// ssub_8_ssub_9_ssub_12_ssub_13
9707      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9708      0,	// dsub_5_dsub_7
9709      0,	// dsub_5_ssub_12_ssub_13_dsub_7
9710      0,	// dsub_5_ssub_12_ssub_13
9711      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9712    },
9713    {	// QPR_VFP2
9714      40,	// dsub_0 -> QPR_VFP2
9715      40,	// dsub_1 -> QPR_VFP2
9716      0,	// dsub_2
9717      0,	// dsub_3
9718      0,	// dsub_4
9719      0,	// dsub_5
9720      0,	// dsub_6
9721      0,	// dsub_7
9722      0,	// gsub_0
9723      0,	// gsub_1
9724      0,	// qqsub_0
9725      0,	// qqsub_1
9726      0,	// qsub_0
9727      0,	// qsub_1
9728      0,	// qsub_2
9729      0,	// qsub_3
9730      40,	// ssub_0 -> QPR_VFP2
9731      40,	// ssub_1 -> QPR_VFP2
9732      40,	// ssub_2 -> QPR_VFP2
9733      40,	// ssub_3 -> QPR_VFP2
9734      0,	// ssub_4
9735      0,	// ssub_5
9736      0,	// ssub_6
9737      0,	// ssub_7
9738      0,	// ssub_8
9739      0,	// ssub_9
9740      0,	// ssub_10
9741      0,	// ssub_11
9742      0,	// ssub_12
9743      0,	// ssub_13
9744      0,	// dsub_7_then_ssub_0
9745      0,	// dsub_7_then_ssub_1
9746      0,	// ssub_0_ssub_1_ssub_4_ssub_5
9747      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9748      0,	// ssub_2_ssub_3_ssub_6_ssub_7
9749      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9750      0,	// ssub_2_ssub_3_ssub_4_ssub_5
9751      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9752      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9753      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9754      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9755      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9756      0,	// ssub_4_ssub_5_ssub_8_ssub_9
9757      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9758      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9759      0,	// ssub_6_ssub_7_dsub_5
9760      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9761      0,	// ssub_6_ssub_7_dsub_5_dsub_7
9762      0,	// ssub_6_ssub_7_ssub_8_ssub_9
9763      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9764      0,	// ssub_8_ssub_9_ssub_12_ssub_13
9765      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9766      0,	// dsub_5_dsub_7
9767      0,	// dsub_5_ssub_12_ssub_13_dsub_7
9768      0,	// dsub_5_ssub_12_ssub_13
9769      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9770    },
9771    {	// DPair_with_dsub_1_in_DPR_8
9772      41,	// dsub_0 -> DPair_with_dsub_1_in_DPR_8
9773      41,	// dsub_1 -> DPair_with_dsub_1_in_DPR_8
9774      0,	// dsub_2
9775      0,	// dsub_3
9776      0,	// dsub_4
9777      0,	// dsub_5
9778      0,	// dsub_6
9779      0,	// dsub_7
9780      0,	// gsub_0
9781      0,	// gsub_1
9782      0,	// qqsub_0
9783      0,	// qqsub_1
9784      0,	// qsub_0
9785      0,	// qsub_1
9786      0,	// qsub_2
9787      0,	// qsub_3
9788      41,	// ssub_0 -> DPair_with_dsub_1_in_DPR_8
9789      41,	// ssub_1 -> DPair_with_dsub_1_in_DPR_8
9790      41,	// ssub_2 -> DPair_with_dsub_1_in_DPR_8
9791      41,	// ssub_3 -> DPair_with_dsub_1_in_DPR_8
9792      0,	// ssub_4
9793      0,	// ssub_5
9794      0,	// ssub_6
9795      0,	// ssub_7
9796      0,	// ssub_8
9797      0,	// ssub_9
9798      0,	// ssub_10
9799      0,	// ssub_11
9800      0,	// ssub_12
9801      0,	// ssub_13
9802      0,	// dsub_7_then_ssub_0
9803      0,	// dsub_7_then_ssub_1
9804      0,	// ssub_0_ssub_1_ssub_4_ssub_5
9805      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9806      0,	// ssub_2_ssub_3_ssub_6_ssub_7
9807      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9808      0,	// ssub_2_ssub_3_ssub_4_ssub_5
9809      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9810      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9811      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9812      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9813      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9814      0,	// ssub_4_ssub_5_ssub_8_ssub_9
9815      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9816      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9817      0,	// ssub_6_ssub_7_dsub_5
9818      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9819      0,	// ssub_6_ssub_7_dsub_5_dsub_7
9820      0,	// ssub_6_ssub_7_ssub_8_ssub_9
9821      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9822      0,	// ssub_8_ssub_9_ssub_12_ssub_13
9823      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9824      0,	// dsub_5_dsub_7
9825      0,	// dsub_5_ssub_12_ssub_13_dsub_7
9826      0,	// dsub_5_ssub_12_ssub_13
9827      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9828    },
9829    {	// QPR_8
9830      42,	// dsub_0 -> QPR_8
9831      42,	// dsub_1 -> QPR_8
9832      0,	// dsub_2
9833      0,	// dsub_3
9834      0,	// dsub_4
9835      0,	// dsub_5
9836      0,	// dsub_6
9837      0,	// dsub_7
9838      0,	// gsub_0
9839      0,	// gsub_1
9840      0,	// qqsub_0
9841      0,	// qqsub_1
9842      0,	// qsub_0
9843      0,	// qsub_1
9844      0,	// qsub_2
9845      0,	// qsub_3
9846      42,	// ssub_0 -> QPR_8
9847      42,	// ssub_1 -> QPR_8
9848      42,	// ssub_2 -> QPR_8
9849      42,	// ssub_3 -> QPR_8
9850      0,	// ssub_4
9851      0,	// ssub_5
9852      0,	// ssub_6
9853      0,	// ssub_7
9854      0,	// ssub_8
9855      0,	// ssub_9
9856      0,	// ssub_10
9857      0,	// ssub_11
9858      0,	// ssub_12
9859      0,	// ssub_13
9860      0,	// dsub_7_then_ssub_0
9861      0,	// dsub_7_then_ssub_1
9862      0,	// ssub_0_ssub_1_ssub_4_ssub_5
9863      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9864      0,	// ssub_2_ssub_3_ssub_6_ssub_7
9865      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9866      0,	// ssub_2_ssub_3_ssub_4_ssub_5
9867      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9868      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9869      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9870      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9871      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9872      0,	// ssub_4_ssub_5_ssub_8_ssub_9
9873      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9874      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9875      0,	// ssub_6_ssub_7_dsub_5
9876      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9877      0,	// ssub_6_ssub_7_dsub_5_dsub_7
9878      0,	// ssub_6_ssub_7_ssub_8_ssub_9
9879      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9880      0,	// ssub_8_ssub_9_ssub_12_ssub_13
9881      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9882      0,	// dsub_5_dsub_7
9883      0,	// dsub_5_ssub_12_ssub_13_dsub_7
9884      0,	// dsub_5_ssub_12_ssub_13
9885      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9886    },
9887    {	// DTriple
9888      43,	// dsub_0 -> DTriple
9889      43,	// dsub_1 -> DTriple
9890      43,	// dsub_2 -> DTriple
9891      0,	// dsub_3
9892      0,	// dsub_4
9893      0,	// dsub_5
9894      0,	// dsub_6
9895      0,	// dsub_7
9896      0,	// gsub_0
9897      0,	// gsub_1
9898      0,	// qqsub_0
9899      0,	// qqsub_1
9900      43,	// qsub_0 -> DTriple
9901      0,	// qsub_1
9902      0,	// qsub_2
9903      0,	// qsub_3
9904      46,	// ssub_0 -> DTriple_with_ssub_0
9905      46,	// ssub_1 -> DTriple_with_ssub_0
9906      48,	// ssub_2 -> DTriple_with_ssub_2
9907      48,	// ssub_3 -> DTriple_with_ssub_2
9908      51,	// ssub_4 -> DTriple_with_ssub_4
9909      51,	// ssub_5 -> DTriple_with_ssub_4
9910      0,	// ssub_6
9911      0,	// ssub_7
9912      0,	// ssub_8
9913      0,	// ssub_9
9914      0,	// ssub_10
9915      0,	// ssub_11
9916      0,	// ssub_12
9917      0,	// ssub_13
9918      0,	// dsub_7_then_ssub_0
9919      0,	// dsub_7_then_ssub_1
9920      43,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple
9921      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9922      0,	// ssub_2_ssub_3_ssub_6_ssub_7
9923      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9924      43,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple
9925      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9926      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9927      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9928      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9929      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9930      0,	// ssub_4_ssub_5_ssub_8_ssub_9
9931      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9932      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9933      0,	// ssub_6_ssub_7_dsub_5
9934      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9935      0,	// ssub_6_ssub_7_dsub_5_dsub_7
9936      0,	// ssub_6_ssub_7_ssub_8_ssub_9
9937      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9938      0,	// ssub_8_ssub_9_ssub_12_ssub_13
9939      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9940      0,	// dsub_5_dsub_7
9941      0,	// dsub_5_ssub_12_ssub_13_dsub_7
9942      0,	// dsub_5_ssub_12_ssub_13
9943      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
9944    },
9945    {	// DTripleSpc
9946      44,	// dsub_0 -> DTripleSpc
9947      0,	// dsub_1
9948      44,	// dsub_2 -> DTripleSpc
9949      0,	// dsub_3
9950      44,	// dsub_4 -> DTripleSpc
9951      0,	// dsub_5
9952      0,	// dsub_6
9953      0,	// dsub_7
9954      0,	// gsub_0
9955      0,	// gsub_1
9956      0,	// qqsub_0
9957      0,	// qqsub_1
9958      0,	// qsub_0
9959      0,	// qsub_1
9960      0,	// qsub_2
9961      0,	// qsub_3
9962      45,	// ssub_0 -> DTripleSpc_with_ssub_0
9963      45,	// ssub_1 -> DTripleSpc_with_ssub_0
9964      0,	// ssub_2
9965      0,	// ssub_3
9966      50,	// ssub_4 -> DTripleSpc_with_ssub_4
9967      50,	// ssub_5 -> DTripleSpc_with_ssub_4
9968      0,	// ssub_6
9969      0,	// ssub_7
9970      52,	// ssub_8 -> DTripleSpc_with_ssub_8
9971      52,	// ssub_9 -> DTripleSpc_with_ssub_8
9972      0,	// ssub_10
9973      0,	// ssub_11
9974      0,	// ssub_12
9975      0,	// ssub_13
9976      0,	// dsub_7_then_ssub_0
9977      0,	// dsub_7_then_ssub_1
9978      44,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc
9979      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
9980      0,	// ssub_2_ssub_3_ssub_6_ssub_7
9981      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
9982      0,	// ssub_2_ssub_3_ssub_4_ssub_5
9983      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
9984      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9985      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
9986      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
9987      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9988      44,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc
9989      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
9990      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
9991      0,	// ssub_6_ssub_7_dsub_5
9992      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
9993      0,	// ssub_6_ssub_7_dsub_5_dsub_7
9994      0,	// ssub_6_ssub_7_ssub_8_ssub_9
9995      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9996      0,	// ssub_8_ssub_9_ssub_12_ssub_13
9997      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
9998      0,	// dsub_5_dsub_7
9999      0,	// dsub_5_ssub_12_ssub_13_dsub_7
10000      0,	// dsub_5_ssub_12_ssub_13
10001      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10002    },
10003    {	// DTripleSpc_with_ssub_0
10004      45,	// dsub_0 -> DTripleSpc_with_ssub_0
10005      0,	// dsub_1
10006      45,	// dsub_2 -> DTripleSpc_with_ssub_0
10007      0,	// dsub_3
10008      45,	// dsub_4 -> DTripleSpc_with_ssub_0
10009      0,	// dsub_5
10010      0,	// dsub_6
10011      0,	// dsub_7
10012      0,	// gsub_0
10013      0,	// gsub_1
10014      0,	// qqsub_0
10015      0,	// qqsub_1
10016      0,	// qsub_0
10017      0,	// qsub_1
10018      0,	// qsub_2
10019      0,	// qsub_3
10020      45,	// ssub_0 -> DTripleSpc_with_ssub_0
10021      45,	// ssub_1 -> DTripleSpc_with_ssub_0
10022      0,	// ssub_2
10023      0,	// ssub_3
10024      50,	// ssub_4 -> DTripleSpc_with_ssub_4
10025      50,	// ssub_5 -> DTripleSpc_with_ssub_4
10026      0,	// ssub_6
10027      0,	// ssub_7
10028      52,	// ssub_8 -> DTripleSpc_with_ssub_8
10029      52,	// ssub_9 -> DTripleSpc_with_ssub_8
10030      0,	// ssub_10
10031      0,	// ssub_11
10032      0,	// ssub_12
10033      0,	// ssub_13
10034      0,	// dsub_7_then_ssub_0
10035      0,	// dsub_7_then_ssub_1
10036      45,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_ssub_0
10037      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10038      0,	// ssub_2_ssub_3_ssub_6_ssub_7
10039      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10040      0,	// ssub_2_ssub_3_ssub_4_ssub_5
10041      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10042      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10043      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10044      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10045      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10046      45,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_ssub_0
10047      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10048      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10049      0,	// ssub_6_ssub_7_dsub_5
10050      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10051      0,	// ssub_6_ssub_7_dsub_5_dsub_7
10052      0,	// ssub_6_ssub_7_ssub_8_ssub_9
10053      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10054      0,	// ssub_8_ssub_9_ssub_12_ssub_13
10055      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10056      0,	// dsub_5_dsub_7
10057      0,	// dsub_5_ssub_12_ssub_13_dsub_7
10058      0,	// dsub_5_ssub_12_ssub_13
10059      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10060    },
10061    {	// DTriple_with_ssub_0
10062      46,	// dsub_0 -> DTriple_with_ssub_0
10063      46,	// dsub_1 -> DTriple_with_ssub_0
10064      46,	// dsub_2 -> DTriple_with_ssub_0
10065      0,	// dsub_3
10066      0,	// dsub_4
10067      0,	// dsub_5
10068      0,	// dsub_6
10069      0,	// dsub_7
10070      0,	// gsub_0
10071      0,	// gsub_1
10072      0,	// qqsub_0
10073      0,	// qqsub_1
10074      46,	// qsub_0 -> DTriple_with_ssub_0
10075      0,	// qsub_1
10076      0,	// qsub_2
10077      0,	// qsub_3
10078      46,	// ssub_0 -> DTriple_with_ssub_0
10079      46,	// ssub_1 -> DTriple_with_ssub_0
10080      48,	// ssub_2 -> DTriple_with_ssub_2
10081      48,	// ssub_3 -> DTriple_with_ssub_2
10082      51,	// ssub_4 -> DTriple_with_ssub_4
10083      51,	// ssub_5 -> DTriple_with_ssub_4
10084      0,	// ssub_6
10085      0,	// ssub_7
10086      0,	// ssub_8
10087      0,	// ssub_9
10088      0,	// ssub_10
10089      0,	// ssub_11
10090      0,	// ssub_12
10091      0,	// ssub_13
10092      0,	// dsub_7_then_ssub_0
10093      0,	// dsub_7_then_ssub_1
10094      46,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_0
10095      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10096      0,	// ssub_2_ssub_3_ssub_6_ssub_7
10097      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10098      46,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_0
10099      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10100      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10101      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10102      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10103      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10104      0,	// ssub_4_ssub_5_ssub_8_ssub_9
10105      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10106      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10107      0,	// ssub_6_ssub_7_dsub_5
10108      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10109      0,	// ssub_6_ssub_7_dsub_5_dsub_7
10110      0,	// ssub_6_ssub_7_ssub_8_ssub_9
10111      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10112      0,	// ssub_8_ssub_9_ssub_12_ssub_13
10113      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10114      0,	// dsub_5_dsub_7
10115      0,	// dsub_5_ssub_12_ssub_13_dsub_7
10116      0,	// dsub_5_ssub_12_ssub_13
10117      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10118    },
10119    {	// DTriple_with_qsub_0_in_QPR
10120      47,	// dsub_0 -> DTriple_with_qsub_0_in_QPR
10121      47,	// dsub_1 -> DTriple_with_qsub_0_in_QPR
10122      47,	// dsub_2 -> DTriple_with_qsub_0_in_QPR
10123      0,	// dsub_3
10124      0,	// dsub_4
10125      0,	// dsub_5
10126      0,	// dsub_6
10127      0,	// dsub_7
10128      0,	// gsub_0
10129      0,	// gsub_1
10130      0,	// qqsub_0
10131      0,	// qqsub_1
10132      47,	// qsub_0 -> DTriple_with_qsub_0_in_QPR
10133      0,	// qsub_1
10134      0,	// qsub_2
10135      0,	// qsub_3
10136      55,	// ssub_0 -> DTriple_with_qsub_0_in_QPR_VFP2
10137      55,	// ssub_1 -> DTriple_with_qsub_0_in_QPR_VFP2
10138      55,	// ssub_2 -> DTriple_with_qsub_0_in_QPR_VFP2
10139      55,	// ssub_3 -> DTriple_with_qsub_0_in_QPR_VFP2
10140      59,	// ssub_4 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10141      59,	// ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10142      0,	// ssub_6
10143      0,	// ssub_7
10144      0,	// ssub_8
10145      0,	// ssub_9
10146      0,	// ssub_10
10147      0,	// ssub_11
10148      0,	// ssub_12
10149      0,	// ssub_13
10150      0,	// dsub_7_then_ssub_0
10151      0,	// dsub_7_then_ssub_1
10152      47,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR
10153      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10154      0,	// ssub_2_ssub_3_ssub_6_ssub_7
10155      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10156      47,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR
10157      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10158      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10159      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10160      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10161      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10162      0,	// ssub_4_ssub_5_ssub_8_ssub_9
10163      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10164      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10165      0,	// ssub_6_ssub_7_dsub_5
10166      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10167      0,	// ssub_6_ssub_7_dsub_5_dsub_7
10168      0,	// ssub_6_ssub_7_ssub_8_ssub_9
10169      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10170      0,	// ssub_8_ssub_9_ssub_12_ssub_13
10171      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10172      0,	// dsub_5_dsub_7
10173      0,	// dsub_5_ssub_12_ssub_13_dsub_7
10174      0,	// dsub_5_ssub_12_ssub_13
10175      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10176    },
10177    {	// DTriple_with_ssub_2
10178      48,	// dsub_0 -> DTriple_with_ssub_2
10179      48,	// dsub_1 -> DTriple_with_ssub_2
10180      48,	// dsub_2 -> DTriple_with_ssub_2
10181      0,	// dsub_3
10182      0,	// dsub_4
10183      0,	// dsub_5
10184      0,	// dsub_6
10185      0,	// dsub_7
10186      0,	// gsub_0
10187      0,	// gsub_1
10188      0,	// qqsub_0
10189      0,	// qqsub_1
10190      48,	// qsub_0 -> DTriple_with_ssub_2
10191      0,	// qsub_1
10192      0,	// qsub_2
10193      0,	// qsub_3
10194      48,	// ssub_0 -> DTriple_with_ssub_2
10195      48,	// ssub_1 -> DTriple_with_ssub_2
10196      48,	// ssub_2 -> DTriple_with_ssub_2
10197      48,	// ssub_3 -> DTriple_with_ssub_2
10198      51,	// ssub_4 -> DTriple_with_ssub_4
10199      51,	// ssub_5 -> DTriple_with_ssub_4
10200      0,	// ssub_6
10201      0,	// ssub_7
10202      0,	// ssub_8
10203      0,	// ssub_9
10204      0,	// ssub_10
10205      0,	// ssub_11
10206      0,	// ssub_12
10207      0,	// ssub_13
10208      0,	// dsub_7_then_ssub_0
10209      0,	// dsub_7_then_ssub_1
10210      48,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2
10211      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10212      0,	// ssub_2_ssub_3_ssub_6_ssub_7
10213      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10214      48,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2
10215      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10216      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10217      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10218      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10219      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10220      0,	// ssub_4_ssub_5_ssub_8_ssub_9
10221      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10222      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10223      0,	// ssub_6_ssub_7_dsub_5
10224      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10225      0,	// ssub_6_ssub_7_dsub_5_dsub_7
10226      0,	// ssub_6_ssub_7_ssub_8_ssub_9
10227      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10228      0,	// ssub_8_ssub_9_ssub_12_ssub_13
10229      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10230      0,	// dsub_5_dsub_7
10231      0,	// dsub_5_ssub_12_ssub_13_dsub_7
10232      0,	// dsub_5_ssub_12_ssub_13
10233      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10234    },
10235    {	// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10236      49,	// dsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10237      49,	// dsub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10238      49,	// dsub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10239      0,	// dsub_3
10240      0,	// dsub_4
10241      0,	// dsub_5
10242      0,	// dsub_6
10243      0,	// dsub_7
10244      0,	// gsub_0
10245      0,	// gsub_1
10246      0,	// qqsub_0
10247      0,	// qqsub_1
10248      49,	// qsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10249      0,	// qsub_1
10250      0,	// qsub_2
10251      0,	// qsub_3
10252      56,	// ssub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10253      56,	// ssub_1 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10254      58,	// ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10255      58,	// ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10256      58,	// ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10257      58,	// ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10258      0,	// ssub_6
10259      0,	// ssub_7
10260      0,	// ssub_8
10261      0,	// ssub_9
10262      0,	// ssub_10
10263      0,	// ssub_11
10264      0,	// ssub_12
10265      0,	// ssub_13
10266      0,	// dsub_7_then_ssub_0
10267      0,	// dsub_7_then_ssub_1
10268      49,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10269      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10270      0,	// ssub_2_ssub_3_ssub_6_ssub_7
10271      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10272      49,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10273      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10274      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10275      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10276      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10277      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10278      0,	// ssub_4_ssub_5_ssub_8_ssub_9
10279      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10280      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10281      0,	// ssub_6_ssub_7_dsub_5
10282      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10283      0,	// ssub_6_ssub_7_dsub_5_dsub_7
10284      0,	// ssub_6_ssub_7_ssub_8_ssub_9
10285      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10286      0,	// ssub_8_ssub_9_ssub_12_ssub_13
10287      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10288      0,	// dsub_5_dsub_7
10289      0,	// dsub_5_ssub_12_ssub_13_dsub_7
10290      0,	// dsub_5_ssub_12_ssub_13
10291      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10292    },
10293    {	// DTripleSpc_with_ssub_4
10294      50,	// dsub_0 -> DTripleSpc_with_ssub_4
10295      0,	// dsub_1
10296      50,	// dsub_2 -> DTripleSpc_with_ssub_4
10297      0,	// dsub_3
10298      50,	// dsub_4 -> DTripleSpc_with_ssub_4
10299      0,	// dsub_5
10300      0,	// dsub_6
10301      0,	// dsub_7
10302      0,	// gsub_0
10303      0,	// gsub_1
10304      0,	// qqsub_0
10305      0,	// qqsub_1
10306      0,	// qsub_0
10307      0,	// qsub_1
10308      0,	// qsub_2
10309      0,	// qsub_3
10310      50,	// ssub_0 -> DTripleSpc_with_ssub_4
10311      50,	// ssub_1 -> DTripleSpc_with_ssub_4
10312      0,	// ssub_2
10313      0,	// ssub_3
10314      50,	// ssub_4 -> DTripleSpc_with_ssub_4
10315      50,	// ssub_5 -> DTripleSpc_with_ssub_4
10316      0,	// ssub_6
10317      0,	// ssub_7
10318      52,	// ssub_8 -> DTripleSpc_with_ssub_8
10319      52,	// ssub_9 -> DTripleSpc_with_ssub_8
10320      0,	// ssub_10
10321      0,	// ssub_11
10322      0,	// ssub_12
10323      0,	// ssub_13
10324      0,	// dsub_7_then_ssub_0
10325      0,	// dsub_7_then_ssub_1
10326      50,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_ssub_4
10327      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10328      0,	// ssub_2_ssub_3_ssub_6_ssub_7
10329      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10330      0,	// ssub_2_ssub_3_ssub_4_ssub_5
10331      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10332      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10333      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10334      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10335      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10336      50,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_ssub_4
10337      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10338      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10339      0,	// ssub_6_ssub_7_dsub_5
10340      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10341      0,	// ssub_6_ssub_7_dsub_5_dsub_7
10342      0,	// ssub_6_ssub_7_ssub_8_ssub_9
10343      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10344      0,	// ssub_8_ssub_9_ssub_12_ssub_13
10345      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10346      0,	// dsub_5_dsub_7
10347      0,	// dsub_5_ssub_12_ssub_13_dsub_7
10348      0,	// dsub_5_ssub_12_ssub_13
10349      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10350    },
10351    {	// DTriple_with_ssub_4
10352      51,	// dsub_0 -> DTriple_with_ssub_4
10353      51,	// dsub_1 -> DTriple_with_ssub_4
10354      51,	// dsub_2 -> DTriple_with_ssub_4
10355      0,	// dsub_3
10356      0,	// dsub_4
10357      0,	// dsub_5
10358      0,	// dsub_6
10359      0,	// dsub_7
10360      0,	// gsub_0
10361      0,	// gsub_1
10362      0,	// qqsub_0
10363      0,	// qqsub_1
10364      51,	// qsub_0 -> DTriple_with_ssub_4
10365      0,	// qsub_1
10366      0,	// qsub_2
10367      0,	// qsub_3
10368      51,	// ssub_0 -> DTriple_with_ssub_4
10369      51,	// ssub_1 -> DTriple_with_ssub_4
10370      51,	// ssub_2 -> DTriple_with_ssub_4
10371      51,	// ssub_3 -> DTriple_with_ssub_4
10372      51,	// ssub_4 -> DTriple_with_ssub_4
10373      51,	// ssub_5 -> DTriple_with_ssub_4
10374      0,	// ssub_6
10375      0,	// ssub_7
10376      0,	// ssub_8
10377      0,	// ssub_9
10378      0,	// ssub_10
10379      0,	// ssub_11
10380      0,	// ssub_12
10381      0,	// ssub_13
10382      0,	// dsub_7_then_ssub_0
10383      0,	// dsub_7_then_ssub_1
10384      51,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_4
10385      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10386      0,	// ssub_2_ssub_3_ssub_6_ssub_7
10387      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10388      51,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_4
10389      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10390      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10391      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10392      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10393      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10394      0,	// ssub_4_ssub_5_ssub_8_ssub_9
10395      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10396      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10397      0,	// ssub_6_ssub_7_dsub_5
10398      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10399      0,	// ssub_6_ssub_7_dsub_5_dsub_7
10400      0,	// ssub_6_ssub_7_ssub_8_ssub_9
10401      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10402      0,	// ssub_8_ssub_9_ssub_12_ssub_13
10403      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10404      0,	// dsub_5_dsub_7
10405      0,	// dsub_5_ssub_12_ssub_13_dsub_7
10406      0,	// dsub_5_ssub_12_ssub_13
10407      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10408    },
10409    {	// DTripleSpc_with_ssub_8
10410      52,	// dsub_0 -> DTripleSpc_with_ssub_8
10411      0,	// dsub_1
10412      52,	// dsub_2 -> DTripleSpc_with_ssub_8
10413      0,	// dsub_3
10414      52,	// dsub_4 -> DTripleSpc_with_ssub_8
10415      0,	// dsub_5
10416      0,	// dsub_6
10417      0,	// dsub_7
10418      0,	// gsub_0
10419      0,	// gsub_1
10420      0,	// qqsub_0
10421      0,	// qqsub_1
10422      0,	// qsub_0
10423      0,	// qsub_1
10424      0,	// qsub_2
10425      0,	// qsub_3
10426      52,	// ssub_0 -> DTripleSpc_with_ssub_8
10427      52,	// ssub_1 -> DTripleSpc_with_ssub_8
10428      0,	// ssub_2
10429      0,	// ssub_3
10430      52,	// ssub_4 -> DTripleSpc_with_ssub_8
10431      52,	// ssub_5 -> DTripleSpc_with_ssub_8
10432      0,	// ssub_6
10433      0,	// ssub_7
10434      52,	// ssub_8 -> DTripleSpc_with_ssub_8
10435      52,	// ssub_9 -> DTripleSpc_with_ssub_8
10436      0,	// ssub_10
10437      0,	// ssub_11
10438      0,	// ssub_12
10439      0,	// ssub_13
10440      0,	// dsub_7_then_ssub_0
10441      0,	// dsub_7_then_ssub_1
10442      52,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_ssub_8
10443      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10444      0,	// ssub_2_ssub_3_ssub_6_ssub_7
10445      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10446      0,	// ssub_2_ssub_3_ssub_4_ssub_5
10447      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10448      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10449      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10450      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10451      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10452      52,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_ssub_8
10453      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10454      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10455      0,	// ssub_6_ssub_7_dsub_5
10456      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10457      0,	// ssub_6_ssub_7_dsub_5_dsub_7
10458      0,	// ssub_6_ssub_7_ssub_8_ssub_9
10459      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10460      0,	// ssub_8_ssub_9_ssub_12_ssub_13
10461      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10462      0,	// dsub_5_dsub_7
10463      0,	// dsub_5_ssub_12_ssub_13_dsub_7
10464      0,	// dsub_5_ssub_12_ssub_13
10465      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10466    },
10467    {	// DTripleSpc_with_dsub_0_in_DPR_8
10468      53,	// dsub_0 -> DTripleSpc_with_dsub_0_in_DPR_8
10469      0,	// dsub_1
10470      53,	// dsub_2 -> DTripleSpc_with_dsub_0_in_DPR_8
10471      0,	// dsub_3
10472      53,	// dsub_4 -> DTripleSpc_with_dsub_0_in_DPR_8
10473      0,	// dsub_5
10474      0,	// dsub_6
10475      0,	// dsub_7
10476      0,	// gsub_0
10477      0,	// gsub_1
10478      0,	// qqsub_0
10479      0,	// qqsub_1
10480      0,	// qsub_0
10481      0,	// qsub_1
10482      0,	// qsub_2
10483      0,	// qsub_3
10484      53,	// ssub_0 -> DTripleSpc_with_dsub_0_in_DPR_8
10485      53,	// ssub_1 -> DTripleSpc_with_dsub_0_in_DPR_8
10486      0,	// ssub_2
10487      0,	// ssub_3
10488      53,	// ssub_4 -> DTripleSpc_with_dsub_0_in_DPR_8
10489      53,	// ssub_5 -> DTripleSpc_with_dsub_0_in_DPR_8
10490      0,	// ssub_6
10491      0,	// ssub_7
10492      53,	// ssub_8 -> DTripleSpc_with_dsub_0_in_DPR_8
10493      53,	// ssub_9 -> DTripleSpc_with_dsub_0_in_DPR_8
10494      0,	// ssub_10
10495      0,	// ssub_11
10496      0,	// ssub_12
10497      0,	// ssub_13
10498      0,	// dsub_7_then_ssub_0
10499      0,	// dsub_7_then_ssub_1
10500      53,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_dsub_0_in_DPR_8
10501      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10502      0,	// ssub_2_ssub_3_ssub_6_ssub_7
10503      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10504      0,	// ssub_2_ssub_3_ssub_4_ssub_5
10505      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10506      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10507      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10508      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10509      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10510      53,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_dsub_0_in_DPR_8
10511      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10512      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10513      0,	// ssub_6_ssub_7_dsub_5
10514      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10515      0,	// ssub_6_ssub_7_dsub_5_dsub_7
10516      0,	// ssub_6_ssub_7_ssub_8_ssub_9
10517      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10518      0,	// ssub_8_ssub_9_ssub_12_ssub_13
10519      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10520      0,	// dsub_5_dsub_7
10521      0,	// dsub_5_ssub_12_ssub_13_dsub_7
10522      0,	// dsub_5_ssub_12_ssub_13
10523      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10524    },
10525    {	// DTriple_with_dsub_0_in_DPR_8
10526      54,	// dsub_0 -> DTriple_with_dsub_0_in_DPR_8
10527      54,	// dsub_1 -> DTriple_with_dsub_0_in_DPR_8
10528      54,	// dsub_2 -> DTriple_with_dsub_0_in_DPR_8
10529      0,	// dsub_3
10530      0,	// dsub_4
10531      0,	// dsub_5
10532      0,	// dsub_6
10533      0,	// dsub_7
10534      0,	// gsub_0
10535      0,	// gsub_1
10536      0,	// qqsub_0
10537      0,	// qqsub_1
10538      54,	// qsub_0 -> DTriple_with_dsub_0_in_DPR_8
10539      0,	// qsub_1
10540      0,	// qsub_2
10541      0,	// qsub_3
10542      54,	// ssub_0 -> DTriple_with_dsub_0_in_DPR_8
10543      54,	// ssub_1 -> DTriple_with_dsub_0_in_DPR_8
10544      54,	// ssub_2 -> DTriple_with_dsub_0_in_DPR_8
10545      54,	// ssub_3 -> DTriple_with_dsub_0_in_DPR_8
10546      54,	// ssub_4 -> DTriple_with_dsub_0_in_DPR_8
10547      54,	// ssub_5 -> DTriple_with_dsub_0_in_DPR_8
10548      0,	// ssub_6
10549      0,	// ssub_7
10550      0,	// ssub_8
10551      0,	// ssub_9
10552      0,	// ssub_10
10553      0,	// ssub_11
10554      0,	// ssub_12
10555      0,	// ssub_13
10556      0,	// dsub_7_then_ssub_0
10557      0,	// dsub_7_then_ssub_1
10558      54,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8
10559      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10560      0,	// ssub_2_ssub_3_ssub_6_ssub_7
10561      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10562      54,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8
10563      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10564      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10565      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10566      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10567      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10568      0,	// ssub_4_ssub_5_ssub_8_ssub_9
10569      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10570      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10571      0,	// ssub_6_ssub_7_dsub_5
10572      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10573      0,	// ssub_6_ssub_7_dsub_5_dsub_7
10574      0,	// ssub_6_ssub_7_ssub_8_ssub_9
10575      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10576      0,	// ssub_8_ssub_9_ssub_12_ssub_13
10577      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10578      0,	// dsub_5_dsub_7
10579      0,	// dsub_5_ssub_12_ssub_13_dsub_7
10580      0,	// dsub_5_ssub_12_ssub_13
10581      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10582    },
10583    {	// DTriple_with_qsub_0_in_QPR_VFP2
10584      55,	// dsub_0 -> DTriple_with_qsub_0_in_QPR_VFP2
10585      55,	// dsub_1 -> DTriple_with_qsub_0_in_QPR_VFP2
10586      55,	// dsub_2 -> DTriple_with_qsub_0_in_QPR_VFP2
10587      0,	// dsub_3
10588      0,	// dsub_4
10589      0,	// dsub_5
10590      0,	// dsub_6
10591      0,	// dsub_7
10592      0,	// gsub_0
10593      0,	// gsub_1
10594      0,	// qqsub_0
10595      0,	// qqsub_1
10596      55,	// qsub_0 -> DTriple_with_qsub_0_in_QPR_VFP2
10597      0,	// qsub_1
10598      0,	// qsub_2
10599      0,	// qsub_3
10600      55,	// ssub_0 -> DTriple_with_qsub_0_in_QPR_VFP2
10601      55,	// ssub_1 -> DTriple_with_qsub_0_in_QPR_VFP2
10602      55,	// ssub_2 -> DTriple_with_qsub_0_in_QPR_VFP2
10603      55,	// ssub_3 -> DTriple_with_qsub_0_in_QPR_VFP2
10604      59,	// ssub_4 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10605      59,	// ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10606      0,	// ssub_6
10607      0,	// ssub_7
10608      0,	// ssub_8
10609      0,	// ssub_9
10610      0,	// ssub_10
10611      0,	// ssub_11
10612      0,	// ssub_12
10613      0,	// ssub_13
10614      0,	// dsub_7_then_ssub_0
10615      0,	// dsub_7_then_ssub_1
10616      55,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR_VFP2
10617      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10618      0,	// ssub_2_ssub_3_ssub_6_ssub_7
10619      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10620      55,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR_VFP2
10621      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10622      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10623      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10624      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10625      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10626      0,	// ssub_4_ssub_5_ssub_8_ssub_9
10627      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10628      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10629      0,	// ssub_6_ssub_7_dsub_5
10630      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10631      0,	// ssub_6_ssub_7_dsub_5_dsub_7
10632      0,	// ssub_6_ssub_7_ssub_8_ssub_9
10633      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10634      0,	// ssub_8_ssub_9_ssub_12_ssub_13
10635      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10636      0,	// dsub_5_dsub_7
10637      0,	// dsub_5_ssub_12_ssub_13_dsub_7
10638      0,	// dsub_5_ssub_12_ssub_13
10639      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10640    },
10641    {	// DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10642      56,	// dsub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10643      56,	// dsub_1 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10644      56,	// dsub_2 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10645      0,	// dsub_3
10646      0,	// dsub_4
10647      0,	// dsub_5
10648      0,	// dsub_6
10649      0,	// dsub_7
10650      0,	// gsub_0
10651      0,	// gsub_1
10652      0,	// qqsub_0
10653      0,	// qqsub_1
10654      56,	// qsub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10655      0,	// qsub_1
10656      0,	// qsub_2
10657      0,	// qsub_3
10658      56,	// ssub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10659      56,	// ssub_1 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10660      58,	// ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10661      58,	// ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10662      58,	// ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10663      58,	// ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10664      0,	// ssub_6
10665      0,	// ssub_7
10666      0,	// ssub_8
10667      0,	// ssub_9
10668      0,	// ssub_10
10669      0,	// ssub_11
10670      0,	// ssub_12
10671      0,	// ssub_13
10672      0,	// dsub_7_then_ssub_0
10673      0,	// dsub_7_then_ssub_1
10674      56,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10675      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10676      0,	// ssub_2_ssub_3_ssub_6_ssub_7
10677      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10678      56,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
10679      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10680      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10681      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10682      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10683      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10684      0,	// ssub_4_ssub_5_ssub_8_ssub_9
10685      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10686      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10687      0,	// ssub_6_ssub_7_dsub_5
10688      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10689      0,	// ssub_6_ssub_7_dsub_5_dsub_7
10690      0,	// ssub_6_ssub_7_ssub_8_ssub_9
10691      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10692      0,	// ssub_8_ssub_9_ssub_12_ssub_13
10693      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10694      0,	// dsub_5_dsub_7
10695      0,	// dsub_5_ssub_12_ssub_13_dsub_7
10696      0,	// dsub_5_ssub_12_ssub_13
10697      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10698    },
10699    {	// DTriple_with_dsub_1_in_DPR_8
10700      57,	// dsub_0 -> DTriple_with_dsub_1_in_DPR_8
10701      57,	// dsub_1 -> DTriple_with_dsub_1_in_DPR_8
10702      57,	// dsub_2 -> DTriple_with_dsub_1_in_DPR_8
10703      0,	// dsub_3
10704      0,	// dsub_4
10705      0,	// dsub_5
10706      0,	// dsub_6
10707      0,	// dsub_7
10708      0,	// gsub_0
10709      0,	// gsub_1
10710      0,	// qqsub_0
10711      0,	// qqsub_1
10712      57,	// qsub_0 -> DTriple_with_dsub_1_in_DPR_8
10713      0,	// qsub_1
10714      0,	// qsub_2
10715      0,	// qsub_3
10716      57,	// ssub_0 -> DTriple_with_dsub_1_in_DPR_8
10717      57,	// ssub_1 -> DTriple_with_dsub_1_in_DPR_8
10718      57,	// ssub_2 -> DTriple_with_dsub_1_in_DPR_8
10719      57,	// ssub_3 -> DTriple_with_dsub_1_in_DPR_8
10720      57,	// ssub_4 -> DTriple_with_dsub_1_in_DPR_8
10721      57,	// ssub_5 -> DTriple_with_dsub_1_in_DPR_8
10722      0,	// ssub_6
10723      0,	// ssub_7
10724      0,	// ssub_8
10725      0,	// ssub_9
10726      0,	// ssub_10
10727      0,	// ssub_11
10728      0,	// ssub_12
10729      0,	// ssub_13
10730      0,	// dsub_7_then_ssub_0
10731      0,	// dsub_7_then_ssub_1
10732      57,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_1_in_DPR_8
10733      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10734      0,	// ssub_2_ssub_3_ssub_6_ssub_7
10735      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10736      57,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_1_in_DPR_8
10737      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10738      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10739      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10740      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10741      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10742      0,	// ssub_4_ssub_5_ssub_8_ssub_9
10743      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10744      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10745      0,	// ssub_6_ssub_7_dsub_5
10746      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10747      0,	// ssub_6_ssub_7_dsub_5_dsub_7
10748      0,	// ssub_6_ssub_7_ssub_8_ssub_9
10749      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10750      0,	// ssub_8_ssub_9_ssub_12_ssub_13
10751      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10752      0,	// dsub_5_dsub_7
10753      0,	// dsub_5_ssub_12_ssub_13_dsub_7
10754      0,	// dsub_5_ssub_12_ssub_13
10755      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10756    },
10757    {	// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10758      58,	// dsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10759      58,	// dsub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10760      58,	// dsub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10761      0,	// dsub_3
10762      0,	// dsub_4
10763      0,	// dsub_5
10764      0,	// dsub_6
10765      0,	// dsub_7
10766      0,	// gsub_0
10767      0,	// gsub_1
10768      0,	// qqsub_0
10769      0,	// qqsub_1
10770      58,	// qsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10771      0,	// qsub_1
10772      0,	// qsub_2
10773      0,	// qsub_3
10774      58,	// ssub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10775      58,	// ssub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10776      58,	// ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10777      58,	// ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10778      58,	// ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10779      58,	// ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10780      0,	// ssub_6
10781      0,	// ssub_7
10782      0,	// ssub_8
10783      0,	// ssub_9
10784      0,	// ssub_10
10785      0,	// ssub_11
10786      0,	// ssub_12
10787      0,	// ssub_13
10788      0,	// dsub_7_then_ssub_0
10789      0,	// dsub_7_then_ssub_1
10790      58,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10791      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10792      0,	// ssub_2_ssub_3_ssub_6_ssub_7
10793      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10794      58,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
10795      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10796      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10797      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10798      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10799      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10800      0,	// ssub_4_ssub_5_ssub_8_ssub_9
10801      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10802      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10803      0,	// ssub_6_ssub_7_dsub_5
10804      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10805      0,	// ssub_6_ssub_7_dsub_5_dsub_7
10806      0,	// ssub_6_ssub_7_ssub_8_ssub_9
10807      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10808      0,	// ssub_8_ssub_9_ssub_12_ssub_13
10809      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10810      0,	// dsub_5_dsub_7
10811      0,	// dsub_5_ssub_12_ssub_13_dsub_7
10812      0,	// dsub_5_ssub_12_ssub_13
10813      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10814    },
10815    {	// DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10816      59,	// dsub_0 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10817      59,	// dsub_1 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10818      59,	// dsub_2 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10819      0,	// dsub_3
10820      0,	// dsub_4
10821      0,	// dsub_5
10822      0,	// dsub_6
10823      0,	// dsub_7
10824      0,	// gsub_0
10825      0,	// gsub_1
10826      0,	// qqsub_0
10827      0,	// qqsub_1
10828      59,	// qsub_0 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10829      0,	// qsub_1
10830      0,	// qsub_2
10831      0,	// qsub_3
10832      59,	// ssub_0 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10833      59,	// ssub_1 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10834      59,	// ssub_2 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10835      59,	// ssub_3 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10836      59,	// ssub_4 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10837      59,	// ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10838      0,	// ssub_6
10839      0,	// ssub_7
10840      0,	// ssub_8
10841      0,	// ssub_9
10842      0,	// ssub_10
10843      0,	// ssub_11
10844      0,	// ssub_12
10845      0,	// ssub_13
10846      0,	// dsub_7_then_ssub_0
10847      0,	// dsub_7_then_ssub_1
10848      59,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10849      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10850      0,	// ssub_2_ssub_3_ssub_6_ssub_7
10851      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10852      59,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
10853      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10854      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10855      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10856      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10857      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10858      0,	// ssub_4_ssub_5_ssub_8_ssub_9
10859      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10860      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10861      0,	// ssub_6_ssub_7_dsub_5
10862      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10863      0,	// ssub_6_ssub_7_dsub_5_dsub_7
10864      0,	// ssub_6_ssub_7_ssub_8_ssub_9
10865      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10866      0,	// ssub_8_ssub_9_ssub_12_ssub_13
10867      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10868      0,	// dsub_5_dsub_7
10869      0,	// dsub_5_ssub_12_ssub_13_dsub_7
10870      0,	// dsub_5_ssub_12_ssub_13
10871      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10872    },
10873    {	// DTripleSpc_with_dsub_2_in_DPR_8
10874      60,	// dsub_0 -> DTripleSpc_with_dsub_2_in_DPR_8
10875      0,	// dsub_1
10876      60,	// dsub_2 -> DTripleSpc_with_dsub_2_in_DPR_8
10877      0,	// dsub_3
10878      60,	// dsub_4 -> DTripleSpc_with_dsub_2_in_DPR_8
10879      0,	// dsub_5
10880      0,	// dsub_6
10881      0,	// dsub_7
10882      0,	// gsub_0
10883      0,	// gsub_1
10884      0,	// qqsub_0
10885      0,	// qqsub_1
10886      0,	// qsub_0
10887      0,	// qsub_1
10888      0,	// qsub_2
10889      0,	// qsub_3
10890      60,	// ssub_0 -> DTripleSpc_with_dsub_2_in_DPR_8
10891      60,	// ssub_1 -> DTripleSpc_with_dsub_2_in_DPR_8
10892      0,	// ssub_2
10893      0,	// ssub_3
10894      60,	// ssub_4 -> DTripleSpc_with_dsub_2_in_DPR_8
10895      60,	// ssub_5 -> DTripleSpc_with_dsub_2_in_DPR_8
10896      0,	// ssub_6
10897      0,	// ssub_7
10898      60,	// ssub_8 -> DTripleSpc_with_dsub_2_in_DPR_8
10899      60,	// ssub_9 -> DTripleSpc_with_dsub_2_in_DPR_8
10900      0,	// ssub_10
10901      0,	// ssub_11
10902      0,	// ssub_12
10903      0,	// ssub_13
10904      0,	// dsub_7_then_ssub_0
10905      0,	// dsub_7_then_ssub_1
10906      60,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_dsub_2_in_DPR_8
10907      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10908      0,	// ssub_2_ssub_3_ssub_6_ssub_7
10909      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10910      0,	// ssub_2_ssub_3_ssub_4_ssub_5
10911      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10912      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10913      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10914      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10915      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10916      60,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_dsub_2_in_DPR_8
10917      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10918      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10919      0,	// ssub_6_ssub_7_dsub_5
10920      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10921      0,	// ssub_6_ssub_7_dsub_5_dsub_7
10922      0,	// ssub_6_ssub_7_ssub_8_ssub_9
10923      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10924      0,	// ssub_8_ssub_9_ssub_12_ssub_13
10925      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10926      0,	// dsub_5_dsub_7
10927      0,	// dsub_5_ssub_12_ssub_13_dsub_7
10928      0,	// dsub_5_ssub_12_ssub_13
10929      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10930    },
10931    {	// DTriple_with_dsub_2_in_DPR_8
10932      61,	// dsub_0 -> DTriple_with_dsub_2_in_DPR_8
10933      61,	// dsub_1 -> DTriple_with_dsub_2_in_DPR_8
10934      61,	// dsub_2 -> DTriple_with_dsub_2_in_DPR_8
10935      0,	// dsub_3
10936      0,	// dsub_4
10937      0,	// dsub_5
10938      0,	// dsub_6
10939      0,	// dsub_7
10940      0,	// gsub_0
10941      0,	// gsub_1
10942      0,	// qqsub_0
10943      0,	// qqsub_1
10944      61,	// qsub_0 -> DTriple_with_dsub_2_in_DPR_8
10945      0,	// qsub_1
10946      0,	// qsub_2
10947      0,	// qsub_3
10948      61,	// ssub_0 -> DTriple_with_dsub_2_in_DPR_8
10949      61,	// ssub_1 -> DTriple_with_dsub_2_in_DPR_8
10950      61,	// ssub_2 -> DTriple_with_dsub_2_in_DPR_8
10951      61,	// ssub_3 -> DTriple_with_dsub_2_in_DPR_8
10952      61,	// ssub_4 -> DTriple_with_dsub_2_in_DPR_8
10953      61,	// ssub_5 -> DTriple_with_dsub_2_in_DPR_8
10954      0,	// ssub_6
10955      0,	// ssub_7
10956      0,	// ssub_8
10957      0,	// ssub_9
10958      0,	// ssub_10
10959      0,	// ssub_11
10960      0,	// ssub_12
10961      0,	// ssub_13
10962      0,	// dsub_7_then_ssub_0
10963      0,	// dsub_7_then_ssub_1
10964      61,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8
10965      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
10966      0,	// ssub_2_ssub_3_ssub_6_ssub_7
10967      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
10968      61,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8
10969      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
10970      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10971      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
10972      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
10973      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10974      0,	// ssub_4_ssub_5_ssub_8_ssub_9
10975      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
10976      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
10977      0,	// ssub_6_ssub_7_dsub_5
10978      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
10979      0,	// ssub_6_ssub_7_dsub_5_dsub_7
10980      0,	// ssub_6_ssub_7_ssub_8_ssub_9
10981      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10982      0,	// ssub_8_ssub_9_ssub_12_ssub_13
10983      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
10984      0,	// dsub_5_dsub_7
10985      0,	// dsub_5_ssub_12_ssub_13_dsub_7
10986      0,	// dsub_5_ssub_12_ssub_13
10987      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
10988    },
10989    {	// DTripleSpc_with_dsub_4_in_DPR_8
10990      62,	// dsub_0 -> DTripleSpc_with_dsub_4_in_DPR_8
10991      0,	// dsub_1
10992      62,	// dsub_2 -> DTripleSpc_with_dsub_4_in_DPR_8
10993      0,	// dsub_3
10994      62,	// dsub_4 -> DTripleSpc_with_dsub_4_in_DPR_8
10995      0,	// dsub_5
10996      0,	// dsub_6
10997      0,	// dsub_7
10998      0,	// gsub_0
10999      0,	// gsub_1
11000      0,	// qqsub_0
11001      0,	// qqsub_1
11002      0,	// qsub_0
11003      0,	// qsub_1
11004      0,	// qsub_2
11005      0,	// qsub_3
11006      62,	// ssub_0 -> DTripleSpc_with_dsub_4_in_DPR_8
11007      62,	// ssub_1 -> DTripleSpc_with_dsub_4_in_DPR_8
11008      0,	// ssub_2
11009      0,	// ssub_3
11010      62,	// ssub_4 -> DTripleSpc_with_dsub_4_in_DPR_8
11011      62,	// ssub_5 -> DTripleSpc_with_dsub_4_in_DPR_8
11012      0,	// ssub_6
11013      0,	// ssub_7
11014      62,	// ssub_8 -> DTripleSpc_with_dsub_4_in_DPR_8
11015      62,	// ssub_9 -> DTripleSpc_with_dsub_4_in_DPR_8
11016      0,	// ssub_10
11017      0,	// ssub_11
11018      0,	// ssub_12
11019      0,	// ssub_13
11020      0,	// dsub_7_then_ssub_0
11021      0,	// dsub_7_then_ssub_1
11022      62,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_dsub_4_in_DPR_8
11023      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11024      0,	// ssub_2_ssub_3_ssub_6_ssub_7
11025      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11026      0,	// ssub_2_ssub_3_ssub_4_ssub_5
11027      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11028      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11029      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11030      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11031      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11032      62,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_dsub_4_in_DPR_8
11033      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11034      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11035      0,	// ssub_6_ssub_7_dsub_5
11036      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11037      0,	// ssub_6_ssub_7_dsub_5_dsub_7
11038      0,	// ssub_6_ssub_7_ssub_8_ssub_9
11039      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11040      0,	// ssub_8_ssub_9_ssub_12_ssub_13
11041      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11042      0,	// dsub_5_dsub_7
11043      0,	// dsub_5_ssub_12_ssub_13_dsub_7
11044      0,	// dsub_5_ssub_12_ssub_13
11045      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11046    },
11047    {	// DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11048      63,	// dsub_0 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11049      63,	// dsub_1 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11050      63,	// dsub_2 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11051      0,	// dsub_3
11052      0,	// dsub_4
11053      0,	// dsub_5
11054      0,	// dsub_6
11055      0,	// dsub_7
11056      0,	// gsub_0
11057      0,	// gsub_1
11058      0,	// qqsub_0
11059      0,	// qqsub_1
11060      63,	// qsub_0 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11061      0,	// qsub_1
11062      0,	// qsub_2
11063      0,	// qsub_3
11064      63,	// ssub_0 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11065      63,	// ssub_1 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11066      63,	// ssub_2 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11067      63,	// ssub_3 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11068      63,	// ssub_4 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11069      63,	// ssub_5 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11070      0,	// ssub_6
11071      0,	// ssub_7
11072      0,	// ssub_8
11073      0,	// ssub_9
11074      0,	// ssub_10
11075      0,	// ssub_11
11076      0,	// ssub_12
11077      0,	// ssub_13
11078      0,	// dsub_7_then_ssub_0
11079      0,	// dsub_7_then_ssub_1
11080      63,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11081      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11082      0,	// ssub_2_ssub_3_ssub_6_ssub_7
11083      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11084      63,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11085      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11086      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11087      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11088      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11089      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11090      0,	// ssub_4_ssub_5_ssub_8_ssub_9
11091      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11092      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11093      0,	// ssub_6_ssub_7_dsub_5
11094      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11095      0,	// ssub_6_ssub_7_dsub_5_dsub_7
11096      0,	// ssub_6_ssub_7_ssub_8_ssub_9
11097      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11098      0,	// ssub_8_ssub_9_ssub_12_ssub_13
11099      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11100      0,	// dsub_5_dsub_7
11101      0,	// dsub_5_ssub_12_ssub_13_dsub_7
11102      0,	// dsub_5_ssub_12_ssub_13
11103      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11104    },
11105    {	// DTriple_with_qsub_0_in_QPR_8
11106      64,	// dsub_0 -> DTriple_with_qsub_0_in_QPR_8
11107      64,	// dsub_1 -> DTriple_with_qsub_0_in_QPR_8
11108      64,	// dsub_2 -> DTriple_with_qsub_0_in_QPR_8
11109      0,	// dsub_3
11110      0,	// dsub_4
11111      0,	// dsub_5
11112      0,	// dsub_6
11113      0,	// dsub_7
11114      0,	// gsub_0
11115      0,	// gsub_1
11116      0,	// qqsub_0
11117      0,	// qqsub_1
11118      64,	// qsub_0 -> DTriple_with_qsub_0_in_QPR_8
11119      0,	// qsub_1
11120      0,	// qsub_2
11121      0,	// qsub_3
11122      64,	// ssub_0 -> DTriple_with_qsub_0_in_QPR_8
11123      64,	// ssub_1 -> DTriple_with_qsub_0_in_QPR_8
11124      64,	// ssub_2 -> DTriple_with_qsub_0_in_QPR_8
11125      64,	// ssub_3 -> DTriple_with_qsub_0_in_QPR_8
11126      64,	// ssub_4 -> DTriple_with_qsub_0_in_QPR_8
11127      64,	// ssub_5 -> DTriple_with_qsub_0_in_QPR_8
11128      0,	// ssub_6
11129      0,	// ssub_7
11130      0,	// ssub_8
11131      0,	// ssub_9
11132      0,	// ssub_10
11133      0,	// ssub_11
11134      0,	// ssub_12
11135      0,	// ssub_13
11136      0,	// dsub_7_then_ssub_0
11137      0,	// dsub_7_then_ssub_1
11138      64,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR_8
11139      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11140      0,	// ssub_2_ssub_3_ssub_6_ssub_7
11141      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11142      64,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR_8
11143      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11144      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11145      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11146      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11147      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11148      0,	// ssub_4_ssub_5_ssub_8_ssub_9
11149      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11150      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11151      0,	// ssub_6_ssub_7_dsub_5
11152      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11153      0,	// ssub_6_ssub_7_dsub_5_dsub_7
11154      0,	// ssub_6_ssub_7_ssub_8_ssub_9
11155      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11156      0,	// ssub_8_ssub_9_ssub_12_ssub_13
11157      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11158      0,	// dsub_5_dsub_7
11159      0,	// dsub_5_ssub_12_ssub_13_dsub_7
11160      0,	// dsub_5_ssub_12_ssub_13
11161      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11162    },
11163    {	// DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11164      65,	// dsub_0 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11165      65,	// dsub_1 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11166      65,	// dsub_2 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11167      0,	// dsub_3
11168      0,	// dsub_4
11169      0,	// dsub_5
11170      0,	// dsub_6
11171      0,	// dsub_7
11172      0,	// gsub_0
11173      0,	// gsub_1
11174      0,	// qqsub_0
11175      0,	// qqsub_1
11176      65,	// qsub_0 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11177      0,	// qsub_1
11178      0,	// qsub_2
11179      0,	// qsub_3
11180      65,	// ssub_0 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11181      65,	// ssub_1 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11182      65,	// ssub_2 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11183      65,	// ssub_3 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11184      65,	// ssub_4 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11185      65,	// ssub_5 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11186      0,	// ssub_6
11187      0,	// ssub_7
11188      0,	// ssub_8
11189      0,	// ssub_9
11190      0,	// ssub_10
11191      0,	// ssub_11
11192      0,	// ssub_12
11193      0,	// ssub_13
11194      0,	// dsub_7_then_ssub_0
11195      0,	// dsub_7_then_ssub_1
11196      65,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11197      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11198      0,	// ssub_2_ssub_3_ssub_6_ssub_7
11199      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11200      65,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
11201      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11202      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11203      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11204      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11205      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11206      0,	// ssub_4_ssub_5_ssub_8_ssub_9
11207      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11208      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11209      0,	// ssub_6_ssub_7_dsub_5
11210      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11211      0,	// ssub_6_ssub_7_dsub_5_dsub_7
11212      0,	// ssub_6_ssub_7_ssub_8_ssub_9
11213      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11214      0,	// ssub_8_ssub_9_ssub_12_ssub_13
11215      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11216      0,	// dsub_5_dsub_7
11217      0,	// dsub_5_ssub_12_ssub_13_dsub_7
11218      0,	// dsub_5_ssub_12_ssub_13
11219      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11220    },
11221    {	// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11222      66,	// dsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11223      66,	// dsub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11224      66,	// dsub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11225      0,	// dsub_3
11226      0,	// dsub_4
11227      0,	// dsub_5
11228      0,	// dsub_6
11229      0,	// dsub_7
11230      0,	// gsub_0
11231      0,	// gsub_1
11232      0,	// qqsub_0
11233      0,	// qqsub_1
11234      66,	// qsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11235      0,	// qsub_1
11236      0,	// qsub_2
11237      0,	// qsub_3
11238      66,	// ssub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11239      66,	// ssub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11240      66,	// ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11241      66,	// ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11242      66,	// ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11243      66,	// ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11244      0,	// ssub_6
11245      0,	// ssub_7
11246      0,	// ssub_8
11247      0,	// ssub_9
11248      0,	// ssub_10
11249      0,	// ssub_11
11250      0,	// ssub_12
11251      0,	// ssub_13
11252      0,	// dsub_7_then_ssub_0
11253      0,	// dsub_7_then_ssub_1
11254      66,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11255      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11256      0,	// ssub_2_ssub_3_ssub_6_ssub_7
11257      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11258      66,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
11259      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11260      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11261      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11262      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11263      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11264      0,	// ssub_4_ssub_5_ssub_8_ssub_9
11265      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11266      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11267      0,	// ssub_6_ssub_7_dsub_5
11268      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11269      0,	// ssub_6_ssub_7_dsub_5_dsub_7
11270      0,	// ssub_6_ssub_7_ssub_8_ssub_9
11271      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11272      0,	// ssub_8_ssub_9_ssub_12_ssub_13
11273      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11274      0,	// dsub_5_dsub_7
11275      0,	// dsub_5_ssub_12_ssub_13_dsub_7
11276      0,	// dsub_5_ssub_12_ssub_13
11277      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11278    },
11279    {	// DQuadSpc
11280      67,	// dsub_0 -> DQuadSpc
11281      0,	// dsub_1
11282      67,	// dsub_2 -> DQuadSpc
11283      0,	// dsub_3
11284      67,	// dsub_4 -> DQuadSpc
11285      0,	// dsub_5
11286      0,	// dsub_6
11287      0,	// dsub_7
11288      0,	// gsub_0
11289      0,	// gsub_1
11290      0,	// qqsub_0
11291      0,	// qqsub_1
11292      0,	// qsub_0
11293      0,	// qsub_1
11294      0,	// qsub_2
11295      0,	// qsub_3
11296      68,	// ssub_0 -> DQuadSpc_with_ssub_0
11297      68,	// ssub_1 -> DQuadSpc_with_ssub_0
11298      0,	// ssub_2
11299      0,	// ssub_3
11300      69,	// ssub_4 -> DQuadSpc_with_ssub_4
11301      69,	// ssub_5 -> DQuadSpc_with_ssub_4
11302      0,	// ssub_6
11303      0,	// ssub_7
11304      70,	// ssub_8 -> DQuadSpc_with_ssub_8
11305      70,	// ssub_9 -> DQuadSpc_with_ssub_8
11306      0,	// ssub_10
11307      0,	// ssub_11
11308      0,	// ssub_12
11309      0,	// ssub_13
11310      0,	// dsub_7_then_ssub_0
11311      0,	// dsub_7_then_ssub_1
11312      67,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc
11313      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11314      0,	// ssub_2_ssub_3_ssub_6_ssub_7
11315      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11316      0,	// ssub_2_ssub_3_ssub_4_ssub_5
11317      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11318      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11319      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11320      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11321      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11322      67,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc
11323      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11324      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11325      0,	// ssub_6_ssub_7_dsub_5
11326      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11327      0,	// ssub_6_ssub_7_dsub_5_dsub_7
11328      0,	// ssub_6_ssub_7_ssub_8_ssub_9
11329      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11330      0,	// ssub_8_ssub_9_ssub_12_ssub_13
11331      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11332      0,	// dsub_5_dsub_7
11333      0,	// dsub_5_ssub_12_ssub_13_dsub_7
11334      0,	// dsub_5_ssub_12_ssub_13
11335      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11336    },
11337    {	// DQuadSpc_with_ssub_0
11338      68,	// dsub_0 -> DQuadSpc_with_ssub_0
11339      0,	// dsub_1
11340      68,	// dsub_2 -> DQuadSpc_with_ssub_0
11341      0,	// dsub_3
11342      68,	// dsub_4 -> DQuadSpc_with_ssub_0
11343      0,	// dsub_5
11344      0,	// dsub_6
11345      0,	// dsub_7
11346      0,	// gsub_0
11347      0,	// gsub_1
11348      0,	// qqsub_0
11349      0,	// qqsub_1
11350      0,	// qsub_0
11351      0,	// qsub_1
11352      0,	// qsub_2
11353      0,	// qsub_3
11354      68,	// ssub_0 -> DQuadSpc_with_ssub_0
11355      68,	// ssub_1 -> DQuadSpc_with_ssub_0
11356      0,	// ssub_2
11357      0,	// ssub_3
11358      69,	// ssub_4 -> DQuadSpc_with_ssub_4
11359      69,	// ssub_5 -> DQuadSpc_with_ssub_4
11360      0,	// ssub_6
11361      0,	// ssub_7
11362      70,	// ssub_8 -> DQuadSpc_with_ssub_8
11363      70,	// ssub_9 -> DQuadSpc_with_ssub_8
11364      0,	// ssub_10
11365      0,	// ssub_11
11366      0,	// ssub_12
11367      0,	// ssub_13
11368      0,	// dsub_7_then_ssub_0
11369      0,	// dsub_7_then_ssub_1
11370      68,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_ssub_0
11371      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11372      0,	// ssub_2_ssub_3_ssub_6_ssub_7
11373      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11374      0,	// ssub_2_ssub_3_ssub_4_ssub_5
11375      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11376      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11377      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11378      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11379      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11380      68,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_ssub_0
11381      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11382      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11383      0,	// ssub_6_ssub_7_dsub_5
11384      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11385      0,	// ssub_6_ssub_7_dsub_5_dsub_7
11386      0,	// ssub_6_ssub_7_ssub_8_ssub_9
11387      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11388      0,	// ssub_8_ssub_9_ssub_12_ssub_13
11389      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11390      0,	// dsub_5_dsub_7
11391      0,	// dsub_5_ssub_12_ssub_13_dsub_7
11392      0,	// dsub_5_ssub_12_ssub_13
11393      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11394    },
11395    {	// DQuadSpc_with_ssub_4
11396      69,	// dsub_0 -> DQuadSpc_with_ssub_4
11397      0,	// dsub_1
11398      69,	// dsub_2 -> DQuadSpc_with_ssub_4
11399      0,	// dsub_3
11400      69,	// dsub_4 -> DQuadSpc_with_ssub_4
11401      0,	// dsub_5
11402      0,	// dsub_6
11403      0,	// dsub_7
11404      0,	// gsub_0
11405      0,	// gsub_1
11406      0,	// qqsub_0
11407      0,	// qqsub_1
11408      0,	// qsub_0
11409      0,	// qsub_1
11410      0,	// qsub_2
11411      0,	// qsub_3
11412      69,	// ssub_0 -> DQuadSpc_with_ssub_4
11413      69,	// ssub_1 -> DQuadSpc_with_ssub_4
11414      0,	// ssub_2
11415      0,	// ssub_3
11416      69,	// ssub_4 -> DQuadSpc_with_ssub_4
11417      69,	// ssub_5 -> DQuadSpc_with_ssub_4
11418      0,	// ssub_6
11419      0,	// ssub_7
11420      70,	// ssub_8 -> DQuadSpc_with_ssub_8
11421      70,	// ssub_9 -> DQuadSpc_with_ssub_8
11422      0,	// ssub_10
11423      0,	// ssub_11
11424      0,	// ssub_12
11425      0,	// ssub_13
11426      0,	// dsub_7_then_ssub_0
11427      0,	// dsub_7_then_ssub_1
11428      69,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_ssub_4
11429      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11430      0,	// ssub_2_ssub_3_ssub_6_ssub_7
11431      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11432      0,	// ssub_2_ssub_3_ssub_4_ssub_5
11433      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11434      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11435      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11436      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11437      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11438      69,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_ssub_4
11439      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11440      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11441      0,	// ssub_6_ssub_7_dsub_5
11442      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11443      0,	// ssub_6_ssub_7_dsub_5_dsub_7
11444      0,	// ssub_6_ssub_7_ssub_8_ssub_9
11445      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11446      0,	// ssub_8_ssub_9_ssub_12_ssub_13
11447      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11448      0,	// dsub_5_dsub_7
11449      0,	// dsub_5_ssub_12_ssub_13_dsub_7
11450      0,	// dsub_5_ssub_12_ssub_13
11451      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11452    },
11453    {	// DQuadSpc_with_ssub_8
11454      70,	// dsub_0 -> DQuadSpc_with_ssub_8
11455      0,	// dsub_1
11456      70,	// dsub_2 -> DQuadSpc_with_ssub_8
11457      0,	// dsub_3
11458      70,	// dsub_4 -> DQuadSpc_with_ssub_8
11459      0,	// dsub_5
11460      0,	// dsub_6
11461      0,	// dsub_7
11462      0,	// gsub_0
11463      0,	// gsub_1
11464      0,	// qqsub_0
11465      0,	// qqsub_1
11466      0,	// qsub_0
11467      0,	// qsub_1
11468      0,	// qsub_2
11469      0,	// qsub_3
11470      70,	// ssub_0 -> DQuadSpc_with_ssub_8
11471      70,	// ssub_1 -> DQuadSpc_with_ssub_8
11472      0,	// ssub_2
11473      0,	// ssub_3
11474      70,	// ssub_4 -> DQuadSpc_with_ssub_8
11475      70,	// ssub_5 -> DQuadSpc_with_ssub_8
11476      0,	// ssub_6
11477      0,	// ssub_7
11478      70,	// ssub_8 -> DQuadSpc_with_ssub_8
11479      70,	// ssub_9 -> DQuadSpc_with_ssub_8
11480      0,	// ssub_10
11481      0,	// ssub_11
11482      0,	// ssub_12
11483      0,	// ssub_13
11484      0,	// dsub_7_then_ssub_0
11485      0,	// dsub_7_then_ssub_1
11486      70,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_ssub_8
11487      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11488      0,	// ssub_2_ssub_3_ssub_6_ssub_7
11489      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11490      0,	// ssub_2_ssub_3_ssub_4_ssub_5
11491      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11492      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11493      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11494      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11495      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11496      70,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_ssub_8
11497      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11498      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11499      0,	// ssub_6_ssub_7_dsub_5
11500      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11501      0,	// ssub_6_ssub_7_dsub_5_dsub_7
11502      0,	// ssub_6_ssub_7_ssub_8_ssub_9
11503      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11504      0,	// ssub_8_ssub_9_ssub_12_ssub_13
11505      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11506      0,	// dsub_5_dsub_7
11507      0,	// dsub_5_ssub_12_ssub_13_dsub_7
11508      0,	// dsub_5_ssub_12_ssub_13
11509      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11510    },
11511    {	// DQuadSpc_with_dsub_0_in_DPR_8
11512      71,	// dsub_0 -> DQuadSpc_with_dsub_0_in_DPR_8
11513      0,	// dsub_1
11514      71,	// dsub_2 -> DQuadSpc_with_dsub_0_in_DPR_8
11515      0,	// dsub_3
11516      71,	// dsub_4 -> DQuadSpc_with_dsub_0_in_DPR_8
11517      0,	// dsub_5
11518      0,	// dsub_6
11519      0,	// dsub_7
11520      0,	// gsub_0
11521      0,	// gsub_1
11522      0,	// qqsub_0
11523      0,	// qqsub_1
11524      0,	// qsub_0
11525      0,	// qsub_1
11526      0,	// qsub_2
11527      0,	// qsub_3
11528      71,	// ssub_0 -> DQuadSpc_with_dsub_0_in_DPR_8
11529      71,	// ssub_1 -> DQuadSpc_with_dsub_0_in_DPR_8
11530      0,	// ssub_2
11531      0,	// ssub_3
11532      71,	// ssub_4 -> DQuadSpc_with_dsub_0_in_DPR_8
11533      71,	// ssub_5 -> DQuadSpc_with_dsub_0_in_DPR_8
11534      0,	// ssub_6
11535      0,	// ssub_7
11536      71,	// ssub_8 -> DQuadSpc_with_dsub_0_in_DPR_8
11537      71,	// ssub_9 -> DQuadSpc_with_dsub_0_in_DPR_8
11538      0,	// ssub_10
11539      0,	// ssub_11
11540      0,	// ssub_12
11541      0,	// ssub_13
11542      0,	// dsub_7_then_ssub_0
11543      0,	// dsub_7_then_ssub_1
11544      71,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_dsub_0_in_DPR_8
11545      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11546      0,	// ssub_2_ssub_3_ssub_6_ssub_7
11547      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11548      0,	// ssub_2_ssub_3_ssub_4_ssub_5
11549      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11550      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11551      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11552      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11553      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11554      71,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_dsub_0_in_DPR_8
11555      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11556      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11557      0,	// ssub_6_ssub_7_dsub_5
11558      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11559      0,	// ssub_6_ssub_7_dsub_5_dsub_7
11560      0,	// ssub_6_ssub_7_ssub_8_ssub_9
11561      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11562      0,	// ssub_8_ssub_9_ssub_12_ssub_13
11563      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11564      0,	// dsub_5_dsub_7
11565      0,	// dsub_5_ssub_12_ssub_13_dsub_7
11566      0,	// dsub_5_ssub_12_ssub_13
11567      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11568    },
11569    {	// DQuadSpc_with_dsub_2_in_DPR_8
11570      72,	// dsub_0 -> DQuadSpc_with_dsub_2_in_DPR_8
11571      0,	// dsub_1
11572      72,	// dsub_2 -> DQuadSpc_with_dsub_2_in_DPR_8
11573      0,	// dsub_3
11574      72,	// dsub_4 -> DQuadSpc_with_dsub_2_in_DPR_8
11575      0,	// dsub_5
11576      0,	// dsub_6
11577      0,	// dsub_7
11578      0,	// gsub_0
11579      0,	// gsub_1
11580      0,	// qqsub_0
11581      0,	// qqsub_1
11582      0,	// qsub_0
11583      0,	// qsub_1
11584      0,	// qsub_2
11585      0,	// qsub_3
11586      72,	// ssub_0 -> DQuadSpc_with_dsub_2_in_DPR_8
11587      72,	// ssub_1 -> DQuadSpc_with_dsub_2_in_DPR_8
11588      0,	// ssub_2
11589      0,	// ssub_3
11590      72,	// ssub_4 -> DQuadSpc_with_dsub_2_in_DPR_8
11591      72,	// ssub_5 -> DQuadSpc_with_dsub_2_in_DPR_8
11592      0,	// ssub_6
11593      0,	// ssub_7
11594      72,	// ssub_8 -> DQuadSpc_with_dsub_2_in_DPR_8
11595      72,	// ssub_9 -> DQuadSpc_with_dsub_2_in_DPR_8
11596      0,	// ssub_10
11597      0,	// ssub_11
11598      0,	// ssub_12
11599      0,	// ssub_13
11600      0,	// dsub_7_then_ssub_0
11601      0,	// dsub_7_then_ssub_1
11602      72,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_dsub_2_in_DPR_8
11603      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11604      0,	// ssub_2_ssub_3_ssub_6_ssub_7
11605      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11606      0,	// ssub_2_ssub_3_ssub_4_ssub_5
11607      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11608      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11609      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11610      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11611      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11612      72,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_dsub_2_in_DPR_8
11613      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11614      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11615      0,	// ssub_6_ssub_7_dsub_5
11616      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11617      0,	// ssub_6_ssub_7_dsub_5_dsub_7
11618      0,	// ssub_6_ssub_7_ssub_8_ssub_9
11619      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11620      0,	// ssub_8_ssub_9_ssub_12_ssub_13
11621      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11622      0,	// dsub_5_dsub_7
11623      0,	// dsub_5_ssub_12_ssub_13_dsub_7
11624      0,	// dsub_5_ssub_12_ssub_13
11625      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11626    },
11627    {	// DQuadSpc_with_dsub_4_in_DPR_8
11628      73,	// dsub_0 -> DQuadSpc_with_dsub_4_in_DPR_8
11629      0,	// dsub_1
11630      73,	// dsub_2 -> DQuadSpc_with_dsub_4_in_DPR_8
11631      0,	// dsub_3
11632      73,	// dsub_4 -> DQuadSpc_with_dsub_4_in_DPR_8
11633      0,	// dsub_5
11634      0,	// dsub_6
11635      0,	// dsub_7
11636      0,	// gsub_0
11637      0,	// gsub_1
11638      0,	// qqsub_0
11639      0,	// qqsub_1
11640      0,	// qsub_0
11641      0,	// qsub_1
11642      0,	// qsub_2
11643      0,	// qsub_3
11644      73,	// ssub_0 -> DQuadSpc_with_dsub_4_in_DPR_8
11645      73,	// ssub_1 -> DQuadSpc_with_dsub_4_in_DPR_8
11646      0,	// ssub_2
11647      0,	// ssub_3
11648      73,	// ssub_4 -> DQuadSpc_with_dsub_4_in_DPR_8
11649      73,	// ssub_5 -> DQuadSpc_with_dsub_4_in_DPR_8
11650      0,	// ssub_6
11651      0,	// ssub_7
11652      73,	// ssub_8 -> DQuadSpc_with_dsub_4_in_DPR_8
11653      73,	// ssub_9 -> DQuadSpc_with_dsub_4_in_DPR_8
11654      0,	// ssub_10
11655      0,	// ssub_11
11656      0,	// ssub_12
11657      0,	// ssub_13
11658      0,	// dsub_7_then_ssub_0
11659      0,	// dsub_7_then_ssub_1
11660      73,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_dsub_4_in_DPR_8
11661      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
11662      0,	// ssub_2_ssub_3_ssub_6_ssub_7
11663      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
11664      0,	// ssub_2_ssub_3_ssub_4_ssub_5
11665      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11666      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11667      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11668      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11669      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11670      73,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_dsub_4_in_DPR_8
11671      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11672      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11673      0,	// ssub_6_ssub_7_dsub_5
11674      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11675      0,	// ssub_6_ssub_7_dsub_5_dsub_7
11676      0,	// ssub_6_ssub_7_ssub_8_ssub_9
11677      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11678      0,	// ssub_8_ssub_9_ssub_12_ssub_13
11679      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11680      0,	// dsub_5_dsub_7
11681      0,	// dsub_5_ssub_12_ssub_13_dsub_7
11682      0,	// dsub_5_ssub_12_ssub_13
11683      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11684    },
11685    {	// DQuad
11686      74,	// dsub_0 -> DQuad
11687      74,	// dsub_1 -> DQuad
11688      74,	// dsub_2 -> DQuad
11689      74,	// dsub_3 -> DQuad
11690      0,	// dsub_4
11691      0,	// dsub_5
11692      0,	// dsub_6
11693      0,	// dsub_7
11694      0,	// gsub_0
11695      0,	// gsub_1
11696      0,	// qqsub_0
11697      0,	// qqsub_1
11698      74,	// qsub_0 -> DQuad
11699      74,	// qsub_1 -> DQuad
11700      0,	// qsub_2
11701      0,	// qsub_3
11702      75,	// ssub_0 -> DQuad_with_ssub_0
11703      75,	// ssub_1 -> DQuad_with_ssub_0
11704      76,	// ssub_2 -> DQuad_with_ssub_2
11705      76,	// ssub_3 -> DQuad_with_ssub_2
11706      79,	// ssub_4 -> DQuad_with_ssub_4
11707      79,	// ssub_5 -> DQuad_with_ssub_4
11708      80,	// ssub_6 -> DQuad_with_ssub_6
11709      80,	// ssub_7 -> DQuad_with_ssub_6
11710      0,	// ssub_8
11711      0,	// ssub_9
11712      0,	// ssub_10
11713      0,	// ssub_11
11714      0,	// ssub_12
11715      0,	// ssub_13
11716      0,	// dsub_7_then_ssub_0
11717      0,	// dsub_7_then_ssub_1
11718      74,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad
11719      74,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad
11720      74,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad
11721      74,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad
11722      74,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad
11723      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11724      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11725      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11726      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11727      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11728      0,	// ssub_4_ssub_5_ssub_8_ssub_9
11729      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11730      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11731      0,	// ssub_6_ssub_7_dsub_5
11732      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11733      0,	// ssub_6_ssub_7_dsub_5_dsub_7
11734      0,	// ssub_6_ssub_7_ssub_8_ssub_9
11735      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11736      0,	// ssub_8_ssub_9_ssub_12_ssub_13
11737      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11738      0,	// dsub_5_dsub_7
11739      0,	// dsub_5_ssub_12_ssub_13_dsub_7
11740      0,	// dsub_5_ssub_12_ssub_13
11741      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11742    },
11743    {	// DQuad_with_ssub_0
11744      75,	// dsub_0 -> DQuad_with_ssub_0
11745      75,	// dsub_1 -> DQuad_with_ssub_0
11746      75,	// dsub_2 -> DQuad_with_ssub_0
11747      75,	// dsub_3 -> DQuad_with_ssub_0
11748      0,	// dsub_4
11749      0,	// dsub_5
11750      0,	// dsub_6
11751      0,	// dsub_7
11752      0,	// gsub_0
11753      0,	// gsub_1
11754      0,	// qqsub_0
11755      0,	// qqsub_1
11756      75,	// qsub_0 -> DQuad_with_ssub_0
11757      75,	// qsub_1 -> DQuad_with_ssub_0
11758      0,	// qsub_2
11759      0,	// qsub_3
11760      75,	// ssub_0 -> DQuad_with_ssub_0
11761      75,	// ssub_1 -> DQuad_with_ssub_0
11762      76,	// ssub_2 -> DQuad_with_ssub_2
11763      76,	// ssub_3 -> DQuad_with_ssub_2
11764      79,	// ssub_4 -> DQuad_with_ssub_4
11765      79,	// ssub_5 -> DQuad_with_ssub_4
11766      80,	// ssub_6 -> DQuad_with_ssub_6
11767      80,	// ssub_7 -> DQuad_with_ssub_6
11768      0,	// ssub_8
11769      0,	// ssub_9
11770      0,	// ssub_10
11771      0,	// ssub_11
11772      0,	// ssub_12
11773      0,	// ssub_13
11774      0,	// dsub_7_then_ssub_0
11775      0,	// dsub_7_then_ssub_1
11776      75,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_0
11777      75,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_0
11778      75,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_0
11779      75,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_0
11780      75,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_0
11781      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11782      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11783      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11784      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11785      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11786      0,	// ssub_4_ssub_5_ssub_8_ssub_9
11787      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11788      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11789      0,	// ssub_6_ssub_7_dsub_5
11790      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11791      0,	// ssub_6_ssub_7_dsub_5_dsub_7
11792      0,	// ssub_6_ssub_7_ssub_8_ssub_9
11793      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11794      0,	// ssub_8_ssub_9_ssub_12_ssub_13
11795      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11796      0,	// dsub_5_dsub_7
11797      0,	// dsub_5_ssub_12_ssub_13_dsub_7
11798      0,	// dsub_5_ssub_12_ssub_13
11799      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11800    },
11801    {	// DQuad_with_ssub_2
11802      76,	// dsub_0 -> DQuad_with_ssub_2
11803      76,	// dsub_1 -> DQuad_with_ssub_2
11804      76,	// dsub_2 -> DQuad_with_ssub_2
11805      76,	// dsub_3 -> DQuad_with_ssub_2
11806      0,	// dsub_4
11807      0,	// dsub_5
11808      0,	// dsub_6
11809      0,	// dsub_7
11810      0,	// gsub_0
11811      0,	// gsub_1
11812      0,	// qqsub_0
11813      0,	// qqsub_1
11814      76,	// qsub_0 -> DQuad_with_ssub_2
11815      76,	// qsub_1 -> DQuad_with_ssub_2
11816      0,	// qsub_2
11817      0,	// qsub_3
11818      76,	// ssub_0 -> DQuad_with_ssub_2
11819      76,	// ssub_1 -> DQuad_with_ssub_2
11820      76,	// ssub_2 -> DQuad_with_ssub_2
11821      76,	// ssub_3 -> DQuad_with_ssub_2
11822      79,	// ssub_4 -> DQuad_with_ssub_4
11823      79,	// ssub_5 -> DQuad_with_ssub_4
11824      80,	// ssub_6 -> DQuad_with_ssub_6
11825      80,	// ssub_7 -> DQuad_with_ssub_6
11826      0,	// ssub_8
11827      0,	// ssub_9
11828      0,	// ssub_10
11829      0,	// ssub_11
11830      0,	// ssub_12
11831      0,	// ssub_13
11832      0,	// dsub_7_then_ssub_0
11833      0,	// dsub_7_then_ssub_1
11834      76,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_2
11835      76,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2
11836      76,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_2
11837      76,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_2
11838      76,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2
11839      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11840      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11841      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11842      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11843      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11844      0,	// ssub_4_ssub_5_ssub_8_ssub_9
11845      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11846      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11847      0,	// ssub_6_ssub_7_dsub_5
11848      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11849      0,	// ssub_6_ssub_7_dsub_5_dsub_7
11850      0,	// ssub_6_ssub_7_ssub_8_ssub_9
11851      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11852      0,	// ssub_8_ssub_9_ssub_12_ssub_13
11853      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11854      0,	// dsub_5_dsub_7
11855      0,	// dsub_5_ssub_12_ssub_13_dsub_7
11856      0,	// dsub_5_ssub_12_ssub_13
11857      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11858    },
11859    {	// QQPR
11860      77,	// dsub_0 -> QQPR
11861      77,	// dsub_1 -> QQPR
11862      77,	// dsub_2 -> QQPR
11863      77,	// dsub_3 -> QQPR
11864      0,	// dsub_4
11865      0,	// dsub_5
11866      0,	// dsub_6
11867      0,	// dsub_7
11868      0,	// gsub_0
11869      0,	// gsub_1
11870      0,	// qqsub_0
11871      0,	// qqsub_1
11872      77,	// qsub_0 -> QQPR
11873      77,	// qsub_1 -> QQPR
11874      0,	// qsub_2
11875      0,	// qsub_3
11876      82,	// ssub_0 -> DQuad_with_qsub_0_in_QPR_VFP2
11877      82,	// ssub_1 -> DQuad_with_qsub_0_in_QPR_VFP2
11878      82,	// ssub_2 -> DQuad_with_qsub_0_in_QPR_VFP2
11879      82,	// ssub_3 -> DQuad_with_qsub_0_in_QPR_VFP2
11880      85,	// ssub_4 -> DQuad_with_qsub_1_in_QPR_VFP2
11881      85,	// ssub_5 -> DQuad_with_qsub_1_in_QPR_VFP2
11882      85,	// ssub_6 -> DQuad_with_qsub_1_in_QPR_VFP2
11883      85,	// ssub_7 -> DQuad_with_qsub_1_in_QPR_VFP2
11884      0,	// ssub_8
11885      0,	// ssub_9
11886      0,	// ssub_10
11887      0,	// ssub_11
11888      0,	// ssub_12
11889      0,	// ssub_13
11890      0,	// dsub_7_then_ssub_0
11891      0,	// dsub_7_then_ssub_1
11892      77,	// ssub_0_ssub_1_ssub_4_ssub_5 -> QQPR
11893      77,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQPR
11894      77,	// ssub_2_ssub_3_ssub_6_ssub_7 -> QQPR
11895      77,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQPR
11896      77,	// ssub_2_ssub_3_ssub_4_ssub_5 -> QQPR
11897      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11898      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11899      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11900      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11901      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11902      0,	// ssub_4_ssub_5_ssub_8_ssub_9
11903      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11904      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11905      0,	// ssub_6_ssub_7_dsub_5
11906      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11907      0,	// ssub_6_ssub_7_dsub_5_dsub_7
11908      0,	// ssub_6_ssub_7_ssub_8_ssub_9
11909      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11910      0,	// ssub_8_ssub_9_ssub_12_ssub_13
11911      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11912      0,	// dsub_5_dsub_7
11913      0,	// dsub_5_ssub_12_ssub_13_dsub_7
11914      0,	// dsub_5_ssub_12_ssub_13
11915      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11916    },
11917    {	// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11918      78,	// dsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11919      78,	// dsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11920      78,	// dsub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11921      78,	// dsub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11922      0,	// dsub_4
11923      0,	// dsub_5
11924      0,	// dsub_6
11925      0,	// dsub_7
11926      0,	// gsub_0
11927      0,	// gsub_1
11928      0,	// qqsub_0
11929      0,	// qqsub_1
11930      78,	// qsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11931      78,	// qsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11932      0,	// qsub_2
11933      0,	// qsub_3
11934      83,	// ssub_0 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11935      83,	// ssub_1 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11936      86,	// ssub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
11937      86,	// ssub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
11938      86,	// ssub_4 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
11939      86,	// ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
11940      88,	// ssub_6 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11941      88,	// ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11942      0,	// ssub_8
11943      0,	// ssub_9
11944      0,	// ssub_10
11945      0,	// ssub_11
11946      0,	// ssub_12
11947      0,	// ssub_13
11948      0,	// dsub_7_then_ssub_0
11949      0,	// dsub_7_then_ssub_1
11950      78,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11951      78,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11952      78,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11953      78,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11954      78,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
11955      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
11956      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11957      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
11958      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
11959      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11960      0,	// ssub_4_ssub_5_ssub_8_ssub_9
11961      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
11962      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
11963      0,	// ssub_6_ssub_7_dsub_5
11964      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
11965      0,	// ssub_6_ssub_7_dsub_5_dsub_7
11966      0,	// ssub_6_ssub_7_ssub_8_ssub_9
11967      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11968      0,	// ssub_8_ssub_9_ssub_12_ssub_13
11969      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
11970      0,	// dsub_5_dsub_7
11971      0,	// dsub_5_ssub_12_ssub_13_dsub_7
11972      0,	// dsub_5_ssub_12_ssub_13
11973      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
11974    },
11975    {	// DQuad_with_ssub_4
11976      79,	// dsub_0 -> DQuad_with_ssub_4
11977      79,	// dsub_1 -> DQuad_with_ssub_4
11978      79,	// dsub_2 -> DQuad_with_ssub_4
11979      79,	// dsub_3 -> DQuad_with_ssub_4
11980      0,	// dsub_4
11981      0,	// dsub_5
11982      0,	// dsub_6
11983      0,	// dsub_7
11984      0,	// gsub_0
11985      0,	// gsub_1
11986      0,	// qqsub_0
11987      0,	// qqsub_1
11988      79,	// qsub_0 -> DQuad_with_ssub_4
11989      79,	// qsub_1 -> DQuad_with_ssub_4
11990      0,	// qsub_2
11991      0,	// qsub_3
11992      79,	// ssub_0 -> DQuad_with_ssub_4
11993      79,	// ssub_1 -> DQuad_with_ssub_4
11994      79,	// ssub_2 -> DQuad_with_ssub_4
11995      79,	// ssub_3 -> DQuad_with_ssub_4
11996      79,	// ssub_4 -> DQuad_with_ssub_4
11997      79,	// ssub_5 -> DQuad_with_ssub_4
11998      80,	// ssub_6 -> DQuad_with_ssub_6
11999      80,	// ssub_7 -> DQuad_with_ssub_6
12000      0,	// ssub_8
12001      0,	// ssub_9
12002      0,	// ssub_10
12003      0,	// ssub_11
12004      0,	// ssub_12
12005      0,	// ssub_13
12006      0,	// dsub_7_then_ssub_0
12007      0,	// dsub_7_then_ssub_1
12008      79,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_4
12009      79,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_4
12010      79,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_4
12011      79,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_4
12012      79,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_4
12013      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12014      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12015      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12016      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12017      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12018      0,	// ssub_4_ssub_5_ssub_8_ssub_9
12019      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12020      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12021      0,	// ssub_6_ssub_7_dsub_5
12022      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12023      0,	// ssub_6_ssub_7_dsub_5_dsub_7
12024      0,	// ssub_6_ssub_7_ssub_8_ssub_9
12025      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12026      0,	// ssub_8_ssub_9_ssub_12_ssub_13
12027      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12028      0,	// dsub_5_dsub_7
12029      0,	// dsub_5_ssub_12_ssub_13_dsub_7
12030      0,	// dsub_5_ssub_12_ssub_13
12031      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12032    },
12033    {	// DQuad_with_ssub_6
12034      80,	// dsub_0 -> DQuad_with_ssub_6
12035      80,	// dsub_1 -> DQuad_with_ssub_6
12036      80,	// dsub_2 -> DQuad_with_ssub_6
12037      80,	// dsub_3 -> DQuad_with_ssub_6
12038      0,	// dsub_4
12039      0,	// dsub_5
12040      0,	// dsub_6
12041      0,	// dsub_7
12042      0,	// gsub_0
12043      0,	// gsub_1
12044      0,	// qqsub_0
12045      0,	// qqsub_1
12046      80,	// qsub_0 -> DQuad_with_ssub_6
12047      80,	// qsub_1 -> DQuad_with_ssub_6
12048      0,	// qsub_2
12049      0,	// qsub_3
12050      80,	// ssub_0 -> DQuad_with_ssub_6
12051      80,	// ssub_1 -> DQuad_with_ssub_6
12052      80,	// ssub_2 -> DQuad_with_ssub_6
12053      80,	// ssub_3 -> DQuad_with_ssub_6
12054      80,	// ssub_4 -> DQuad_with_ssub_6
12055      80,	// ssub_5 -> DQuad_with_ssub_6
12056      80,	// ssub_6 -> DQuad_with_ssub_6
12057      80,	// ssub_7 -> DQuad_with_ssub_6
12058      0,	// ssub_8
12059      0,	// ssub_9
12060      0,	// ssub_10
12061      0,	// ssub_11
12062      0,	// ssub_12
12063      0,	// ssub_13
12064      0,	// dsub_7_then_ssub_0
12065      0,	// dsub_7_then_ssub_1
12066      80,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_6
12067      80,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_6
12068      80,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_6
12069      80,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_6
12070      80,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_6
12071      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12072      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12073      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12074      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12075      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12076      0,	// ssub_4_ssub_5_ssub_8_ssub_9
12077      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12078      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12079      0,	// ssub_6_ssub_7_dsub_5
12080      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12081      0,	// ssub_6_ssub_7_dsub_5_dsub_7
12082      0,	// ssub_6_ssub_7_ssub_8_ssub_9
12083      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12084      0,	// ssub_8_ssub_9_ssub_12_ssub_13
12085      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12086      0,	// dsub_5_dsub_7
12087      0,	// dsub_5_ssub_12_ssub_13_dsub_7
12088      0,	// dsub_5_ssub_12_ssub_13
12089      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12090    },
12091    {	// DQuad_with_dsub_0_in_DPR_8
12092      81,	// dsub_0 -> DQuad_with_dsub_0_in_DPR_8
12093      81,	// dsub_1 -> DQuad_with_dsub_0_in_DPR_8
12094      81,	// dsub_2 -> DQuad_with_dsub_0_in_DPR_8
12095      81,	// dsub_3 -> DQuad_with_dsub_0_in_DPR_8
12096      0,	// dsub_4
12097      0,	// dsub_5
12098      0,	// dsub_6
12099      0,	// dsub_7
12100      0,	// gsub_0
12101      0,	// gsub_1
12102      0,	// qqsub_0
12103      0,	// qqsub_1
12104      81,	// qsub_0 -> DQuad_with_dsub_0_in_DPR_8
12105      81,	// qsub_1 -> DQuad_with_dsub_0_in_DPR_8
12106      0,	// qsub_2
12107      0,	// qsub_3
12108      81,	// ssub_0 -> DQuad_with_dsub_0_in_DPR_8
12109      81,	// ssub_1 -> DQuad_with_dsub_0_in_DPR_8
12110      81,	// ssub_2 -> DQuad_with_dsub_0_in_DPR_8
12111      81,	// ssub_3 -> DQuad_with_dsub_0_in_DPR_8
12112      81,	// ssub_4 -> DQuad_with_dsub_0_in_DPR_8
12113      81,	// ssub_5 -> DQuad_with_dsub_0_in_DPR_8
12114      81,	// ssub_6 -> DQuad_with_dsub_0_in_DPR_8
12115      81,	// ssub_7 -> DQuad_with_dsub_0_in_DPR_8
12116      0,	// ssub_8
12117      0,	// ssub_9
12118      0,	// ssub_10
12119      0,	// ssub_11
12120      0,	// ssub_12
12121      0,	// ssub_13
12122      0,	// dsub_7_then_ssub_0
12123      0,	// dsub_7_then_ssub_1
12124      81,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8
12125      81,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8
12126      81,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_0_in_DPR_8
12127      81,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_0_in_DPR_8
12128      81,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8
12129      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12130      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12131      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12132      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12133      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12134      0,	// ssub_4_ssub_5_ssub_8_ssub_9
12135      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12136      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12137      0,	// ssub_6_ssub_7_dsub_5
12138      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12139      0,	// ssub_6_ssub_7_dsub_5_dsub_7
12140      0,	// ssub_6_ssub_7_ssub_8_ssub_9
12141      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12142      0,	// ssub_8_ssub_9_ssub_12_ssub_13
12143      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12144      0,	// dsub_5_dsub_7
12145      0,	// dsub_5_ssub_12_ssub_13_dsub_7
12146      0,	// dsub_5_ssub_12_ssub_13
12147      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12148    },
12149    {	// DQuad_with_qsub_0_in_QPR_VFP2
12150      82,	// dsub_0 -> DQuad_with_qsub_0_in_QPR_VFP2
12151      82,	// dsub_1 -> DQuad_with_qsub_0_in_QPR_VFP2
12152      82,	// dsub_2 -> DQuad_with_qsub_0_in_QPR_VFP2
12153      82,	// dsub_3 -> DQuad_with_qsub_0_in_QPR_VFP2
12154      0,	// dsub_4
12155      0,	// dsub_5
12156      0,	// dsub_6
12157      0,	// dsub_7
12158      0,	// gsub_0
12159      0,	// gsub_1
12160      0,	// qqsub_0
12161      0,	// qqsub_1
12162      82,	// qsub_0 -> DQuad_with_qsub_0_in_QPR_VFP2
12163      82,	// qsub_1 -> DQuad_with_qsub_0_in_QPR_VFP2
12164      0,	// qsub_2
12165      0,	// qsub_3
12166      82,	// ssub_0 -> DQuad_with_qsub_0_in_QPR_VFP2
12167      82,	// ssub_1 -> DQuad_with_qsub_0_in_QPR_VFP2
12168      82,	// ssub_2 -> DQuad_with_qsub_0_in_QPR_VFP2
12169      82,	// ssub_3 -> DQuad_with_qsub_0_in_QPR_VFP2
12170      85,	// ssub_4 -> DQuad_with_qsub_1_in_QPR_VFP2
12171      85,	// ssub_5 -> DQuad_with_qsub_1_in_QPR_VFP2
12172      85,	// ssub_6 -> DQuad_with_qsub_1_in_QPR_VFP2
12173      85,	// ssub_7 -> DQuad_with_qsub_1_in_QPR_VFP2
12174      0,	// ssub_8
12175      0,	// ssub_9
12176      0,	// ssub_10
12177      0,	// ssub_11
12178      0,	// ssub_12
12179      0,	// ssub_13
12180      0,	// dsub_7_then_ssub_0
12181      0,	// dsub_7_then_ssub_1
12182      82,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_VFP2
12183      82,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_VFP2
12184      82,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_qsub_0_in_QPR_VFP2
12185      82,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_qsub_0_in_QPR_VFP2
12186      82,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_VFP2
12187      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12188      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12189      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12190      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12191      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12192      0,	// ssub_4_ssub_5_ssub_8_ssub_9
12193      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12194      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12195      0,	// ssub_6_ssub_7_dsub_5
12196      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12197      0,	// ssub_6_ssub_7_dsub_5_dsub_7
12198      0,	// ssub_6_ssub_7_ssub_8_ssub_9
12199      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12200      0,	// ssub_8_ssub_9_ssub_12_ssub_13
12201      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12202      0,	// dsub_5_dsub_7
12203      0,	// dsub_5_ssub_12_ssub_13_dsub_7
12204      0,	// dsub_5_ssub_12_ssub_13
12205      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12206    },
12207    {	// DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12208      83,	// dsub_0 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12209      83,	// dsub_1 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12210      83,	// dsub_2 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12211      83,	// dsub_3 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12212      0,	// dsub_4
12213      0,	// dsub_5
12214      0,	// dsub_6
12215      0,	// dsub_7
12216      0,	// gsub_0
12217      0,	// gsub_1
12218      0,	// qqsub_0
12219      0,	// qqsub_1
12220      83,	// qsub_0 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12221      83,	// qsub_1 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12222      0,	// qsub_2
12223      0,	// qsub_3
12224      83,	// ssub_0 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12225      83,	// ssub_1 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12226      86,	// ssub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12227      86,	// ssub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12228      86,	// ssub_4 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12229      86,	// ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12230      88,	// ssub_6 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12231      88,	// ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12232      0,	// ssub_8
12233      0,	// ssub_9
12234      0,	// ssub_10
12235      0,	// ssub_11
12236      0,	// ssub_12
12237      0,	// ssub_13
12238      0,	// dsub_7_then_ssub_0
12239      0,	// dsub_7_then_ssub_1
12240      83,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12241      83,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12242      83,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12243      83,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12244      83,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12245      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12246      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12247      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12248      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12249      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12250      0,	// ssub_4_ssub_5_ssub_8_ssub_9
12251      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12252      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12253      0,	// ssub_6_ssub_7_dsub_5
12254      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12255      0,	// ssub_6_ssub_7_dsub_5_dsub_7
12256      0,	// ssub_6_ssub_7_ssub_8_ssub_9
12257      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12258      0,	// ssub_8_ssub_9_ssub_12_ssub_13
12259      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12260      0,	// dsub_5_dsub_7
12261      0,	// dsub_5_ssub_12_ssub_13_dsub_7
12262      0,	// dsub_5_ssub_12_ssub_13
12263      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12264    },
12265    {	// DQuad_with_dsub_1_in_DPR_8
12266      84,	// dsub_0 -> DQuad_with_dsub_1_in_DPR_8
12267      84,	// dsub_1 -> DQuad_with_dsub_1_in_DPR_8
12268      84,	// dsub_2 -> DQuad_with_dsub_1_in_DPR_8
12269      84,	// dsub_3 -> DQuad_with_dsub_1_in_DPR_8
12270      0,	// dsub_4
12271      0,	// dsub_5
12272      0,	// dsub_6
12273      0,	// dsub_7
12274      0,	// gsub_0
12275      0,	// gsub_1
12276      0,	// qqsub_0
12277      0,	// qqsub_1
12278      84,	// qsub_0 -> DQuad_with_dsub_1_in_DPR_8
12279      84,	// qsub_1 -> DQuad_with_dsub_1_in_DPR_8
12280      0,	// qsub_2
12281      0,	// qsub_3
12282      84,	// ssub_0 -> DQuad_with_dsub_1_in_DPR_8
12283      84,	// ssub_1 -> DQuad_with_dsub_1_in_DPR_8
12284      84,	// ssub_2 -> DQuad_with_dsub_1_in_DPR_8
12285      84,	// ssub_3 -> DQuad_with_dsub_1_in_DPR_8
12286      84,	// ssub_4 -> DQuad_with_dsub_1_in_DPR_8
12287      84,	// ssub_5 -> DQuad_with_dsub_1_in_DPR_8
12288      84,	// ssub_6 -> DQuad_with_dsub_1_in_DPR_8
12289      84,	// ssub_7 -> DQuad_with_dsub_1_in_DPR_8
12290      0,	// ssub_8
12291      0,	// ssub_9
12292      0,	// ssub_10
12293      0,	// ssub_11
12294      0,	// ssub_12
12295      0,	// ssub_13
12296      0,	// dsub_7_then_ssub_0
12297      0,	// dsub_7_then_ssub_1
12298      84,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_1_in_DPR_8
12299      84,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_1_in_DPR_8
12300      84,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_1_in_DPR_8
12301      84,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_1_in_DPR_8
12302      84,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_1_in_DPR_8
12303      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12304      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12305      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12306      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12307      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12308      0,	// ssub_4_ssub_5_ssub_8_ssub_9
12309      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12310      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12311      0,	// ssub_6_ssub_7_dsub_5
12312      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12313      0,	// ssub_6_ssub_7_dsub_5_dsub_7
12314      0,	// ssub_6_ssub_7_ssub_8_ssub_9
12315      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12316      0,	// ssub_8_ssub_9_ssub_12_ssub_13
12317      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12318      0,	// dsub_5_dsub_7
12319      0,	// dsub_5_ssub_12_ssub_13_dsub_7
12320      0,	// dsub_5_ssub_12_ssub_13
12321      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12322    },
12323    {	// DQuad_with_qsub_1_in_QPR_VFP2
12324      85,	// dsub_0 -> DQuad_with_qsub_1_in_QPR_VFP2
12325      85,	// dsub_1 -> DQuad_with_qsub_1_in_QPR_VFP2
12326      85,	// dsub_2 -> DQuad_with_qsub_1_in_QPR_VFP2
12327      85,	// dsub_3 -> DQuad_with_qsub_1_in_QPR_VFP2
12328      0,	// dsub_4
12329      0,	// dsub_5
12330      0,	// dsub_6
12331      0,	// dsub_7
12332      0,	// gsub_0
12333      0,	// gsub_1
12334      0,	// qqsub_0
12335      0,	// qqsub_1
12336      85,	// qsub_0 -> DQuad_with_qsub_1_in_QPR_VFP2
12337      85,	// qsub_1 -> DQuad_with_qsub_1_in_QPR_VFP2
12338      0,	// qsub_2
12339      0,	// qsub_3
12340      85,	// ssub_0 -> DQuad_with_qsub_1_in_QPR_VFP2
12341      85,	// ssub_1 -> DQuad_with_qsub_1_in_QPR_VFP2
12342      85,	// ssub_2 -> DQuad_with_qsub_1_in_QPR_VFP2
12343      85,	// ssub_3 -> DQuad_with_qsub_1_in_QPR_VFP2
12344      85,	// ssub_4 -> DQuad_with_qsub_1_in_QPR_VFP2
12345      85,	// ssub_5 -> DQuad_with_qsub_1_in_QPR_VFP2
12346      85,	// ssub_6 -> DQuad_with_qsub_1_in_QPR_VFP2
12347      85,	// ssub_7 -> DQuad_with_qsub_1_in_QPR_VFP2
12348      0,	// ssub_8
12349      0,	// ssub_9
12350      0,	// ssub_10
12351      0,	// ssub_11
12352      0,	// ssub_12
12353      0,	// ssub_13
12354      0,	// dsub_7_then_ssub_0
12355      0,	// dsub_7_then_ssub_1
12356      85,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_VFP2
12357      85,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_VFP2
12358      85,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_qsub_1_in_QPR_VFP2
12359      85,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_qsub_1_in_QPR_VFP2
12360      85,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_VFP2
12361      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12362      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12363      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12364      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12365      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12366      0,	// ssub_4_ssub_5_ssub_8_ssub_9
12367      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12368      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12369      0,	// ssub_6_ssub_7_dsub_5
12370      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12371      0,	// ssub_6_ssub_7_dsub_5_dsub_7
12372      0,	// ssub_6_ssub_7_ssub_8_ssub_9
12373      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12374      0,	// ssub_8_ssub_9_ssub_12_ssub_13
12375      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12376      0,	// dsub_5_dsub_7
12377      0,	// dsub_5_ssub_12_ssub_13_dsub_7
12378      0,	// dsub_5_ssub_12_ssub_13
12379      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12380    },
12381    {	// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12382      86,	// dsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12383      86,	// dsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12384      86,	// dsub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12385      86,	// dsub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12386      0,	// dsub_4
12387      0,	// dsub_5
12388      0,	// dsub_6
12389      0,	// dsub_7
12390      0,	// gsub_0
12391      0,	// gsub_1
12392      0,	// qqsub_0
12393      0,	// qqsub_1
12394      86,	// qsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12395      86,	// qsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12396      0,	// qsub_2
12397      0,	// qsub_3
12398      86,	// ssub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12399      86,	// ssub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12400      86,	// ssub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12401      86,	// ssub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12402      86,	// ssub_4 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12403      86,	// ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12404      88,	// ssub_6 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12405      88,	// ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12406      0,	// ssub_8
12407      0,	// ssub_9
12408      0,	// ssub_10
12409      0,	// ssub_11
12410      0,	// ssub_12
12411      0,	// ssub_13
12412      0,	// dsub_7_then_ssub_0
12413      0,	// dsub_7_then_ssub_1
12414      86,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12415      86,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12416      86,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12417      86,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12418      86,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
12419      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12420      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12421      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12422      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12423      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12424      0,	// ssub_4_ssub_5_ssub_8_ssub_9
12425      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12426      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12427      0,	// ssub_6_ssub_7_dsub_5
12428      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12429      0,	// ssub_6_ssub_7_dsub_5_dsub_7
12430      0,	// ssub_6_ssub_7_ssub_8_ssub_9
12431      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12432      0,	// ssub_8_ssub_9_ssub_12_ssub_13
12433      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12434      0,	// dsub_5_dsub_7
12435      0,	// dsub_5_ssub_12_ssub_13_dsub_7
12436      0,	// dsub_5_ssub_12_ssub_13
12437      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12438    },
12439    {	// DQuad_with_dsub_2_in_DPR_8
12440      87,	// dsub_0 -> DQuad_with_dsub_2_in_DPR_8
12441      87,	// dsub_1 -> DQuad_with_dsub_2_in_DPR_8
12442      87,	// dsub_2 -> DQuad_with_dsub_2_in_DPR_8
12443      87,	// dsub_3 -> DQuad_with_dsub_2_in_DPR_8
12444      0,	// dsub_4
12445      0,	// dsub_5
12446      0,	// dsub_6
12447      0,	// dsub_7
12448      0,	// gsub_0
12449      0,	// gsub_1
12450      0,	// qqsub_0
12451      0,	// qqsub_1
12452      87,	// qsub_0 -> DQuad_with_dsub_2_in_DPR_8
12453      87,	// qsub_1 -> DQuad_with_dsub_2_in_DPR_8
12454      0,	// qsub_2
12455      0,	// qsub_3
12456      87,	// ssub_0 -> DQuad_with_dsub_2_in_DPR_8
12457      87,	// ssub_1 -> DQuad_with_dsub_2_in_DPR_8
12458      87,	// ssub_2 -> DQuad_with_dsub_2_in_DPR_8
12459      87,	// ssub_3 -> DQuad_with_dsub_2_in_DPR_8
12460      87,	// ssub_4 -> DQuad_with_dsub_2_in_DPR_8
12461      87,	// ssub_5 -> DQuad_with_dsub_2_in_DPR_8
12462      87,	// ssub_6 -> DQuad_with_dsub_2_in_DPR_8
12463      87,	// ssub_7 -> DQuad_with_dsub_2_in_DPR_8
12464      0,	// ssub_8
12465      0,	// ssub_9
12466      0,	// ssub_10
12467      0,	// ssub_11
12468      0,	// ssub_12
12469      0,	// ssub_13
12470      0,	// dsub_7_then_ssub_0
12471      0,	// dsub_7_then_ssub_1
12472      87,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_2_in_DPR_8
12473      87,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_2_in_DPR_8
12474      87,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_2_in_DPR_8
12475      87,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_2_in_DPR_8
12476      87,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_2_in_DPR_8
12477      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12478      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12479      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12480      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12481      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12482      0,	// ssub_4_ssub_5_ssub_8_ssub_9
12483      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12484      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12485      0,	// ssub_6_ssub_7_dsub_5
12486      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12487      0,	// ssub_6_ssub_7_dsub_5_dsub_7
12488      0,	// ssub_6_ssub_7_ssub_8_ssub_9
12489      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12490      0,	// ssub_8_ssub_9_ssub_12_ssub_13
12491      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12492      0,	// dsub_5_dsub_7
12493      0,	// dsub_5_ssub_12_ssub_13_dsub_7
12494      0,	// dsub_5_ssub_12_ssub_13
12495      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12496    },
12497    {	// DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12498      88,	// dsub_0 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12499      88,	// dsub_1 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12500      88,	// dsub_2 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12501      88,	// dsub_3 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12502      0,	// dsub_4
12503      0,	// dsub_5
12504      0,	// dsub_6
12505      0,	// dsub_7
12506      0,	// gsub_0
12507      0,	// gsub_1
12508      0,	// qqsub_0
12509      0,	// qqsub_1
12510      88,	// qsub_0 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12511      88,	// qsub_1 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12512      0,	// qsub_2
12513      0,	// qsub_3
12514      88,	// ssub_0 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12515      88,	// ssub_1 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12516      88,	// ssub_2 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12517      88,	// ssub_3 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12518      88,	// ssub_4 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12519      88,	// ssub_5 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12520      88,	// ssub_6 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12521      88,	// ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12522      0,	// ssub_8
12523      0,	// ssub_9
12524      0,	// ssub_10
12525      0,	// ssub_11
12526      0,	// ssub_12
12527      0,	// ssub_13
12528      0,	// dsub_7_then_ssub_0
12529      0,	// dsub_7_then_ssub_1
12530      88,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12531      88,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12532      88,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12533      88,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12534      88,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12535      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12536      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12537      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12538      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12539      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12540      0,	// ssub_4_ssub_5_ssub_8_ssub_9
12541      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12542      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12543      0,	// ssub_6_ssub_7_dsub_5
12544      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12545      0,	// ssub_6_ssub_7_dsub_5_dsub_7
12546      0,	// ssub_6_ssub_7_ssub_8_ssub_9
12547      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12548      0,	// ssub_8_ssub_9_ssub_12_ssub_13
12549      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12550      0,	// dsub_5_dsub_7
12551      0,	// dsub_5_ssub_12_ssub_13_dsub_7
12552      0,	// dsub_5_ssub_12_ssub_13
12553      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12554    },
12555    {	// DQuad_with_dsub_3_in_DPR_8
12556      89,	// dsub_0 -> DQuad_with_dsub_3_in_DPR_8
12557      89,	// dsub_1 -> DQuad_with_dsub_3_in_DPR_8
12558      89,	// dsub_2 -> DQuad_with_dsub_3_in_DPR_8
12559      89,	// dsub_3 -> DQuad_with_dsub_3_in_DPR_8
12560      0,	// dsub_4
12561      0,	// dsub_5
12562      0,	// dsub_6
12563      0,	// dsub_7
12564      0,	// gsub_0
12565      0,	// gsub_1
12566      0,	// qqsub_0
12567      0,	// qqsub_1
12568      89,	// qsub_0 -> DQuad_with_dsub_3_in_DPR_8
12569      89,	// qsub_1 -> DQuad_with_dsub_3_in_DPR_8
12570      0,	// qsub_2
12571      0,	// qsub_3
12572      89,	// ssub_0 -> DQuad_with_dsub_3_in_DPR_8
12573      89,	// ssub_1 -> DQuad_with_dsub_3_in_DPR_8
12574      89,	// ssub_2 -> DQuad_with_dsub_3_in_DPR_8
12575      89,	// ssub_3 -> DQuad_with_dsub_3_in_DPR_8
12576      89,	// ssub_4 -> DQuad_with_dsub_3_in_DPR_8
12577      89,	// ssub_5 -> DQuad_with_dsub_3_in_DPR_8
12578      89,	// ssub_6 -> DQuad_with_dsub_3_in_DPR_8
12579      89,	// ssub_7 -> DQuad_with_dsub_3_in_DPR_8
12580      0,	// ssub_8
12581      0,	// ssub_9
12582      0,	// ssub_10
12583      0,	// ssub_11
12584      0,	// ssub_12
12585      0,	// ssub_13
12586      0,	// dsub_7_then_ssub_0
12587      0,	// dsub_7_then_ssub_1
12588      89,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8
12589      89,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8
12590      89,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_3_in_DPR_8
12591      89,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_3_in_DPR_8
12592      89,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8
12593      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12594      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12595      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12596      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12597      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12598      0,	// ssub_4_ssub_5_ssub_8_ssub_9
12599      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12600      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12601      0,	// ssub_6_ssub_7_dsub_5
12602      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12603      0,	// ssub_6_ssub_7_dsub_5_dsub_7
12604      0,	// ssub_6_ssub_7_ssub_8_ssub_9
12605      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12606      0,	// ssub_8_ssub_9_ssub_12_ssub_13
12607      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12608      0,	// dsub_5_dsub_7
12609      0,	// dsub_5_ssub_12_ssub_13_dsub_7
12610      0,	// dsub_5_ssub_12_ssub_13
12611      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12612    },
12613    {	// DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12614      90,	// dsub_0 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12615      90,	// dsub_1 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12616      90,	// dsub_2 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12617      90,	// dsub_3 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12618      0,	// dsub_4
12619      0,	// dsub_5
12620      0,	// dsub_6
12621      0,	// dsub_7
12622      0,	// gsub_0
12623      0,	// gsub_1
12624      0,	// qqsub_0
12625      0,	// qqsub_1
12626      90,	// qsub_0 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12627      90,	// qsub_1 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12628      0,	// qsub_2
12629      0,	// qsub_3
12630      90,	// ssub_0 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12631      90,	// ssub_1 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12632      90,	// ssub_2 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12633      90,	// ssub_3 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12634      90,	// ssub_4 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12635      90,	// ssub_5 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12636      90,	// ssub_6 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12637      90,	// ssub_7 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12638      0,	// ssub_8
12639      0,	// ssub_9
12640      0,	// ssub_10
12641      0,	// ssub_11
12642      0,	// ssub_12
12643      0,	// ssub_13
12644      0,	// dsub_7_then_ssub_0
12645      0,	// dsub_7_then_ssub_1
12646      90,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12647      90,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12648      90,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12649      90,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12650      90,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12651      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12652      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12653      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12654      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12655      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12656      0,	// ssub_4_ssub_5_ssub_8_ssub_9
12657      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12658      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12659      0,	// ssub_6_ssub_7_dsub_5
12660      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12661      0,	// ssub_6_ssub_7_dsub_5_dsub_7
12662      0,	// ssub_6_ssub_7_ssub_8_ssub_9
12663      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12664      0,	// ssub_8_ssub_9_ssub_12_ssub_13
12665      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12666      0,	// dsub_5_dsub_7
12667      0,	// dsub_5_ssub_12_ssub_13_dsub_7
12668      0,	// dsub_5_ssub_12_ssub_13
12669      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12670    },
12671    {	// DQuad_with_qsub_0_in_QPR_8
12672      91,	// dsub_0 -> DQuad_with_qsub_0_in_QPR_8
12673      91,	// dsub_1 -> DQuad_with_qsub_0_in_QPR_8
12674      91,	// dsub_2 -> DQuad_with_qsub_0_in_QPR_8
12675      91,	// dsub_3 -> DQuad_with_qsub_0_in_QPR_8
12676      0,	// dsub_4
12677      0,	// dsub_5
12678      0,	// dsub_6
12679      0,	// dsub_7
12680      0,	// gsub_0
12681      0,	// gsub_1
12682      0,	// qqsub_0
12683      0,	// qqsub_1
12684      91,	// qsub_0 -> DQuad_with_qsub_0_in_QPR_8
12685      91,	// qsub_1 -> DQuad_with_qsub_0_in_QPR_8
12686      0,	// qsub_2
12687      0,	// qsub_3
12688      91,	// ssub_0 -> DQuad_with_qsub_0_in_QPR_8
12689      91,	// ssub_1 -> DQuad_with_qsub_0_in_QPR_8
12690      91,	// ssub_2 -> DQuad_with_qsub_0_in_QPR_8
12691      91,	// ssub_3 -> DQuad_with_qsub_0_in_QPR_8
12692      91,	// ssub_4 -> DQuad_with_qsub_0_in_QPR_8
12693      91,	// ssub_5 -> DQuad_with_qsub_0_in_QPR_8
12694      91,	// ssub_6 -> DQuad_with_qsub_0_in_QPR_8
12695      91,	// ssub_7 -> DQuad_with_qsub_0_in_QPR_8
12696      0,	// ssub_8
12697      0,	// ssub_9
12698      0,	// ssub_10
12699      0,	// ssub_11
12700      0,	// ssub_12
12701      0,	// ssub_13
12702      0,	// dsub_7_then_ssub_0
12703      0,	// dsub_7_then_ssub_1
12704      91,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_8
12705      91,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_8
12706      91,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_qsub_0_in_QPR_8
12707      91,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_qsub_0_in_QPR_8
12708      91,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_8
12709      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12710      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12711      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12712      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12713      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12714      0,	// ssub_4_ssub_5_ssub_8_ssub_9
12715      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12716      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12717      0,	// ssub_6_ssub_7_dsub_5
12718      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12719      0,	// ssub_6_ssub_7_dsub_5_dsub_7
12720      0,	// ssub_6_ssub_7_ssub_8_ssub_9
12721      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12722      0,	// ssub_8_ssub_9_ssub_12_ssub_13
12723      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12724      0,	// dsub_5_dsub_7
12725      0,	// dsub_5_ssub_12_ssub_13_dsub_7
12726      0,	// dsub_5_ssub_12_ssub_13
12727      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12728    },
12729    {	// DQuad_with_qsub_1_in_QPR_8
12730      92,	// dsub_0 -> DQuad_with_qsub_1_in_QPR_8
12731      92,	// dsub_1 -> DQuad_with_qsub_1_in_QPR_8
12732      92,	// dsub_2 -> DQuad_with_qsub_1_in_QPR_8
12733      92,	// dsub_3 -> DQuad_with_qsub_1_in_QPR_8
12734      0,	// dsub_4
12735      0,	// dsub_5
12736      0,	// dsub_6
12737      0,	// dsub_7
12738      0,	// gsub_0
12739      0,	// gsub_1
12740      0,	// qqsub_0
12741      0,	// qqsub_1
12742      92,	// qsub_0 -> DQuad_with_qsub_1_in_QPR_8
12743      92,	// qsub_1 -> DQuad_with_qsub_1_in_QPR_8
12744      0,	// qsub_2
12745      0,	// qsub_3
12746      92,	// ssub_0 -> DQuad_with_qsub_1_in_QPR_8
12747      92,	// ssub_1 -> DQuad_with_qsub_1_in_QPR_8
12748      92,	// ssub_2 -> DQuad_with_qsub_1_in_QPR_8
12749      92,	// ssub_3 -> DQuad_with_qsub_1_in_QPR_8
12750      92,	// ssub_4 -> DQuad_with_qsub_1_in_QPR_8
12751      92,	// ssub_5 -> DQuad_with_qsub_1_in_QPR_8
12752      92,	// ssub_6 -> DQuad_with_qsub_1_in_QPR_8
12753      92,	// ssub_7 -> DQuad_with_qsub_1_in_QPR_8
12754      0,	// ssub_8
12755      0,	// ssub_9
12756      0,	// ssub_10
12757      0,	// ssub_11
12758      0,	// ssub_12
12759      0,	// ssub_13
12760      0,	// dsub_7_then_ssub_0
12761      0,	// dsub_7_then_ssub_1
12762      92,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_8
12763      92,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_8
12764      92,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_qsub_1_in_QPR_8
12765      92,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_qsub_1_in_QPR_8
12766      92,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_8
12767      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12768      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12769      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12770      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12771      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12772      0,	// ssub_4_ssub_5_ssub_8_ssub_9
12773      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12774      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12775      0,	// ssub_6_ssub_7_dsub_5
12776      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12777      0,	// ssub_6_ssub_7_dsub_5_dsub_7
12778      0,	// ssub_6_ssub_7_ssub_8_ssub_9
12779      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12780      0,	// ssub_8_ssub_9_ssub_12_ssub_13
12781      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12782      0,	// dsub_5_dsub_7
12783      0,	// dsub_5_ssub_12_ssub_13_dsub_7
12784      0,	// dsub_5_ssub_12_ssub_13
12785      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12786    },
12787    {	// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12788      93,	// dsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12789      93,	// dsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12790      93,	// dsub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12791      93,	// dsub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12792      0,	// dsub_4
12793      0,	// dsub_5
12794      0,	// dsub_6
12795      0,	// dsub_7
12796      0,	// gsub_0
12797      0,	// gsub_1
12798      0,	// qqsub_0
12799      0,	// qqsub_1
12800      93,	// qsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12801      93,	// qsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12802      0,	// qsub_2
12803      0,	// qsub_3
12804      93,	// ssub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12805      93,	// ssub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12806      93,	// ssub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12807      93,	// ssub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12808      93,	// ssub_4 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12809      93,	// ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12810      93,	// ssub_6 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12811      93,	// ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12812      0,	// ssub_8
12813      0,	// ssub_9
12814      0,	// ssub_10
12815      0,	// ssub_11
12816      0,	// ssub_12
12817      0,	// ssub_13
12818      0,	// dsub_7_then_ssub_0
12819      0,	// dsub_7_then_ssub_1
12820      93,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12821      93,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12822      93,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12823      93,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12824      93,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
12825      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12826      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12827      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12828      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12829      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12830      0,	// ssub_4_ssub_5_ssub_8_ssub_9
12831      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12832      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12833      0,	// ssub_6_ssub_7_dsub_5
12834      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12835      0,	// ssub_6_ssub_7_dsub_5_dsub_7
12836      0,	// ssub_6_ssub_7_ssub_8_ssub_9
12837      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12838      0,	// ssub_8_ssub_9_ssub_12_ssub_13
12839      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12840      0,	// dsub_5_dsub_7
12841      0,	// dsub_5_ssub_12_ssub_13_dsub_7
12842      0,	// dsub_5_ssub_12_ssub_13
12843      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12844    },
12845    {	// DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12846      94,	// dsub_0 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12847      94,	// dsub_1 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12848      94,	// dsub_2 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12849      94,	// dsub_3 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12850      0,	// dsub_4
12851      0,	// dsub_5
12852      0,	// dsub_6
12853      0,	// dsub_7
12854      0,	// gsub_0
12855      0,	// gsub_1
12856      0,	// qqsub_0
12857      0,	// qqsub_1
12858      94,	// qsub_0 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12859      94,	// qsub_1 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12860      0,	// qsub_2
12861      0,	// qsub_3
12862      94,	// ssub_0 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12863      94,	// ssub_1 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12864      94,	// ssub_2 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12865      94,	// ssub_3 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12866      94,	// ssub_4 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12867      94,	// ssub_5 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12868      94,	// ssub_6 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12869      94,	// ssub_7 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12870      0,	// ssub_8
12871      0,	// ssub_9
12872      0,	// ssub_10
12873      0,	// ssub_11
12874      0,	// ssub_12
12875      0,	// ssub_13
12876      0,	// dsub_7_then_ssub_0
12877      0,	// dsub_7_then_ssub_1
12878      94,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12879      94,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12880      94,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12881      94,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12882      94,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
12883      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
12884      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12885      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
12886      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
12887      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12888      0,	// ssub_4_ssub_5_ssub_8_ssub_9
12889      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
12890      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
12891      0,	// ssub_6_ssub_7_dsub_5
12892      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
12893      0,	// ssub_6_ssub_7_dsub_5_dsub_7
12894      0,	// ssub_6_ssub_7_ssub_8_ssub_9
12895      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12896      0,	// ssub_8_ssub_9_ssub_12_ssub_13
12897      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
12898      0,	// dsub_5_dsub_7
12899      0,	// dsub_5_ssub_12_ssub_13_dsub_7
12900      0,	// dsub_5_ssub_12_ssub_13
12901      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
12902    },
12903    {	// QQQQPR
12904      95,	// dsub_0 -> QQQQPR
12905      95,	// dsub_1 -> QQQQPR
12906      95,	// dsub_2 -> QQQQPR
12907      95,	// dsub_3 -> QQQQPR
12908      95,	// dsub_4 -> QQQQPR
12909      95,	// dsub_5 -> QQQQPR
12910      95,	// dsub_6 -> QQQQPR
12911      95,	// dsub_7 -> QQQQPR
12912      0,	// gsub_0
12913      0,	// gsub_1
12914      95,	// qqsub_0 -> QQQQPR
12915      95,	// qqsub_1 -> QQQQPR
12916      95,	// qsub_0 -> QQQQPR
12917      95,	// qsub_1 -> QQQQPR
12918      95,	// qsub_2 -> QQQQPR
12919      95,	// qsub_3 -> QQQQPR
12920      96,	// ssub_0 -> QQQQPR_with_ssub_0
12921      96,	// ssub_1 -> QQQQPR_with_ssub_0
12922      96,	// ssub_2 -> QQQQPR_with_ssub_0
12923      96,	// ssub_3 -> QQQQPR_with_ssub_0
12924      97,	// ssub_4 -> QQQQPR_with_ssub_4
12925      97,	// ssub_5 -> QQQQPR_with_ssub_4
12926      97,	// ssub_6 -> QQQQPR_with_ssub_4
12927      97,	// ssub_7 -> QQQQPR_with_ssub_4
12928      98,	// ssub_8 -> QQQQPR_with_ssub_8
12929      98,	// ssub_9 -> QQQQPR_with_ssub_8
12930      98,	// ssub_10 -> QQQQPR_with_ssub_8
12931      98,	// ssub_11 -> QQQQPR_with_ssub_8
12932      99,	// ssub_12 -> QQQQPR_with_ssub_12
12933      99,	// ssub_13 -> QQQQPR_with_ssub_12
12934      99,	// dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12
12935      99,	// dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12
12936      95,	// ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR
12937      95,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR
12938      95,	// ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR
12939      95,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR
12940      95,	// ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR
12941      95,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR
12942      95,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR
12943      95,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR
12944      95,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR
12945      95,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR
12946      95,	// ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR
12947      95,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR
12948      95,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR
12949      95,	// ssub_6_ssub_7_dsub_5 -> QQQQPR
12950      95,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR
12951      95,	// ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR
12952      95,	// ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR
12953      95,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR
12954      95,	// ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR
12955      95,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR
12956      95,	// dsub_5_dsub_7 -> QQQQPR
12957      95,	// dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR
12958      95,	// dsub_5_ssub_12_ssub_13 -> QQQQPR
12959      95,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR
12960    },
12961    {	// QQQQPR_with_ssub_0
12962      96,	// dsub_0 -> QQQQPR_with_ssub_0
12963      96,	// dsub_1 -> QQQQPR_with_ssub_0
12964      96,	// dsub_2 -> QQQQPR_with_ssub_0
12965      96,	// dsub_3 -> QQQQPR_with_ssub_0
12966      96,	// dsub_4 -> QQQQPR_with_ssub_0
12967      96,	// dsub_5 -> QQQQPR_with_ssub_0
12968      96,	// dsub_6 -> QQQQPR_with_ssub_0
12969      96,	// dsub_7 -> QQQQPR_with_ssub_0
12970      0,	// gsub_0
12971      0,	// gsub_1
12972      96,	// qqsub_0 -> QQQQPR_with_ssub_0
12973      96,	// qqsub_1 -> QQQQPR_with_ssub_0
12974      96,	// qsub_0 -> QQQQPR_with_ssub_0
12975      96,	// qsub_1 -> QQQQPR_with_ssub_0
12976      96,	// qsub_2 -> QQQQPR_with_ssub_0
12977      96,	// qsub_3 -> QQQQPR_with_ssub_0
12978      96,	// ssub_0 -> QQQQPR_with_ssub_0
12979      96,	// ssub_1 -> QQQQPR_with_ssub_0
12980      96,	// ssub_2 -> QQQQPR_with_ssub_0
12981      96,	// ssub_3 -> QQQQPR_with_ssub_0
12982      97,	// ssub_4 -> QQQQPR_with_ssub_4
12983      97,	// ssub_5 -> QQQQPR_with_ssub_4
12984      97,	// ssub_6 -> QQQQPR_with_ssub_4
12985      97,	// ssub_7 -> QQQQPR_with_ssub_4
12986      98,	// ssub_8 -> QQQQPR_with_ssub_8
12987      98,	// ssub_9 -> QQQQPR_with_ssub_8
12988      98,	// ssub_10 -> QQQQPR_with_ssub_8
12989      98,	// ssub_11 -> QQQQPR_with_ssub_8
12990      99,	// ssub_12 -> QQQQPR_with_ssub_12
12991      99,	// ssub_13 -> QQQQPR_with_ssub_12
12992      99,	// dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12
12993      99,	// dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12
12994      96,	// ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_ssub_0
12995      96,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_0
12996      96,	// ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_ssub_0
12997      96,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_ssub_0
12998      96,	// ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_0
12999      96,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_0
13000      96,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_0
13001      96,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_0
13002      96,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_0
13003      96,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_0
13004      96,	// ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_0
13005      96,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_0
13006      96,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_0
13007      96,	// ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_0
13008      96,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_ssub_0
13009      96,	// ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_0
13010      96,	// ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_0
13011      96,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_0
13012      96,	// ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_0
13013      96,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_0
13014      96,	// dsub_5_dsub_7 -> QQQQPR_with_ssub_0
13015      96,	// dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_ssub_0
13016      96,	// dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_0
13017      96,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_ssub_0
13018    },
13019    {	// QQQQPR_with_ssub_4
13020      97,	// dsub_0 -> QQQQPR_with_ssub_4
13021      97,	// dsub_1 -> QQQQPR_with_ssub_4
13022      97,	// dsub_2 -> QQQQPR_with_ssub_4
13023      97,	// dsub_3 -> QQQQPR_with_ssub_4
13024      97,	// dsub_4 -> QQQQPR_with_ssub_4
13025      97,	// dsub_5 -> QQQQPR_with_ssub_4
13026      97,	// dsub_6 -> QQQQPR_with_ssub_4
13027      97,	// dsub_7 -> QQQQPR_with_ssub_4
13028      0,	// gsub_0
13029      0,	// gsub_1
13030      97,	// qqsub_0 -> QQQQPR_with_ssub_4
13031      97,	// qqsub_1 -> QQQQPR_with_ssub_4
13032      97,	// qsub_0 -> QQQQPR_with_ssub_4
13033      97,	// qsub_1 -> QQQQPR_with_ssub_4
13034      97,	// qsub_2 -> QQQQPR_with_ssub_4
13035      97,	// qsub_3 -> QQQQPR_with_ssub_4
13036      97,	// ssub_0 -> QQQQPR_with_ssub_4
13037      97,	// ssub_1 -> QQQQPR_with_ssub_4
13038      97,	// ssub_2 -> QQQQPR_with_ssub_4
13039      97,	// ssub_3 -> QQQQPR_with_ssub_4
13040      97,	// ssub_4 -> QQQQPR_with_ssub_4
13041      97,	// ssub_5 -> QQQQPR_with_ssub_4
13042      97,	// ssub_6 -> QQQQPR_with_ssub_4
13043      97,	// ssub_7 -> QQQQPR_with_ssub_4
13044      98,	// ssub_8 -> QQQQPR_with_ssub_8
13045      98,	// ssub_9 -> QQQQPR_with_ssub_8
13046      98,	// ssub_10 -> QQQQPR_with_ssub_8
13047      98,	// ssub_11 -> QQQQPR_with_ssub_8
13048      99,	// ssub_12 -> QQQQPR_with_ssub_12
13049      99,	// ssub_13 -> QQQQPR_with_ssub_12
13050      99,	// dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12
13051      99,	// dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12
13052      97,	// ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_ssub_4
13053      97,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_4
13054      97,	// ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_ssub_4
13055      97,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_ssub_4
13056      97,	// ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_4
13057      97,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_4
13058      97,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_4
13059      97,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_4
13060      97,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_4
13061      97,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_4
13062      97,	// ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_4
13063      97,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_4
13064      97,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_4
13065      97,	// ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_4
13066      97,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_ssub_4
13067      97,	// ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_4
13068      97,	// ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_4
13069      97,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_4
13070      97,	// ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_4
13071      97,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_4
13072      97,	// dsub_5_dsub_7 -> QQQQPR_with_ssub_4
13073      97,	// dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_ssub_4
13074      97,	// dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_4
13075      97,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_ssub_4
13076    },
13077    {	// QQQQPR_with_ssub_8
13078      98,	// dsub_0 -> QQQQPR_with_ssub_8
13079      98,	// dsub_1 -> QQQQPR_with_ssub_8
13080      98,	// dsub_2 -> QQQQPR_with_ssub_8
13081      98,	// dsub_3 -> QQQQPR_with_ssub_8
13082      98,	// dsub_4 -> QQQQPR_with_ssub_8
13083      98,	// dsub_5 -> QQQQPR_with_ssub_8
13084      98,	// dsub_6 -> QQQQPR_with_ssub_8
13085      98,	// dsub_7 -> QQQQPR_with_ssub_8
13086      0,	// gsub_0
13087      0,	// gsub_1
13088      98,	// qqsub_0 -> QQQQPR_with_ssub_8
13089      98,	// qqsub_1 -> QQQQPR_with_ssub_8
13090      98,	// qsub_0 -> QQQQPR_with_ssub_8
13091      98,	// qsub_1 -> QQQQPR_with_ssub_8
13092      98,	// qsub_2 -> QQQQPR_with_ssub_8
13093      98,	// qsub_3 -> QQQQPR_with_ssub_8
13094      98,	// ssub_0 -> QQQQPR_with_ssub_8
13095      98,	// ssub_1 -> QQQQPR_with_ssub_8
13096      98,	// ssub_2 -> QQQQPR_with_ssub_8
13097      98,	// ssub_3 -> QQQQPR_with_ssub_8
13098      98,	// ssub_4 -> QQQQPR_with_ssub_8
13099      98,	// ssub_5 -> QQQQPR_with_ssub_8
13100      98,	// ssub_6 -> QQQQPR_with_ssub_8
13101      98,	// ssub_7 -> QQQQPR_with_ssub_8
13102      98,	// ssub_8 -> QQQQPR_with_ssub_8
13103      98,	// ssub_9 -> QQQQPR_with_ssub_8
13104      98,	// ssub_10 -> QQQQPR_with_ssub_8
13105      98,	// ssub_11 -> QQQQPR_with_ssub_8
13106      99,	// ssub_12 -> QQQQPR_with_ssub_12
13107      99,	// ssub_13 -> QQQQPR_with_ssub_12
13108      99,	// dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12
13109      99,	// dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12
13110      98,	// ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_ssub_8
13111      98,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_8
13112      98,	// ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_ssub_8
13113      98,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_ssub_8
13114      98,	// ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_8
13115      98,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_8
13116      98,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_8
13117      98,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_8
13118      98,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_8
13119      98,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_8
13120      98,	// ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_8
13121      98,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_8
13122      98,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_8
13123      98,	// ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_8
13124      98,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_ssub_8
13125      98,	// ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_8
13126      98,	// ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_8
13127      98,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_8
13128      98,	// ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_8
13129      98,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_8
13130      98,	// dsub_5_dsub_7 -> QQQQPR_with_ssub_8
13131      98,	// dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_ssub_8
13132      98,	// dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_8
13133      98,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_ssub_8
13134    },
13135    {	// QQQQPR_with_ssub_12
13136      99,	// dsub_0 -> QQQQPR_with_ssub_12
13137      99,	// dsub_1 -> QQQQPR_with_ssub_12
13138      99,	// dsub_2 -> QQQQPR_with_ssub_12
13139      99,	// dsub_3 -> QQQQPR_with_ssub_12
13140      99,	// dsub_4 -> QQQQPR_with_ssub_12
13141      99,	// dsub_5 -> QQQQPR_with_ssub_12
13142      99,	// dsub_6 -> QQQQPR_with_ssub_12
13143      99,	// dsub_7 -> QQQQPR_with_ssub_12
13144      0,	// gsub_0
13145      0,	// gsub_1
13146      99,	// qqsub_0 -> QQQQPR_with_ssub_12
13147      99,	// qqsub_1 -> QQQQPR_with_ssub_12
13148      99,	// qsub_0 -> QQQQPR_with_ssub_12
13149      99,	// qsub_1 -> QQQQPR_with_ssub_12
13150      99,	// qsub_2 -> QQQQPR_with_ssub_12
13151      99,	// qsub_3 -> QQQQPR_with_ssub_12
13152      99,	// ssub_0 -> QQQQPR_with_ssub_12
13153      99,	// ssub_1 -> QQQQPR_with_ssub_12
13154      99,	// ssub_2 -> QQQQPR_with_ssub_12
13155      99,	// ssub_3 -> QQQQPR_with_ssub_12
13156      99,	// ssub_4 -> QQQQPR_with_ssub_12
13157      99,	// ssub_5 -> QQQQPR_with_ssub_12
13158      99,	// ssub_6 -> QQQQPR_with_ssub_12
13159      99,	// ssub_7 -> QQQQPR_with_ssub_12
13160      99,	// ssub_8 -> QQQQPR_with_ssub_12
13161      99,	// ssub_9 -> QQQQPR_with_ssub_12
13162      99,	// ssub_10 -> QQQQPR_with_ssub_12
13163      99,	// ssub_11 -> QQQQPR_with_ssub_12
13164      99,	// ssub_12 -> QQQQPR_with_ssub_12
13165      99,	// ssub_13 -> QQQQPR_with_ssub_12
13166      99,	// dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12
13167      99,	// dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12
13168      99,	// ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_ssub_12
13169      99,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_12
13170      99,	// ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_ssub_12
13171      99,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_ssub_12
13172      99,	// ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_12
13173      99,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_12
13174      99,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_12
13175      99,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_12
13176      99,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_12
13177      99,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_12
13178      99,	// ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_12
13179      99,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_12
13180      99,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_12
13181      99,	// ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_12
13182      99,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_ssub_12
13183      99,	// ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_12
13184      99,	// ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_12
13185      99,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_12
13186      99,	// ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_12
13187      99,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_12
13188      99,	// dsub_5_dsub_7 -> QQQQPR_with_ssub_12
13189      99,	// dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_ssub_12
13190      99,	// dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_12
13191      99,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_ssub_12
13192    },
13193    {	// QQQQPR_with_dsub_0_in_DPR_8
13194      100,	// dsub_0 -> QQQQPR_with_dsub_0_in_DPR_8
13195      100,	// dsub_1 -> QQQQPR_with_dsub_0_in_DPR_8
13196      100,	// dsub_2 -> QQQQPR_with_dsub_0_in_DPR_8
13197      100,	// dsub_3 -> QQQQPR_with_dsub_0_in_DPR_8
13198      100,	// dsub_4 -> QQQQPR_with_dsub_0_in_DPR_8
13199      100,	// dsub_5 -> QQQQPR_with_dsub_0_in_DPR_8
13200      100,	// dsub_6 -> QQQQPR_with_dsub_0_in_DPR_8
13201      100,	// dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8
13202      0,	// gsub_0
13203      0,	// gsub_1
13204      100,	// qqsub_0 -> QQQQPR_with_dsub_0_in_DPR_8
13205      100,	// qqsub_1 -> QQQQPR_with_dsub_0_in_DPR_8
13206      100,	// qsub_0 -> QQQQPR_with_dsub_0_in_DPR_8
13207      100,	// qsub_1 -> QQQQPR_with_dsub_0_in_DPR_8
13208      100,	// qsub_2 -> QQQQPR_with_dsub_0_in_DPR_8
13209      100,	// qsub_3 -> QQQQPR_with_dsub_0_in_DPR_8
13210      100,	// ssub_0 -> QQQQPR_with_dsub_0_in_DPR_8
13211      100,	// ssub_1 -> QQQQPR_with_dsub_0_in_DPR_8
13212      100,	// ssub_2 -> QQQQPR_with_dsub_0_in_DPR_8
13213      100,	// ssub_3 -> QQQQPR_with_dsub_0_in_DPR_8
13214      100,	// ssub_4 -> QQQQPR_with_dsub_0_in_DPR_8
13215      100,	// ssub_5 -> QQQQPR_with_dsub_0_in_DPR_8
13216      100,	// ssub_6 -> QQQQPR_with_dsub_0_in_DPR_8
13217      100,	// ssub_7 -> QQQQPR_with_dsub_0_in_DPR_8
13218      100,	// ssub_8 -> QQQQPR_with_dsub_0_in_DPR_8
13219      100,	// ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8
13220      100,	// ssub_10 -> QQQQPR_with_dsub_0_in_DPR_8
13221      100,	// ssub_11 -> QQQQPR_with_dsub_0_in_DPR_8
13222      100,	// ssub_12 -> QQQQPR_with_dsub_0_in_DPR_8
13223      100,	// ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
13224      100,	// dsub_7_then_ssub_0 -> QQQQPR_with_dsub_0_in_DPR_8
13225      100,	// dsub_7_then_ssub_1 -> QQQQPR_with_dsub_0_in_DPR_8
13226      100,	// ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_dsub_0_in_DPR_8
13227      100,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_0_in_DPR_8
13228      100,	// ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_dsub_0_in_DPR_8
13229      100,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_dsub_0_in_DPR_8
13230      100,	// ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_0_in_DPR_8
13231      100,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8
13232      100,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
13233      100,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_0_in_DPR_8
13234      100,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8
13235      100,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8
13236      100,	// ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8
13237      100,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8
13238      100,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
13239      100,	// ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_0_in_DPR_8
13240      100,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_dsub_0_in_DPR_8
13241      100,	// ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8
13242      100,	// ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8
13243      100,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
13244      100,	// ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
13245      100,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
13246      100,	// dsub_5_dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8
13247      100,	// dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8
13248      100,	// dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
13249      100,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_dsub_0_in_DPR_8
13250    },
13251    {	// QQQQPR_with_dsub_2_in_DPR_8
13252      101,	// dsub_0 -> QQQQPR_with_dsub_2_in_DPR_8
13253      101,	// dsub_1 -> QQQQPR_with_dsub_2_in_DPR_8
13254      101,	// dsub_2 -> QQQQPR_with_dsub_2_in_DPR_8
13255      101,	// dsub_3 -> QQQQPR_with_dsub_2_in_DPR_8
13256      101,	// dsub_4 -> QQQQPR_with_dsub_2_in_DPR_8
13257      101,	// dsub_5 -> QQQQPR_with_dsub_2_in_DPR_8
13258      101,	// dsub_6 -> QQQQPR_with_dsub_2_in_DPR_8
13259      101,	// dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8
13260      0,	// gsub_0
13261      0,	// gsub_1
13262      101,	// qqsub_0 -> QQQQPR_with_dsub_2_in_DPR_8
13263      101,	// qqsub_1 -> QQQQPR_with_dsub_2_in_DPR_8
13264      101,	// qsub_0 -> QQQQPR_with_dsub_2_in_DPR_8
13265      101,	// qsub_1 -> QQQQPR_with_dsub_2_in_DPR_8
13266      101,	// qsub_2 -> QQQQPR_with_dsub_2_in_DPR_8
13267      101,	// qsub_3 -> QQQQPR_with_dsub_2_in_DPR_8
13268      101,	// ssub_0 -> QQQQPR_with_dsub_2_in_DPR_8
13269      101,	// ssub_1 -> QQQQPR_with_dsub_2_in_DPR_8
13270      101,	// ssub_2 -> QQQQPR_with_dsub_2_in_DPR_8
13271      101,	// ssub_3 -> QQQQPR_with_dsub_2_in_DPR_8
13272      101,	// ssub_4 -> QQQQPR_with_dsub_2_in_DPR_8
13273      101,	// ssub_5 -> QQQQPR_with_dsub_2_in_DPR_8
13274      101,	// ssub_6 -> QQQQPR_with_dsub_2_in_DPR_8
13275      101,	// ssub_7 -> QQQQPR_with_dsub_2_in_DPR_8
13276      101,	// ssub_8 -> QQQQPR_with_dsub_2_in_DPR_8
13277      101,	// ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8
13278      101,	// ssub_10 -> QQQQPR_with_dsub_2_in_DPR_8
13279      101,	// ssub_11 -> QQQQPR_with_dsub_2_in_DPR_8
13280      101,	// ssub_12 -> QQQQPR_with_dsub_2_in_DPR_8
13281      101,	// ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
13282      101,	// dsub_7_then_ssub_0 -> QQQQPR_with_dsub_2_in_DPR_8
13283      101,	// dsub_7_then_ssub_1 -> QQQQPR_with_dsub_2_in_DPR_8
13284      101,	// ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_dsub_2_in_DPR_8
13285      101,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_2_in_DPR_8
13286      101,	// ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_dsub_2_in_DPR_8
13287      101,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_dsub_2_in_DPR_8
13288      101,	// ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_2_in_DPR_8
13289      101,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8
13290      101,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
13291      101,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_2_in_DPR_8
13292      101,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8
13293      101,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8
13294      101,	// ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8
13295      101,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8
13296      101,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
13297      101,	// ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_2_in_DPR_8
13298      101,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_dsub_2_in_DPR_8
13299      101,	// ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8
13300      101,	// ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8
13301      101,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
13302      101,	// ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
13303      101,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
13304      101,	// dsub_5_dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8
13305      101,	// dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8
13306      101,	// dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
13307      101,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_dsub_2_in_DPR_8
13308    },
13309    {	// QQQQPR_with_dsub_4_in_DPR_8
13310      102,	// dsub_0 -> QQQQPR_with_dsub_4_in_DPR_8
13311      102,	// dsub_1 -> QQQQPR_with_dsub_4_in_DPR_8
13312      102,	// dsub_2 -> QQQQPR_with_dsub_4_in_DPR_8
13313      102,	// dsub_3 -> QQQQPR_with_dsub_4_in_DPR_8
13314      102,	// dsub_4 -> QQQQPR_with_dsub_4_in_DPR_8
13315      102,	// dsub_5 -> QQQQPR_with_dsub_4_in_DPR_8
13316      102,	// dsub_6 -> QQQQPR_with_dsub_4_in_DPR_8
13317      102,	// dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8
13318      0,	// gsub_0
13319      0,	// gsub_1
13320      102,	// qqsub_0 -> QQQQPR_with_dsub_4_in_DPR_8
13321      102,	// qqsub_1 -> QQQQPR_with_dsub_4_in_DPR_8
13322      102,	// qsub_0 -> QQQQPR_with_dsub_4_in_DPR_8
13323      102,	// qsub_1 -> QQQQPR_with_dsub_4_in_DPR_8
13324      102,	// qsub_2 -> QQQQPR_with_dsub_4_in_DPR_8
13325      102,	// qsub_3 -> QQQQPR_with_dsub_4_in_DPR_8
13326      102,	// ssub_0 -> QQQQPR_with_dsub_4_in_DPR_8
13327      102,	// ssub_1 -> QQQQPR_with_dsub_4_in_DPR_8
13328      102,	// ssub_2 -> QQQQPR_with_dsub_4_in_DPR_8
13329      102,	// ssub_3 -> QQQQPR_with_dsub_4_in_DPR_8
13330      102,	// ssub_4 -> QQQQPR_with_dsub_4_in_DPR_8
13331      102,	// ssub_5 -> QQQQPR_with_dsub_4_in_DPR_8
13332      102,	// ssub_6 -> QQQQPR_with_dsub_4_in_DPR_8
13333      102,	// ssub_7 -> QQQQPR_with_dsub_4_in_DPR_8
13334      102,	// ssub_8 -> QQQQPR_with_dsub_4_in_DPR_8
13335      102,	// ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8
13336      102,	// ssub_10 -> QQQQPR_with_dsub_4_in_DPR_8
13337      102,	// ssub_11 -> QQQQPR_with_dsub_4_in_DPR_8
13338      102,	// ssub_12 -> QQQQPR_with_dsub_4_in_DPR_8
13339      102,	// ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
13340      102,	// dsub_7_then_ssub_0 -> QQQQPR_with_dsub_4_in_DPR_8
13341      102,	// dsub_7_then_ssub_1 -> QQQQPR_with_dsub_4_in_DPR_8
13342      102,	// ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_dsub_4_in_DPR_8
13343      102,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_4_in_DPR_8
13344      102,	// ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_dsub_4_in_DPR_8
13345      102,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_dsub_4_in_DPR_8
13346      102,	// ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_4_in_DPR_8
13347      102,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8
13348      102,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
13349      102,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_4_in_DPR_8
13350      102,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8
13351      102,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8
13352      102,	// ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8
13353      102,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8
13354      102,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
13355      102,	// ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_4_in_DPR_8
13356      102,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_dsub_4_in_DPR_8
13357      102,	// ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8
13358      102,	// ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8
13359      102,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
13360      102,	// ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
13361      102,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
13362      102,	// dsub_5_dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8
13363      102,	// dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8
13364      102,	// dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
13365      102,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_dsub_4_in_DPR_8
13366    },
13367    {	// QQQQPR_with_dsub_6_in_DPR_8
13368      103,	// dsub_0 -> QQQQPR_with_dsub_6_in_DPR_8
13369      103,	// dsub_1 -> QQQQPR_with_dsub_6_in_DPR_8
13370      103,	// dsub_2 -> QQQQPR_with_dsub_6_in_DPR_8
13371      103,	// dsub_3 -> QQQQPR_with_dsub_6_in_DPR_8
13372      103,	// dsub_4 -> QQQQPR_with_dsub_6_in_DPR_8
13373      103,	// dsub_5 -> QQQQPR_with_dsub_6_in_DPR_8
13374      103,	// dsub_6 -> QQQQPR_with_dsub_6_in_DPR_8
13375      103,	// dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8
13376      0,	// gsub_0
13377      0,	// gsub_1
13378      103,	// qqsub_0 -> QQQQPR_with_dsub_6_in_DPR_8
13379      103,	// qqsub_1 -> QQQQPR_with_dsub_6_in_DPR_8
13380      103,	// qsub_0 -> QQQQPR_with_dsub_6_in_DPR_8
13381      103,	// qsub_1 -> QQQQPR_with_dsub_6_in_DPR_8
13382      103,	// qsub_2 -> QQQQPR_with_dsub_6_in_DPR_8
13383      103,	// qsub_3 -> QQQQPR_with_dsub_6_in_DPR_8
13384      103,	// ssub_0 -> QQQQPR_with_dsub_6_in_DPR_8
13385      103,	// ssub_1 -> QQQQPR_with_dsub_6_in_DPR_8
13386      103,	// ssub_2 -> QQQQPR_with_dsub_6_in_DPR_8
13387      103,	// ssub_3 -> QQQQPR_with_dsub_6_in_DPR_8
13388      103,	// ssub_4 -> QQQQPR_with_dsub_6_in_DPR_8
13389      103,	// ssub_5 -> QQQQPR_with_dsub_6_in_DPR_8
13390      103,	// ssub_6 -> QQQQPR_with_dsub_6_in_DPR_8
13391      103,	// ssub_7 -> QQQQPR_with_dsub_6_in_DPR_8
13392      103,	// ssub_8 -> QQQQPR_with_dsub_6_in_DPR_8
13393      103,	// ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8
13394      103,	// ssub_10 -> QQQQPR_with_dsub_6_in_DPR_8
13395      103,	// ssub_11 -> QQQQPR_with_dsub_6_in_DPR_8
13396      103,	// ssub_12 -> QQQQPR_with_dsub_6_in_DPR_8
13397      103,	// ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
13398      103,	// dsub_7_then_ssub_0 -> QQQQPR_with_dsub_6_in_DPR_8
13399      103,	// dsub_7_then_ssub_1 -> QQQQPR_with_dsub_6_in_DPR_8
13400      103,	// ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_dsub_6_in_DPR_8
13401      103,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_6_in_DPR_8
13402      103,	// ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_dsub_6_in_DPR_8
13403      103,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_dsub_6_in_DPR_8
13404      103,	// ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_6_in_DPR_8
13405      103,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8
13406      103,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
13407      103,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_6_in_DPR_8
13408      103,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8
13409      103,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8
13410      103,	// ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8
13411      103,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8
13412      103,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
13413      103,	// ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_6_in_DPR_8
13414      103,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_dsub_6_in_DPR_8
13415      103,	// ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8
13416      103,	// ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8
13417      103,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
13418      103,	// ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
13419      103,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
13420      103,	// dsub_5_dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8
13421      103,	// dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8
13422      103,	// dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
13423      103,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_dsub_6_in_DPR_8
13424    },
13425  };
13426  assert(RC && "Missing regclass");
13427  if (!Idx) return RC;
13428  --Idx;
13429  assert(Idx < 56 && "Bad subreg");
13430  unsigned TV = Table[RC->getID()][Idx];
13431  return TV ? getRegClass(TV - 1) : nullptr;
13432}
13433
13434/// Get the weight in units of pressure for this register class.
13435const RegClassWeight &ARMGenRegisterInfo::
13436getRegClassWeight(const TargetRegisterClass *RC) const {
13437  static const RegClassWeight RCWeightTable[] = {
13438    {1, 32},  	// HPR
13439    {1, 32},  	// SPR
13440    {1, 16},  	// GPR
13441    {1, 16},  	// GPRwithAPSR
13442    {1, 16},  	// SPR_8
13443    {1, 15},  	// GPRnopc
13444    {1, 14},  	// rGPR
13445    {1, 9},  	// tGPRwithpc
13446    {1, 8},  	// hGPR
13447    {1, 8},  	// tGPR
13448    {1, 7},  	// GPRnopc_and_hGPR
13449    {1, 6},  	// hGPR_and_rGPR
13450    {1, 5},  	// tcGPR
13451    {1, 4},  	// tGPR_and_tcGPR
13452    {0, 0},  	// CCR
13453    {1, 1},  	// GPRsp
13454    {1, 1},  	// hGPR_and_tGPRwithpc
13455    {1, 1},  	// hGPR_and_tcGPR
13456    {2, 64},  	// DPR
13457    {2, 32},  	// DPR_VFP2
13458    {2, 16},  	// DPR_8
13459    {2, 14},  	// GPRPair
13460    {2, 12},  	// GPRPair_with_gsub_1_in_rGPR
13461    {2, 8},  	// GPRPair_with_gsub_0_in_tGPR
13462    {2, 6},  	// GPRPair_with_gsub_0_in_hGPR
13463    {2, 6},  	// GPRPair_with_gsub_0_in_tcGPR
13464    {2, 4},  	// GPRPair_with_gsub_1_in_hGPR_and_rGPR
13465    {2, 4},  	// GPRPair_with_gsub_1_in_tcGPR
13466    {2, 2},  	// GPRPair_with_gsub_1_in_GPRsp
13467    {4, 64},  	// DPairSpc
13468    {4, 36},  	// DPairSpc_with_ssub_0
13469    {4, 32},  	// DPairSpc_with_ssub_4
13470    {4, 20},  	// DPairSpc_with_dsub_0_in_DPR_8
13471    {4, 16},  	// DPairSpc_with_dsub_2_in_DPR_8
13472    {4, 64},  	// DPair
13473    {4, 34},  	// DPair_with_ssub_0
13474    {4, 64},  	// QPR
13475    {4, 32},  	// DPair_with_ssub_2
13476    {4, 18},  	// DPair_with_dsub_0_in_DPR_8
13477    {4, 32},  	// QPR_VFP2
13478    {4, 16},  	// DPair_with_dsub_1_in_DPR_8
13479    {4, 16},  	// QPR_8
13480    {6, 64},  	// DTriple
13481    {6, 64},  	// DTripleSpc
13482    {6, 40},  	// DTripleSpc_with_ssub_0
13483    {6, 36},  	// DTriple_with_ssub_0
13484    {6, 62},  	// DTriple_with_qsub_0_in_QPR
13485    {6, 34},  	// DTriple_with_ssub_2
13486    {6, 62},  	// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13487    {6, 36},  	// DTripleSpc_with_ssub_4
13488    {6, 32},  	// DTriple_with_ssub_4
13489    {6, 32},  	// DTripleSpc_with_ssub_8
13490    {6, 24},  	// DTripleSpc_with_dsub_0_in_DPR_8
13491    {6, 20},  	// DTriple_with_dsub_0_in_DPR_8
13492    {6, 34},  	// DTriple_with_qsub_0_in_QPR_VFP2
13493    {6, 34},  	// DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13494    {6, 18},  	// DTriple_with_dsub_1_in_DPR_8
13495    {6, 30},  	// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
13496    {6, 30},  	// DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
13497    {6, 20},  	// DTripleSpc_with_dsub_2_in_DPR_8
13498    {6, 16},  	// DTriple_with_dsub_2_in_DPR_8
13499    {6, 16},  	// DTripleSpc_with_dsub_4_in_DPR_8
13500    {6, 18},  	// DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13501    {6, 18},  	// DTriple_with_qsub_0_in_QPR_8
13502    {6, 14},  	// DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
13503    {6, 14},  	// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
13504    {6, 64},  	// DQuadSpc
13505    {6, 40},  	// DQuadSpc_with_ssub_0
13506    {6, 36},  	// DQuadSpc_with_ssub_4
13507    {6, 32},  	// DQuadSpc_with_ssub_8
13508    {6, 24},  	// DQuadSpc_with_dsub_0_in_DPR_8
13509    {6, 20},  	// DQuadSpc_with_dsub_2_in_DPR_8
13510    {6, 16},  	// DQuadSpc_with_dsub_4_in_DPR_8
13511    {8, 64},  	// DQuad
13512    {8, 38},  	// DQuad_with_ssub_0
13513    {8, 36},  	// DQuad_with_ssub_2
13514    {8, 64},  	// QQPR
13515    {8, 60},  	// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13516    {8, 34},  	// DQuad_with_ssub_4
13517    {8, 32},  	// DQuad_with_ssub_6
13518    {8, 22},  	// DQuad_with_dsub_0_in_DPR_8
13519    {8, 36},  	// DQuad_with_qsub_0_in_QPR_VFP2
13520    {8, 36},  	// DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13521    {8, 20},  	// DQuad_with_dsub_1_in_DPR_8
13522    {8, 32},  	// DQuad_with_qsub_1_in_QPR_VFP2
13523    {8, 32},  	// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
13524    {8, 18},  	// DQuad_with_dsub_2_in_DPR_8
13525    {8, 28},  	// DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13526    {8, 16},  	// DQuad_with_dsub_3_in_DPR_8
13527    {8, 20},  	// DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13528    {8, 20},  	// DQuad_with_qsub_0_in_QPR_8
13529    {8, 16},  	// DQuad_with_qsub_1_in_QPR_8
13530    {8, 16},  	// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
13531    {8, 12},  	// DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13532    {16, 64},  	// QQQQPR
13533    {16, 44},  	// QQQQPR_with_ssub_0
13534    {16, 40},  	// QQQQPR_with_ssub_4
13535    {16, 36},  	// QQQQPR_with_ssub_8
13536    {16, 32},  	// QQQQPR_with_ssub_12
13537    {16, 28},  	// QQQQPR_with_dsub_0_in_DPR_8
13538    {16, 24},  	// QQQQPR_with_dsub_2_in_DPR_8
13539    {16, 20},  	// QQQQPR_with_dsub_4_in_DPR_8
13540    {16, 16},  	// QQQQPR_with_dsub_6_in_DPR_8
13541  };
13542  return RCWeightTable[RC->getID()];
13543}
13544
13545/// Get the weight in units of pressure for this register unit.
13546unsigned ARMGenRegisterInfo::
13547getRegUnitWeight(unsigned RegUnit) const {
13548  assert(RegUnit < 77 && "invalid register unit");
13549  static const uint8_t RUWeightTable[] = {
13550    0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
13551  return RUWeightTable[RegUnit];
13552}
13553
13554
13555// Get the number of dimensions of register pressure.
13556unsigned ARMGenRegisterInfo::getNumRegPressureSets() const {
13557  return 21;
13558}
13559
13560// Get the name of this register unit pressure set.
13561const char *ARMGenRegisterInfo::
13562getRegPressureSetName(unsigned Idx) const {
13563  static const char *const PressureNameTable[] = {
13564    "hGPR_and_tGPRwithpc",
13565    "GPRsp",
13566    "tcGPR",
13567    "hGPR",
13568    "tGPR",
13569    "hGPR+tcGPR",
13570    "GPR",
13571    "DQuad_with_dsub_0_in_DPR_8",
13572    "DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2",
13573    "HPR",
13574    "DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR",
13575    "DPair_with_ssub_0",
13576    "DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR",
13577    "DPairSpc_with_ssub_0",
13578    "DQuad_with_ssub_0",
13579    "DTripleSpc_with_ssub_0",
13580    "QQQQPR_with_ssub_0",
13581    "DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR",
13582    "DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR",
13583    "DTriple_with_qsub_0_in_QPR",
13584    "DPR",
13585  };
13586  return PressureNameTable[Idx];
13587}
13588
13589// Get the register unit pressure limit for this dimension.
13590// This limit must be adjusted dynamically for reserved registers.
13591unsigned ARMGenRegisterInfo::
13592getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
13593  static const uint8_t PressureLimitTable[] = {
13594    1,  	// 0: hGPR_and_tGPRwithpc
13595    2,  	// 1: GPRsp
13596    6,  	// 2: tcGPR
13597    8,  	// 3: hGPR
13598    11,  	// 4: tGPR
13599    12,  	// 5: hGPR+tcGPR
13600    17,  	// 6: GPR
13601    24,  	// 7: DQuad_with_dsub_0_in_DPR_8
13602    32,  	// 8: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
13603    32,  	// 9: HPR
13604    34,  	// 10: DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13605    34,  	// 11: DPair_with_ssub_0
13606    36,  	// 12: DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13607    36,  	// 13: DPairSpc_with_ssub_0
13608    38,  	// 14: DQuad_with_ssub_0
13609    40,  	// 15: DTripleSpc_with_ssub_0
13610    44,  	// 16: QQQQPR_with_ssub_0
13611    60,  	// 17: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13612    62,  	// 18: DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
13613    62,  	// 19: DTriple_with_qsub_0_in_QPR
13614    64,  	// 20: DPR
13615  };
13616  return PressureLimitTable[Idx];
13617}
13618
13619/// Table of pressure sets per register class or unit.
13620static const int RCSetsTable[] = {
13621  /* 0 */ 4, 6, -1,
13622  /* 3 */ 3, 5, 6, -1,
13623  /* 7 */ 2, 4, 5, 6, -1,
13624  /* 12 */ 0, 3, 4, 5, 6, -1,
13625  /* 18 */ 1, 2, 3, 4, 5, 6, -1,
13626  /* 25 */ 18, 20, -1,
13627  /* 28 */ 7, 9, 11, 13, 14, 15, 16, 19, 20, -1,
13628  /* 38 */ 12, 14, 15, 16, 17, 18, 19, 20, -1,
13629  /* 47 */ 10, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1,
13630  /* 58 */ 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1,
13631  /* 71 */ 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1,
13632};
13633
13634/// Get the dimensions of register pressure impacted by this register class.
13635/// Returns a -1 terminated array of pressure set IDs
13636const int* ARMGenRegisterInfo::
13637getRegClassPressureSets(const TargetRegisterClass *RC) const {
13638  static const uint8_t RCSetStartTable[] = {
13639    29,29,1,1,28,1,1,0,3,0,3,3,7,7,2,18,12,18,26,29,28,1,1,0,3,7,3,7,18,26,31,29,28,28,26,30,26,29,28,29,28,28,26,26,33,31,35,30,25,31,29,29,28,28,30,47,28,72,29,28,28,28,71,28,28,71,26,33,31,29,28,28,28,26,32,31,26,42,30,29,28,31,38,28,29,58,28,72,28,71,28,28,71,71,26,34,33,31,29,29,28,28,28,};
13640  return &RCSetsTable[RCSetStartTable[RC->getID()]];
13641}
13642
13643/// Get the dimensions of register pressure impacted by this register unit.
13644/// Returns a -1 terminated array of pressure set IDs
13645const int* ARMGenRegisterInfo::
13646getRegUnitPressureSets(unsigned RegUnit) const {
13647  assert(RegUnit < 77 && "invalid register unit");
13648  static const uint8_t RUSetStartTable[] = {
13649    2,1,2,2,2,2,2,2,3,12,18,2,28,28,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,72,72,72,72,72,72,72,72,58,47,38,40,41,41,42,42,42,42,42,42,42,42,42,25,2,2,2,2,7,7,7,7,0,0,0,0,3,3,3,3,18,};
13650  return &RCSetsTable[RUSetStartTable[RegUnit]];
13651}
13652
13653extern const MCRegisterDesc ARMRegDesc[];
13654extern const MCPhysReg ARMRegDiffLists[];
13655extern const LaneBitmask ARMLaneMaskLists[];
13656extern const char ARMRegStrings[];
13657extern const char ARMRegClassStrings[];
13658extern const MCPhysReg ARMRegUnitRoots[][2];
13659extern const uint16_t ARMSubRegIdxLists[];
13660extern const MCRegisterInfo::SubRegCoveredBits ARMSubRegIdxRanges[];
13661extern const uint16_t ARMRegEncodingTable[];
13662// ARM Dwarf<->LLVM register mappings.
13663extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0Dwarf2L[];
13664extern const unsigned ARMDwarfFlavour0Dwarf2LSize;
13665
13666extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0Dwarf2L[];
13667extern const unsigned ARMEHFlavour0Dwarf2LSize;
13668
13669extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0L2Dwarf[];
13670extern const unsigned ARMDwarfFlavour0L2DwarfSize;
13671
13672extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0L2Dwarf[];
13673extern const unsigned ARMEHFlavour0L2DwarfSize;
13674
13675ARMGenRegisterInfo::
13676ARMGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
13677      unsigned PC, unsigned HwMode)
13678  : TargetRegisterInfo(ARMRegInfoDesc, RegisterClasses, RegisterClasses+103,
13679             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
13680             LaneBitmask(0xFFFFFFFF), RegClassInfos, HwMode) {
13681  InitMCRegisterInfo(ARMRegDesc, 289, RA, PC,
13682                     ARMMCRegisterClasses, 103,
13683                     ARMRegUnitRoots,
13684                     77,
13685                     ARMRegDiffLists,
13686                     ARMLaneMaskLists,
13687                     ARMRegStrings,
13688                     ARMRegClassStrings,
13689                     ARMSubRegIdxLists,
13690                     57,
13691                     ARMSubRegIdxRanges,
13692                     ARMRegEncodingTable);
13693
13694  switch (DwarfFlavour) {
13695  default:
13696    llvm_unreachable("Unknown DWARF flavour");
13697  case 0:
13698    mapDwarfRegsToLLVMRegs(ARMDwarfFlavour0Dwarf2L, ARMDwarfFlavour0Dwarf2LSize, false);
13699    break;
13700  }
13701  switch (EHFlavour) {
13702  default:
13703    llvm_unreachable("Unknown DWARF flavour");
13704  case 0:
13705    mapDwarfRegsToLLVMRegs(ARMEHFlavour0Dwarf2L, ARMEHFlavour0Dwarf2LSize, true);
13706    break;
13707  }
13708  switch (DwarfFlavour) {
13709  default:
13710    llvm_unreachable("Unknown DWARF flavour");
13711  case 0:
13712    mapLLVMRegsToDwarfRegs(ARMDwarfFlavour0L2Dwarf, ARMDwarfFlavour0L2DwarfSize, false);
13713    break;
13714  }
13715  switch (EHFlavour) {
13716  default:
13717    llvm_unreachable("Unknown DWARF flavour");
13718  case 0:
13719    mapLLVMRegsToDwarfRegs(ARMEHFlavour0L2Dwarf, ARMEHFlavour0L2DwarfSize, true);
13720    break;
13721  }
13722}
13723
13724static const MCPhysReg CSR_AAPCS_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
13725static const uint32_t CSR_AAPCS_RegMask[] = { 0x3fc00400, 0x03c00000, 0x80003fc0, 0x1f807fff, 0x000e0000, 0x3f00f001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
13726static const MCPhysReg CSR_AAPCS_SplitPush_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
13727static const uint32_t CSR_AAPCS_SplitPush_RegMask[] = { 0x3fc00400, 0x03c00000, 0x80003fc0, 0x1f807fff, 0x000e0000, 0x3f00f001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
13728static const MCPhysReg CSR_AAPCS_SplitPush_SwiftError_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R9, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
13729static const uint32_t CSR_AAPCS_SplitPush_SwiftError_RegMask[] = { 0x3fc00400, 0x03c00000, 0x80003bc0, 0x1f807fff, 0x000e0000, 0x3f00b001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
13730static const MCPhysReg CSR_AAPCS_SwiftError_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
13731static const uint32_t CSR_AAPCS_SwiftError_RegMask[] = { 0x3fc00400, 0x03c00000, 0x80003bc0, 0x1f807fff, 0x000e0000, 0x3f00b001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
13732static const MCPhysReg CSR_AAPCS_ThisReturn_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R0, 0 };
13733static const uint32_t CSR_AAPCS_ThisReturn_RegMask[] = { 0x3fc00400, 0x03c00000, 0x80003fc4, 0x1f807fff, 0x000e0000, 0x3f00f001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
13734static const MCPhysReg CSR_FIQ_SaveList[] = { ARM::LR, ARM::R11, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::R0, 0 };
13735static const uint32_t CSR_FIQ_RegMask[] = { 0x00000400, 0x00000000, 0x000023fc, 0x00000000, 0x00000000, 0x00003c00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13736static const MCPhysReg CSR_FPRegs_SaveList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, 0 };
13737static const uint32_t CSR_FPRegs_RegMask[] = { 0xffffc000, 0xfffc3fff, 0xffff8003, 0xffffffff, 0xffffffff, 0xffff01ff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000001, };
13738static const MCPhysReg CSR_GenericInt_SaveList[] = { ARM::LR, ARM::R12, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::R0, 0 };
13739static const uint32_t CSR_GenericInt_RegMask[] = { 0x00000400, 0x00000000, 0x00007ffc, 0x00000000, 0x00000000, 0x0000fc00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13740static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
13741static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13742static const MCPhysReg CSR_iOS_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
13743static const uint32_t CSR_iOS_RegMask[] = { 0x3fc00400, 0x03c00000, 0x800037c0, 0x1f807fff, 0x000e0000, 0x3f00b001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
13744static const MCPhysReg CSR_iOS_CXX_TLS_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R12, ARM::R9, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
13745static const uint32_t CSR_iOS_CXX_TLS_RegMask[] = { 0xffffc400, 0xfffc3fff, 0xfffffffb, 0xffffffff, 0xffffffff, 0xfffff9ff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000001, };
13746static const MCPhysReg CSR_iOS_CXX_TLS_PE_SaveList[] = { ARM::LR, ARM::R12, ARM::R11, ARM::R7, ARM::R5, ARM::R4, 0 };
13747static const uint32_t CSR_iOS_CXX_TLS_PE_RegMask[] = { 0x00000400, 0x00000000, 0x000062c0, 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13748static const MCPhysReg CSR_iOS_CXX_TLS_ViaCopy_SaveList[] = { ARM::R6, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R9, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
13749static const uint32_t CSR_iOS_CXX_TLS_ViaCopy_RegMask[] = { 0xffffc000, 0xfffc3fff, 0xffff9d3b, 0xffffffff, 0xffffffff, 0xffff49ff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000001, };
13750static const MCPhysReg CSR_iOS_SwiftError_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
13751static const uint32_t CSR_iOS_SwiftError_RegMask[] = { 0x3fc00400, 0x03c00000, 0x800033c0, 0x1f807fff, 0x000e0000, 0x3f00b001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
13752static const MCPhysReg CSR_iOS_TLSCall_SaveList[] = { ARM::LR, ARM::SP, ARM::R11, ARM::R10, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
13753static const uint32_t CSR_iOS_TLSCall_RegMask[] = { 0xffffd400, 0xfffc3fff, 0xffffb7fb, 0xffffffff, 0xffffffff, 0xffffb9ff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000001, };
13754static const MCPhysReg CSR_iOS_ThisReturn_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R0, 0 };
13755static const uint32_t CSR_iOS_ThisReturn_RegMask[] = { 0x3fc00400, 0x03c00000, 0x800037c4, 0x1f807fff, 0x000e0000, 0x3f00b001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
13756
13757
13758ArrayRef<const uint32_t *> ARMGenRegisterInfo::getRegMasks() const {
13759  static const uint32_t *const Masks[] = {
13760    CSR_AAPCS_RegMask,
13761    CSR_AAPCS_SplitPush_RegMask,
13762    CSR_AAPCS_SplitPush_SwiftError_RegMask,
13763    CSR_AAPCS_SwiftError_RegMask,
13764    CSR_AAPCS_ThisReturn_RegMask,
13765    CSR_FIQ_RegMask,
13766    CSR_FPRegs_RegMask,
13767    CSR_GenericInt_RegMask,
13768    CSR_NoRegs_RegMask,
13769    CSR_iOS_RegMask,
13770    CSR_iOS_CXX_TLS_RegMask,
13771    CSR_iOS_CXX_TLS_PE_RegMask,
13772    CSR_iOS_CXX_TLS_ViaCopy_RegMask,
13773    CSR_iOS_SwiftError_RegMask,
13774    CSR_iOS_TLSCall_RegMask,
13775    CSR_iOS_ThisReturn_RegMask,
13776  };
13777  return makeArrayRef(Masks);
13778}
13779
13780ArrayRef<const char *> ARMGenRegisterInfo::getRegMaskNames() const {
13781  static const char *const Names[] = {
13782    "CSR_AAPCS",
13783    "CSR_AAPCS_SplitPush",
13784    "CSR_AAPCS_SplitPush_SwiftError",
13785    "CSR_AAPCS_SwiftError",
13786    "CSR_AAPCS_ThisReturn",
13787    "CSR_FIQ",
13788    "CSR_FPRegs",
13789    "CSR_GenericInt",
13790    "CSR_NoRegs",
13791    "CSR_iOS",
13792    "CSR_iOS_CXX_TLS",
13793    "CSR_iOS_CXX_TLS_PE",
13794    "CSR_iOS_CXX_TLS_ViaCopy",
13795    "CSR_iOS_SwiftError",
13796    "CSR_iOS_TLSCall",
13797    "CSR_iOS_ThisReturn",
13798  };
13799  return makeArrayRef(Names);
13800}
13801
13802const ARMFrameLowering *
13803ARMGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
13804  return static_cast<const ARMFrameLowering *>(
13805      MF.getSubtarget().getFrameLowering());
13806}
13807
13808} // end namespace llvm
13809
13810#endif // GET_REGINFO_TARGET_DESC
13811
13812