1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "AArch64TargetMachine.h"
14 #include "AArch64.h"
15 #include "AArch64MacroFusion.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64TargetObjectFile.h"
18 #include "AArch64TargetTransformInfo.h"
19 #include "MCTargetDesc/AArch64MCTargetDesc.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
24 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
25 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
26 #include "llvm/CodeGen/GlobalISel/Localizer.h"
27 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
28 #include "llvm/CodeGen/MachineScheduler.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/CodeGen/TargetPassConfig.h"
31 #include "llvm/IR/Attributes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/MC/MCTargetOptions.h"
34 #include "llvm/Pass.h"
35 #include "llvm/Support/CodeGen.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Target/TargetLoweringObjectFile.h"
39 #include "llvm/Target/TargetOptions.h"
40 #include "llvm/Transforms/Scalar.h"
41 #include <memory>
42 #include <string>
43
44 using namespace llvm;
45
46 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
47 cl::desc("Enable the CCMP formation pass"),
48 cl::init(true), cl::Hidden);
49
50 static cl::opt<bool>
51 EnableCondBrTuning("aarch64-enable-cond-br-tune",
52 cl::desc("Enable the conditional branch tuning pass"),
53 cl::init(true), cl::Hidden);
54
55 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
56 cl::desc("Enable the machine combiner pass"),
57 cl::init(true), cl::Hidden);
58
59 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
60 cl::desc("Suppress STP for AArch64"),
61 cl::init(true), cl::Hidden);
62
63 static cl::opt<bool> EnableAdvSIMDScalar(
64 "aarch64-enable-simd-scalar",
65 cl::desc("Enable use of AdvSIMD scalar integer instructions"),
66 cl::init(false), cl::Hidden);
67
68 static cl::opt<bool>
69 EnablePromoteConstant("aarch64-enable-promote-const",
70 cl::desc("Enable the promote constant pass"),
71 cl::init(true), cl::Hidden);
72
73 static cl::opt<bool> EnableCollectLOH(
74 "aarch64-enable-collect-loh",
75 cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
76 cl::init(true), cl::Hidden);
77
78 static cl::opt<bool>
79 EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
80 cl::desc("Enable the pass that removes dead"
81 " definitons and replaces stores to"
82 " them with stores to the zero"
83 " register"),
84 cl::init(true));
85
86 static cl::opt<bool> EnableRedundantCopyElimination(
87 "aarch64-enable-copyelim",
88 cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
89 cl::Hidden);
90
91 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
92 cl::desc("Enable the load/store pair"
93 " optimization pass"),
94 cl::init(true), cl::Hidden);
95
96 static cl::opt<bool> EnableAtomicTidy(
97 "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
98 cl::desc("Run SimplifyCFG after expanding atomic operations"
99 " to make use of cmpxchg flow-based information"),
100 cl::init(true));
101
102 static cl::opt<bool>
103 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
104 cl::desc("Run early if-conversion"),
105 cl::init(true));
106
107 static cl::opt<bool>
108 EnableCondOpt("aarch64-enable-condopt",
109 cl::desc("Enable the condition optimizer pass"),
110 cl::init(true), cl::Hidden);
111
112 static cl::opt<bool>
113 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
114 cl::desc("Work around Cortex-A53 erratum 835769"),
115 cl::init(false));
116
117 static cl::opt<bool>
118 EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
119 cl::desc("Enable optimizations on complex GEPs"),
120 cl::init(false));
121
122 static cl::opt<bool>
123 BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
124 cl::desc("Relax out of range conditional branches"));
125
126 // FIXME: Unify control over GlobalMerge.
127 static cl::opt<cl::boolOrDefault>
128 EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
129 cl::desc("Enable the global merge pass"));
130
131 static cl::opt<bool>
132 EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
133 cl::desc("Enable the loop data prefetch pass"),
134 cl::init(true));
135
136 static cl::opt<int> EnableGlobalISelAtO(
137 "aarch64-enable-global-isel-at-O", cl::Hidden,
138 cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
139 cl::init(0));
140
141 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
142 cl::init(true), cl::Hidden);
143
LLVMInitializeAArch64Target()144 extern "C" void LLVMInitializeAArch64Target() {
145 // Register the target.
146 RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
147 RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
148 RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
149 auto PR = PassRegistry::getPassRegistry();
150 initializeGlobalISel(*PR);
151 initializeAArch64A53Fix835769Pass(*PR);
152 initializeAArch64A57FPLoadBalancingPass(*PR);
153 initializeAArch64AdvSIMDScalarPass(*PR);
154 initializeAArch64CollectLOHPass(*PR);
155 initializeAArch64ConditionalComparesPass(*PR);
156 initializeAArch64ConditionOptimizerPass(*PR);
157 initializeAArch64DeadRegisterDefinitionsPass(*PR);
158 initializeAArch64ExpandPseudoPass(*PR);
159 initializeAArch64LoadStoreOptPass(*PR);
160 initializeAArch64SIMDInstrOptPass(*PR);
161 initializeAArch64PromoteConstantPass(*PR);
162 initializeAArch64RedundantCopyEliminationPass(*PR);
163 initializeAArch64StorePairSuppressPass(*PR);
164 initializeFalkorHWPFFixPass(*PR);
165 initializeFalkorMarkStridedAccessesLegacyPass(*PR);
166 initializeLDTLSCleanupPass(*PR);
167 }
168
169 //===----------------------------------------------------------------------===//
170 // AArch64 Lowering public interface.
171 //===----------------------------------------------------------------------===//
createTLOF(const Triple & TT)172 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
173 if (TT.isOSBinFormatMachO())
174 return llvm::make_unique<AArch64_MachoTargetObjectFile>();
175 if (TT.isOSBinFormatCOFF())
176 return llvm::make_unique<AArch64_COFFTargetObjectFile>();
177
178 return llvm::make_unique<AArch64_ELFTargetObjectFile>();
179 }
180
181 // Helper function to build a DataLayout string
computeDataLayout(const Triple & TT,const MCTargetOptions & Options,bool LittleEndian)182 static std::string computeDataLayout(const Triple &TT,
183 const MCTargetOptions &Options,
184 bool LittleEndian) {
185 if (Options.getABIName() == "ilp32")
186 return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
187 if (TT.isOSBinFormatMachO())
188 return "e-m:o-i64:64-i128:128-n32:64-S128";
189 if (TT.isOSBinFormatCOFF())
190 return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
191 if (LittleEndian)
192 return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
193 return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
194 }
195
getEffectiveRelocModel(const Triple & TT,Optional<Reloc::Model> RM)196 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
197 Optional<Reloc::Model> RM) {
198 // AArch64 Darwin is always PIC.
199 if (TT.isOSDarwin())
200 return Reloc::PIC_;
201 // On ELF platforms the default static relocation model has a smart enough
202 // linker to cope with referencing external symbols defined in a shared
203 // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
204 if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
205 return Reloc::Static;
206 return *RM;
207 }
208
getEffectiveCodeModel(const Triple & TT,Optional<CodeModel::Model> CM,bool JIT)209 static CodeModel::Model getEffectiveCodeModel(const Triple &TT,
210 Optional<CodeModel::Model> CM,
211 bool JIT) {
212 if (CM) {
213 if (*CM != CodeModel::Small && *CM != CodeModel::Large) {
214 if (!TT.isOSFuchsia())
215 report_fatal_error(
216 "Only small and large code models are allowed on AArch64");
217 else if (CM != CodeModel::Kernel)
218 report_fatal_error(
219 "Only small, kernel, and large code models are allowed on AArch64");
220 }
221 return *CM;
222 }
223 // The default MCJIT memory managers make no guarantees about where they can
224 // find an executable page; JITed code needs to be able to refer to globals
225 // no matter how far away they are.
226 if (JIT)
227 return CodeModel::Large;
228 return CodeModel::Small;
229 }
230
231 /// Create an AArch64 architecture model.
232 ///
AArch64TargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT,bool LittleEndian)233 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
234 StringRef CPU, StringRef FS,
235 const TargetOptions &Options,
236 Optional<Reloc::Model> RM,
237 Optional<CodeModel::Model> CM,
238 CodeGenOpt::Level OL, bool JIT,
239 bool LittleEndian)
240 : LLVMTargetMachine(T,
241 computeDataLayout(TT, Options.MCOptions, LittleEndian),
242 TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM),
243 getEffectiveCodeModel(TT, CM, JIT), OL),
244 TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
245 initAsmInfo();
246
247 if (TT.isOSBinFormatMachO()) {
248 this->Options.TrapUnreachable = true;
249 this->Options.NoTrapAfterNoreturn = true;
250 }
251
252 // Enable GlobalISel at or below EnableGlobalISelAt0.
253 if (getOptLevel() <= EnableGlobalISelAtO)
254 setGlobalISel(true);
255
256 // AArch64 supports the MachineOutliner.
257 setMachineOutliner(true);
258
259 // AArch64 supports default outlining behaviour.
260 setSupportsDefaultOutlining(true);
261 }
262
263 AArch64TargetMachine::~AArch64TargetMachine() = default;
264
265 const AArch64Subtarget *
getSubtargetImpl(const Function & F) const266 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
267 Attribute CPUAttr = F.getFnAttribute("target-cpu");
268 Attribute FSAttr = F.getFnAttribute("target-features");
269
270 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
271 ? CPUAttr.getValueAsString().str()
272 : TargetCPU;
273 std::string FS = !FSAttr.hasAttribute(Attribute::None)
274 ? FSAttr.getValueAsString().str()
275 : TargetFS;
276
277 auto &I = SubtargetMap[CPU + FS];
278 if (!I) {
279 // This needs to be done before we create a new subtarget since any
280 // creation will depend on the TM and the code generation flags on the
281 // function that reside in TargetOptions.
282 resetTargetOptions(F);
283 I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
284 isLittle);
285 }
286 return I.get();
287 }
288
anchor()289 void AArch64leTargetMachine::anchor() { }
290
AArch64leTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT)291 AArch64leTargetMachine::AArch64leTargetMachine(
292 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
293 const TargetOptions &Options, Optional<Reloc::Model> RM,
294 Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
295 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
296
anchor()297 void AArch64beTargetMachine::anchor() { }
298
AArch64beTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT)299 AArch64beTargetMachine::AArch64beTargetMachine(
300 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
301 const TargetOptions &Options, Optional<Reloc::Model> RM,
302 Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
303 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
304
305 namespace {
306
307 /// AArch64 Code Generator Pass Configuration Options.
308 class AArch64PassConfig : public TargetPassConfig {
309 public:
AArch64PassConfig(AArch64TargetMachine & TM,PassManagerBase & PM)310 AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
311 : TargetPassConfig(TM, PM) {
312 if (TM.getOptLevel() != CodeGenOpt::None)
313 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
314 }
315
getAArch64TargetMachine() const316 AArch64TargetMachine &getAArch64TargetMachine() const {
317 return getTM<AArch64TargetMachine>();
318 }
319
320 ScheduleDAGInstrs *
createMachineScheduler(MachineSchedContext * C) const321 createMachineScheduler(MachineSchedContext *C) const override {
322 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
323 ScheduleDAGMILive *DAG = createGenericSchedLive(C);
324 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
325 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
326 if (ST.hasFusion())
327 DAG->addMutation(createAArch64MacroFusionDAGMutation());
328 return DAG;
329 }
330
331 ScheduleDAGInstrs *
createPostMachineScheduler(MachineSchedContext * C) const332 createPostMachineScheduler(MachineSchedContext *C) const override {
333 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
334 if (ST.hasFusion()) {
335 // Run the Macro Fusion after RA again since literals are expanded from
336 // pseudos then (v. addPreSched2()).
337 ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
338 DAG->addMutation(createAArch64MacroFusionDAGMutation());
339 return DAG;
340 }
341
342 return nullptr;
343 }
344
345 void addIRPasses() override;
346 bool addPreISel() override;
347 bool addInstSelector() override;
348 bool addIRTranslator() override;
349 bool addLegalizeMachineIR() override;
350 bool addRegBankSelect() override;
351 void addPreGlobalInstructionSelect() override;
352 bool addGlobalInstructionSelect() override;
353 bool addILPOpts() override;
354 void addPreRegAlloc() override;
355 void addPostRegAlloc() override;
356 void addPreSched2() override;
357 void addPreEmitPass() override;
358 };
359
360 } // end anonymous namespace
361
362 TargetTransformInfo
getTargetTransformInfo(const Function & F)363 AArch64TargetMachine::getTargetTransformInfo(const Function &F) {
364 return TargetTransformInfo(AArch64TTIImpl(this, F));
365 }
366
createPassConfig(PassManagerBase & PM)367 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
368 return new AArch64PassConfig(*this, PM);
369 }
370
addIRPasses()371 void AArch64PassConfig::addIRPasses() {
372 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
373 // ourselves.
374 addPass(createAtomicExpandPass());
375
376 // Cmpxchg instructions are often used with a subsequent comparison to
377 // determine whether it succeeded. We can exploit existing control-flow in
378 // ldrex/strex loops to simplify this, but it needs tidying up.
379 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
380 addPass(createCFGSimplificationPass(1, true, true, false, true));
381
382 // Run LoopDataPrefetch
383 //
384 // Run this before LSR to remove the multiplies involved in computing the
385 // pointer values N iterations ahead.
386 if (TM->getOptLevel() != CodeGenOpt::None) {
387 if (EnableLoopDataPrefetch)
388 addPass(createLoopDataPrefetchPass());
389 if (EnableFalkorHWPFFix)
390 addPass(createFalkorMarkStridedAccessesPass());
391 }
392
393 TargetPassConfig::addIRPasses();
394
395 // Match interleaved memory accesses to ldN/stN intrinsics.
396 if (TM->getOptLevel() != CodeGenOpt::None)
397 addPass(createInterleavedAccessPass());
398
399 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
400 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
401 // and lower a GEP with multiple indices to either arithmetic operations or
402 // multiple GEPs with single index.
403 addPass(createSeparateConstOffsetFromGEPPass(true));
404 // Call EarlyCSE pass to find and remove subexpressions in the lowered
405 // result.
406 addPass(createEarlyCSEPass());
407 // Do loop invariant code motion in case part of the lowered result is
408 // invariant.
409 addPass(createLICMPass());
410 }
411 }
412
413 // Pass Pipeline Configuration
addPreISel()414 bool AArch64PassConfig::addPreISel() {
415 // Run promote constant before global merge, so that the promoted constants
416 // get a chance to be merged
417 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
418 addPass(createAArch64PromoteConstantPass());
419 // FIXME: On AArch64, this depends on the type.
420 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
421 // and the offset has to be a multiple of the related size in bytes.
422 if ((TM->getOptLevel() != CodeGenOpt::None &&
423 EnableGlobalMerge == cl::BOU_UNSET) ||
424 EnableGlobalMerge == cl::BOU_TRUE) {
425 bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
426 (EnableGlobalMerge == cl::BOU_UNSET);
427 addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize));
428 }
429
430 return false;
431 }
432
addInstSelector()433 bool AArch64PassConfig::addInstSelector() {
434 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
435
436 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
437 // references to _TLS_MODULE_BASE_ as possible.
438 if (TM->getTargetTriple().isOSBinFormatELF() &&
439 getOptLevel() != CodeGenOpt::None)
440 addPass(createAArch64CleanupLocalDynamicTLSPass());
441
442 return false;
443 }
444
addIRTranslator()445 bool AArch64PassConfig::addIRTranslator() {
446 addPass(new IRTranslator());
447 return false;
448 }
449
addLegalizeMachineIR()450 bool AArch64PassConfig::addLegalizeMachineIR() {
451 addPass(new Legalizer());
452 return false;
453 }
454
addRegBankSelect()455 bool AArch64PassConfig::addRegBankSelect() {
456 addPass(new RegBankSelect());
457 return false;
458 }
459
addPreGlobalInstructionSelect()460 void AArch64PassConfig::addPreGlobalInstructionSelect() {
461 // Workaround the deficiency of the fast register allocator.
462 if (TM->getOptLevel() == CodeGenOpt::None)
463 addPass(new Localizer());
464 }
465
addGlobalInstructionSelect()466 bool AArch64PassConfig::addGlobalInstructionSelect() {
467 addPass(new InstructionSelect());
468 return false;
469 }
470
addILPOpts()471 bool AArch64PassConfig::addILPOpts() {
472 if (EnableCondOpt)
473 addPass(createAArch64ConditionOptimizerPass());
474 if (EnableCCMP)
475 addPass(createAArch64ConditionalCompares());
476 if (EnableMCR)
477 addPass(&MachineCombinerID);
478 if (EnableCondBrTuning)
479 addPass(createAArch64CondBrTuning());
480 if (EnableEarlyIfConversion)
481 addPass(&EarlyIfConverterID);
482 if (EnableStPairSuppress)
483 addPass(createAArch64StorePairSuppressPass());
484 addPass(createAArch64SIMDInstrOptPass());
485 return true;
486 }
487
addPreRegAlloc()488 void AArch64PassConfig::addPreRegAlloc() {
489 // Change dead register definitions to refer to the zero register.
490 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
491 addPass(createAArch64DeadRegisterDefinitions());
492
493 // Use AdvSIMD scalar instructions whenever profitable.
494 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
495 addPass(createAArch64AdvSIMDScalar());
496 // The AdvSIMD pass may produce copies that can be rewritten to
497 // be register coaleascer friendly.
498 addPass(&PeepholeOptimizerID);
499 }
500 }
501
addPostRegAlloc()502 void AArch64PassConfig::addPostRegAlloc() {
503 // Remove redundant copy instructions.
504 if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
505 addPass(createAArch64RedundantCopyEliminationPass());
506
507 if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
508 // Improve performance for some FP/SIMD code for A57.
509 addPass(createAArch64A57FPLoadBalancing());
510 }
511
addPreSched2()512 void AArch64PassConfig::addPreSched2() {
513 // Expand some pseudo instructions to allow proper scheduling.
514 addPass(createAArch64ExpandPseudoPass());
515 // Use load/store pair instructions when possible.
516 if (TM->getOptLevel() != CodeGenOpt::None) {
517 if (EnableLoadStoreOpt)
518 addPass(createAArch64LoadStoreOptimizationPass());
519 if (EnableFalkorHWPFFix)
520 addPass(createFalkorHWPFFixPass());
521 }
522 }
523
addPreEmitPass()524 void AArch64PassConfig::addPreEmitPass() {
525 if (EnableA53Fix835769)
526 addPass(createAArch64A53Fix835769());
527 // Relax conditional branch instructions if they're otherwise out of
528 // range of their destination.
529 if (BranchRelaxation)
530 addPass(&BranchRelaxationPassID);
531
532 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
533 TM->getTargetTriple().isOSBinFormatMachO())
534 addPass(createAArch64CollectLOHPass());
535 }
536