1//===-- AMDGPUGIsel.td - AMDGPU GlobalISel Patterns---------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This files contains patterns that should only be used by GlobalISel.  For
10// example patterns for V_* instructions that have S_* equivalents.
11// SelectionDAG does not support selecting V_* instructions.
12//===----------------------------------------------------------------------===//
13
14include "AMDGPU.td"
15
16def sd_vsrc0 : ComplexPattern<i32, 1, "">;
17def gi_vsrc0 :
18    GIComplexOperandMatcher<s32, "selectVSRC0">,
19    GIComplexPatternEquiv<sd_vsrc0>;
20
21def sd_vcsrc : ComplexPattern<i32, 1, "">;
22def gi_vcsrc :
23    GIComplexOperandMatcher<s32, "selectVCSRC">,
24    GIComplexPatternEquiv<sd_vcsrc>;
25
26def gi_vop3mods0 :
27    GIComplexOperandMatcher<s32, "selectVOP3Mods0">,
28    GIComplexPatternEquiv<VOP3Mods0>;
29
30def gi_vop3mods :
31    GIComplexOperandMatcher<s32, "selectVOP3Mods">,
32    GIComplexPatternEquiv<VOP3Mods>;
33
34def gi_vop3omods :
35    GIComplexOperandMatcher<s32, "selectVOP3OMods">,
36    GIComplexPatternEquiv<VOP3OMods>;
37
38class GISelSop2Pat <
39  SDPatternOperator node,
40  Instruction inst,
41  ValueType dst_vt,
42  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
43
44  (dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))),
45  (inst src0_vt:$src0, src1_vt:$src1)
46>;
47
48class GISelVop2Pat <
49  SDPatternOperator node,
50  Instruction inst,
51  ValueType dst_vt,
52  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
53
54  (dst_vt (node (src0_vt (sd_vsrc0 src0_vt:$src0)), (src1_vt VGPR_32:$src1))),
55  (inst src0_vt:$src0, src1_vt:$src1)
56>;
57
58class GISelVop2CommutePat <
59  SDPatternOperator node,
60  Instruction inst,
61  ValueType dst_vt,
62  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
63
64  (dst_vt (node (src1_vt VGPR_32:$src1), (src0_vt (sd_vsrc0 src0_vt:$src0)))),
65  (inst src0_vt:$src0, src1_vt:$src1)
66>;
67
68class GISelVop3Pat2 <
69  SDPatternOperator node,
70  Instruction inst,
71  ValueType dst_vt,
72  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
73
74  (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
75  (inst src0_vt:$src0, src1_vt:$src1)
76>;
77
78class GISelVop3Pat2CommutePat <
79  SDPatternOperator node,
80  Instruction inst,
81  ValueType dst_vt,
82  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
83
84  (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
85  (inst src0_vt:$src1, src1_vt:$src0)
86>;
87
88class GISelVop3Pat2ModsPat <
89  SDPatternOperator node,
90  Instruction inst,
91  ValueType dst_vt,
92  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat <
93
94  (dst_vt (node (src0_vt (VOP3Mods0 src0_vt:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omods)),
95                (src1_vt (VOP3Mods src1_vt:$src1, i32:$src1_modifiers)))),
96  (inst i32:$src0_modifiers, src0_vt:$src0,
97        i32:$src1_modifiers, src1_vt:$src1, $clamp, $omods)
98>;
99
100multiclass GISelVop2IntrPat <
101  SDPatternOperator node, Instruction inst,
102  ValueType dst_vt, ValueType src_vt = dst_vt> {
103
104  def : GISelVop2Pat <node, inst, dst_vt, src_vt>;
105
106  // FIXME: Intrinsics aren't marked as commutable, so we need to add an explcit
107  // pattern to handle commuting.  This is another reason why legalizing to a
108  // generic machine instruction may be better that matching the intrinsic
109  // directly.
110  def : GISelVop2CommutePat <node, inst, dst_vt, src_vt>;
111}
112
113def : GISelSop2Pat <or, S_OR_B32, i32>;
114def : GISelVop2Pat <or, V_OR_B32_e32, i32>;
115
116def : GISelSop2Pat <sra, S_ASHR_I32, i32>;
117let AddedComplexity = 100 in {
118let SubtargetPredicate = isSICI in {
119def : GISelVop2Pat <sra, V_ASHR_I32_e32, i32>;
120}
121def : GISelVop2CommutePat <sra, V_ASHRREV_I32_e32, i32>;
122}
123def : GISelVop3Pat2CommutePat <sra, V_ASHRREV_I32_e64, i32>;
124
125// FIXME: Select directly to _e32 so we don't need to deal with modifiers.
126// FIXME: We can't re-use SelectionDAG patterns here because they match
127// against a custom SDNode and we would need to create a generic machine
128// instruction that is equivalent to the custom SDNode.  This would also require
129// us to custom legalize the intrinsic to the new generic machine instruction,
130// but I can't get custom legalizing of intrinsic to work and I'm not sure if
131// this is even supported yet.
132defm : GISelVop2IntrPat <
133  int_amdgcn_cvt_pkrtz, V_CVT_PKRTZ_F16_F32_e32, v2f16, f32>;
134
135defm : GISelVop2IntrPat <int_maxnum, V_MAX_F32_e32, f32>;
136def : GISelVop3Pat2ModsPat <int_maxnum, V_MAX_F64, f64>;
137defm : GISelVop2IntrPat <int_minnum, V_MIN_F32_e32, f32>;
138def : GISelVop3Pat2ModsPat <int_minnum, V_MIN_F64, f64>;
139