1//===- AMDGPUGenRegisterBankInfo.def -----------------------------*- C++ -*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9/// \file 10/// This file defines all the static objects used by AMDGPURegisterBankInfo. 11/// \todo This should be generated by TableGen. 12//===----------------------------------------------------------------------===// 13 14namespace llvm { 15namespace AMDGPU { 16 17enum PartialMappingIdx { 18 None = - 1, 19 PM_SGPR1 = 0, 20 PM_SGPR16 = 4, 21 PM_SGPR32 = 5, 22 PM_SGPR64 = 6, 23 PM_SGPR128 = 7, 24 PM_SGPR256 = 8, 25 PM_SGPR512 = 9, 26 PM_VGPR1 = 10, 27 PM_VGPR16 = 14, 28 PM_VGPR32 = 15, 29 PM_VGPR64 = 16, 30 PM_VGPR128 = 17, 31 PM_VGPR256 = 18, 32 PM_VGPR512 = 19, 33 PM_SGPR96 = 20, 34 PM_VGPR96 = 21 35}; 36 37const RegisterBankInfo::PartialMapping PartMappings[] { 38 // StartIdx, Length, RegBank 39 {0, 1, SCCRegBank}, 40 {0, 16, SGPRRegBank}, 41 {0, 32, SGPRRegBank}, 42 {0, 64, SGPRRegBank}, 43 {0, 128, SGPRRegBank}, 44 {0, 256, SGPRRegBank}, 45 {0, 512, SGPRRegBank}, 46 {0, 1, SGPRRegBank}, 47 {0, 16, VGPRRegBank}, 48 {0, 32, VGPRRegBank}, 49 {0, 64, VGPRRegBank}, 50 {0, 128, VGPRRegBank}, 51 {0, 256, VGPRRegBank}, 52 {0, 512, VGPRRegBank}, 53 {0, 96, SGPRRegBank}, 54 {0, 96, VGPRRegBank}, 55}; 56 57const RegisterBankInfo::ValueMapping ValMappings[] { 58 {&PartMappings[0], 1}, 59 {nullptr, 0}, 60 {nullptr, 0}, 61 {nullptr, 0}, 62 {&PartMappings[1], 1}, 63 {&PartMappings[2], 1}, 64 {&PartMappings[3], 1}, 65 {&PartMappings[4], 1}, 66 {&PartMappings[5], 1}, 67 {&PartMappings[6], 1}, 68 {&PartMappings[7], 1}, 69 {nullptr, 0}, 70 {nullptr, 0}, 71 {nullptr, 0}, 72 {&PartMappings[8], 1}, 73 {&PartMappings[9], 1}, 74 {&PartMappings[10], 1}, 75 {&PartMappings[11], 1}, 76 {&PartMappings[12], 1}, 77 {&PartMappings[13], 1}, 78 {&PartMappings[14], 1}, 79 {&PartMappings[15], 1} 80}; 81 82enum ValueMappingIdx { 83 SGPRStartIdx = 0, 84 VGPRStartIdx = 10 85}; 86 87const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID, 88 unsigned Size) { 89 unsigned Idx; 90 switch (Size) { 91 case 1: 92 Idx = BankID == AMDGPU::SCCRegBankID ? PM_SGPR1 : PM_VGPR1; 93 break; 94 case 96: 95 Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR96 : PM_VGPR96; 96 break; 97 default: 98 Idx = BankID == AMDGPU::VGPRRegBankID ? VGPRStartIdx : SGPRStartIdx; 99 Idx += Log2_32_Ceil(Size); 100 break; 101 } 102 return &ValMappings[Idx]; 103} 104 105} // End AMDGPU namespace. 106} // End llvm namespace. 107