1//===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// TableGen definitions for instructions which are available on R600 family 11// GPUs. 12// 13//===----------------------------------------------------------------------===// 14 15include "R600InstrFormats.td" 16 17// FIXME: Should not be arbitrarily split from other R600 inst classes. 18class R600WrapperInst <dag outs, dag ins, string asm = "", list<dag> pattern = []> : 19 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl { 20 let SubtargetPredicate = isR600toCayman; 21 let Namespace = "R600"; 22} 23 24 25class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern = []> : 26 InstR600 <outs, ins, asm, pattern, NullALU> { 27 28} 29 30def MEMxi : Operand<iPTR> { 31 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index); 32 let PrintMethod = "printMemOperand"; 33} 34 35def MEMrr : Operand<iPTR> { 36 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index); 37} 38 39// Operands for non-registers 40 41class InstFlag<string PM = "printOperand", int Default = 0> 42 : OperandWithDefaultOps <i32, (ops (i32 Default))> { 43 let PrintMethod = PM; 44} 45 46// src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers 47def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))>; 48def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> { 49 let PrintMethod = "printBankSwizzle"; 50} 51 52def LITERAL : InstFlag<"printLiteral">; 53 54def WRITE : InstFlag <"printWrite", 1>; 55def OMOD : InstFlag <"printOMOD">; 56def REL : InstFlag <"printRel">; 57def CLAMP : InstFlag <"printClamp">; 58def NEG : InstFlag <"printNeg">; 59def ABS : InstFlag <"printAbs">; 60def UEM : InstFlag <"printUpdateExecMask">; 61def UP : InstFlag <"printUpdatePred">; 62 63// XXX: The r600g finalizer in Mesa expects last to be one in most cases. 64// Once we start using the packetizer in this backend we should have this 65// default to 0. 66def LAST : InstFlag<"printLast", 1>; 67def RSel : Operand<i32> { 68 let PrintMethod = "printRSel"; 69} 70def CT: Operand<i32> { 71 let PrintMethod = "printCT"; 72} 73 74def FRAMEri : Operand<iPTR> { 75 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index); 76} 77 78def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>; 79def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>; 80def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>; 81def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>; 82def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>; 83def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>; 84 85 86def R600_Pred : PredicateOperand<i32, (ops R600_Predicate), 87 (ops PRED_SEL_OFF)>; 88 89let isTerminator = 1, isReturn = 1, hasCtrlDep = 1, 90 usesCustomInserter = 1, Namespace = "R600" in { 91 def RETURN : ILFormat<(outs), (ins variable_ops), 92 "RETURN", [(AMDGPUendpgm)] 93 >; 94} 95 96let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { 97 98// Class for instructions with only one source register. 99// If you add new ins to this instruction, make sure they are listed before 100// $literal, because the backend currently assumes that the last operand is 101// a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in 102// R600Defines.h, R600InstrInfo::buildDefaultInstruction(), 103// and R600InstrInfo::getOperandIdx(). 104class R600_1OP <bits<11> inst, string opName, list<dag> pattern, 105 InstrItinClass itin = AnyALU> : 106 InstR600 <(outs R600_Reg32:$dst), 107 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp, 108 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel, 109 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 110 BANK_SWIZZLE:$bank_swizzle), 111 !strconcat(" ", opName, 112 "$clamp $last $dst$write$dst_rel$omod, " 113 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, " 114 "$pred_sel $bank_swizzle"), 115 pattern, 116 itin>, 117 R600ALU_Word0, 118 R600ALU_Word1_OP2 <inst> { 119 120 let src1 = 0; 121 let src1_rel = 0; 122 let src1_neg = 0; 123 let src1_abs = 0; 124 let update_exec_mask = 0; 125 let update_pred = 0; 126 let HasNativeOperands = 1; 127 let Op1 = 1; 128 let ALUInst = 1; 129 let DisableEncoding = "$literal"; 130 let UseNamedOperandTable = 1; 131 132 let Inst{31-0} = Word0; 133 let Inst{63-32} = Word1; 134} 135 136class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node, 137 InstrItinClass itin = AnyALU> : 138 R600_1OP <inst, opName, 139 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))], itin 140>; 141 142// If you add or change the operands for R600_2OP instructions, you must 143// also update the R600Op2OperandIndex::ROI enum in R600Defines.h, 144// R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx(). 145class R600_2OP <bits<11> inst, string opName, list<dag> pattern, 146 InstrItinClass itin = AnyALU> : 147 InstR600 <(outs R600_Reg32:$dst), 148 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write, 149 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp, 150 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel, 151 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel, 152 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 153 BANK_SWIZZLE:$bank_swizzle), 154 !strconcat(" ", opName, 155 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, " 156 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, " 157 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, " 158 "$pred_sel $bank_swizzle"), 159 pattern, 160 itin>, 161 R600ALU_Word0, 162 R600ALU_Word1_OP2 <inst> { 163 164 let HasNativeOperands = 1; 165 let Op2 = 1; 166 let ALUInst = 1; 167 let DisableEncoding = "$literal"; 168 let UseNamedOperandTable = 1; 169 170 let Inst{31-0} = Word0; 171 let Inst{63-32} = Word1; 172} 173 174class R600_2OP_Helper <bits<11> inst, string opName, 175 SDPatternOperator node = null_frag, 176 InstrItinClass itin = AnyALU> : 177 R600_2OP <inst, opName, 178 [(set R600_Reg32:$dst, (node R600_Reg32:$src0, 179 R600_Reg32:$src1))], itin 180>; 181 182// If you add our change the operands for R600_3OP instructions, you must 183// also update the R600Op3OperandIndex::ROI enum in R600Defines.h, 184// R600InstrInfo::buildDefaultInstruction(), and 185// R600InstrInfo::getOperandIdx(). 186class R600_3OP <bits<5> inst, string opName, list<dag> pattern, 187 InstrItinClass itin = AnyALU> : 188 InstR600 <(outs R600_Reg32:$dst), 189 (ins REL:$dst_rel, CLAMP:$clamp, 190 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel, 191 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel, 192 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel, 193 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 194 BANK_SWIZZLE:$bank_swizzle), 195 !strconcat(" ", opName, "$clamp $last $dst$dst_rel, " 196 "$src0_neg$src0$src0_rel, " 197 "$src1_neg$src1$src1_rel, " 198 "$src2_neg$src2$src2_rel, " 199 "$pred_sel" 200 "$bank_swizzle"), 201 pattern, 202 itin>, 203 R600ALU_Word0, 204 R600ALU_Word1_OP3<inst>{ 205 206 let HasNativeOperands = 1; 207 let DisableEncoding = "$literal"; 208 let Op3 = 1; 209 let UseNamedOperandTable = 1; 210 let ALUInst = 1; 211 212 let Inst{31-0} = Word0; 213 let Inst{63-32} = Word1; 214} 215 216class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern, 217 InstrItinClass itin = VecALU> : 218 InstR600 <(outs R600_Reg32:$dst), 219 ins, 220 asm, 221 pattern, 222 itin>; 223 224 225 226} // End mayLoad = 1, mayStore = 0, hasSideEffects = 0 227 228class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> ratid, bits<4> mask, 229 dag outs, dag ins, string asm, list<dag> pattern> : 230 InstR600ISA <outs, ins, asm, pattern>, 231 CF_ALLOC_EXPORT_WORD0_RAT, CF_ALLOC_EXPORT_WORD1_BUF { 232 233 let rat_id = ratid; 234 let rat_inst = ratinst; 235 let rim = 0; 236 // XXX: Have a separate instruction for non-indexed writes. 237 let type = 1; 238 let rw_rel = 0; 239 let elem_size = 0; 240 241 let array_size = 0; 242 let comp_mask = mask; 243 let burst_count = 0; 244 let vpm = 0; 245 let cf_inst = cfinst; 246 let mark = 0; 247 let barrier = 1; 248 249 let Inst{31-0} = Word0; 250 let Inst{63-32} = Word1; 251 let IsExport = 1; 252 253} 254 255class VTX_READ <string name, dag outs, list<dag> pattern> 256 : InstR600ISA <outs, (ins MEMxi:$src_gpr, i8imm:$buffer_id), !strconcat(" ", name, ", #$buffer_id"), pattern>, 257 VTX_WORD1_GPR { 258 259 // Static fields 260 let DST_REL = 0; 261 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL, 262 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored, 263 // however, based on my testing if USE_CONST_FIELDS is set, then all 264 // these fields need to be set to 0. 265 let USE_CONST_FIELDS = 0; 266 let NUM_FORMAT_ALL = 1; 267 let FORMAT_COMP_ALL = 0; 268 let SRF_MODE_ALL = 0; 269 270 let Inst{63-32} = Word1; 271 // LLVM can only encode 64-bit instructions, so these fields are manually 272 // encoded in R600CodeEmitter 273 // 274 // bits<16> OFFSET; 275 // bits<2> ENDIAN_SWAP = 0; 276 // bits<1> CONST_BUF_NO_STRIDE = 0; 277 // bits<1> MEGA_FETCH = 0; 278 // bits<1> ALT_CONST = 0; 279 // bits<2> BUFFER_INDEX_MODE = 0; 280 281 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 282 // is done in R600CodeEmitter 283 // 284 // Inst{79-64} = OFFSET; 285 // Inst{81-80} = ENDIAN_SWAP; 286 // Inst{82} = CONST_BUF_NO_STRIDE; 287 // Inst{83} = MEGA_FETCH; 288 // Inst{84} = ALT_CONST; 289 // Inst{86-85} = BUFFER_INDEX_MODE; 290 // Inst{95-86} = 0; Reserved 291 292 // VTX_WORD3 (Padding) 293 // 294 // Inst{127-96} = 0; 295 296 let VTXInst = 1; 297} 298 299class LoadParamFrag <PatFrag load_type> : PatFrag < 300 (ops node:$ptr), (load_type node:$ptr), 301 [{ return isConstantLoad(cast<LoadSDNode>(N), 0) || 302 (cast<LoadSDNode>(N)->getAddressSpace() == AMDGPUASI.PARAM_I_ADDRESS); }] 303>; 304 305def vtx_id3_az_extloadi8 : LoadParamFrag<az_extloadi8>; 306def vtx_id3_az_extloadi16 : LoadParamFrag<az_extloadi16>; 307def vtx_id3_load : LoadParamFrag<load>; 308 309class LoadVtxId1 <PatFrag load> : PatFrag < 310 (ops node:$ptr), (load node:$ptr), [{ 311 const MemSDNode *LD = cast<MemSDNode>(N); 312 return LD->getAddressSpace() == AMDGPUASI.GLOBAL_ADDRESS || 313 (LD->getAddressSpace() == AMDGPUASI.CONSTANT_ADDRESS && 314 !isa<GlobalValue>(GetUnderlyingObject( 315 LD->getMemOperand()->getValue(), CurDAG->getDataLayout()))); 316}]>; 317 318def vtx_id1_az_extloadi8 : LoadVtxId1 <az_extloadi8>; 319def vtx_id1_az_extloadi16 : LoadVtxId1 <az_extloadi16>; 320def vtx_id1_load : LoadVtxId1 <load>; 321 322class LoadVtxId2 <PatFrag load> : PatFrag < 323 (ops node:$ptr), (load node:$ptr), [{ 324 const MemSDNode *LD = cast<MemSDNode>(N); 325 return LD->getAddressSpace() == AMDGPUASI.CONSTANT_ADDRESS && 326 isa<GlobalValue>(GetUnderlyingObject( 327 LD->getMemOperand()->getValue(), CurDAG->getDataLayout())); 328}]>; 329 330def vtx_id2_az_extloadi8 : LoadVtxId2 <az_extloadi8>; 331def vtx_id2_az_extloadi16 : LoadVtxId2 <az_extloadi16>; 332def vtx_id2_load : LoadVtxId2 <load>; 333 334//===----------------------------------------------------------------------===// 335// R600 SDNodes 336//===----------------------------------------------------------------------===// 337 338let Namespace = "R600" in { 339 340def INTERP_PAIR_XY : AMDGPUShaderInst < 341 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1), 342 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2), 343 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1", 344 []>; 345 346def INTERP_PAIR_ZW : AMDGPUShaderInst < 347 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1), 348 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2), 349 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1", 350 []>; 351 352} 353 354def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS", 355 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>, 356 [SDNPVariadic] 357>; 358 359def DOT4 : SDNode<"AMDGPUISD::DOT4", 360 SDTypeProfile<1, 8, [SDTCisFP<0>, SDTCisVT<1, f32>, SDTCisVT<2, f32>, 361 SDTCisVT<3, f32>, SDTCisVT<4, f32>, SDTCisVT<5, f32>, 362 SDTCisVT<6, f32>, SDTCisVT<7, f32>, SDTCisVT<8, f32>]>, 363 [] 364>; 365 366def COS_HW : SDNode<"AMDGPUISD::COS_HW", 367 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]> 368>; 369 370def SIN_HW : SDNode<"AMDGPUISD::SIN_HW", 371 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]> 372>; 373 374def TEXTURE_FETCH_Type : SDTypeProfile<1, 19, [SDTCisFP<0>]>; 375 376def TEXTURE_FETCH: SDNode<"AMDGPUISD::TEXTURE_FETCH", TEXTURE_FETCH_Type, []>; 377 378multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> { 379def : R600Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR, 380 (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw), 381 (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz), 382 (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z), 383 (i32 imm:$DST_SEL_W), 384 (i32 imm:$RESOURCE_ID), (i32 imm:$SAMPLER_ID), 385 (i32 imm:$COORD_TYPE_X), (i32 imm:$COORD_TYPE_Y), (i32 imm:$COORD_TYPE_Z), 386 (i32 imm:$COORD_TYPE_W)), 387 (inst R600_Reg128:$SRC_GPR, 388 imm:$srcx, imm:$srcy, imm:$srcz, imm:$srcw, 389 imm:$offsetx, imm:$offsety, imm:$offsetz, 390 imm:$DST_SEL_X, imm:$DST_SEL_Y, imm:$DST_SEL_Z, 391 imm:$DST_SEL_W, 392 imm:$RESOURCE_ID, imm:$SAMPLER_ID, 393 imm:$COORD_TYPE_X, imm:$COORD_TYPE_Y, imm:$COORD_TYPE_Z, 394 imm:$COORD_TYPE_W)>; 395} 396 397//===----------------------------------------------------------------------===// 398// Interpolation Instructions 399//===----------------------------------------------------------------------===// 400 401let Namespace = "R600" in { 402 403def INTERP_VEC_LOAD : AMDGPUShaderInst < 404 (outs R600_Reg128:$dst), 405 (ins i32imm:$src0), 406 "INTERP_LOAD $src0 : $dst">; 407 408} 409 410def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> { 411 let bank_swizzle = 5; 412} 413 414def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> { 415 let bank_swizzle = 5; 416} 417 418def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>; 419 420//===----------------------------------------------------------------------===// 421// Export Instructions 422//===----------------------------------------------------------------------===// 423 424class ExportWord0 { 425 field bits<32> Word0; 426 427 bits<13> arraybase; 428 bits<2> type; 429 bits<7> gpr; 430 bits<2> elem_size; 431 432 let Word0{12-0} = arraybase; 433 let Word0{14-13} = type; 434 let Word0{21-15} = gpr; 435 let Word0{22} = 0; // RW_REL 436 let Word0{29-23} = 0; // INDEX_GPR 437 let Word0{31-30} = elem_size; 438} 439 440class ExportSwzWord1 { 441 field bits<32> Word1; 442 443 bits<3> sw_x; 444 bits<3> sw_y; 445 bits<3> sw_z; 446 bits<3> sw_w; 447 bits<1> eop; 448 bits<8> inst; 449 450 let Word1{2-0} = sw_x; 451 let Word1{5-3} = sw_y; 452 let Word1{8-6} = sw_z; 453 let Word1{11-9} = sw_w; 454} 455 456class ExportBufWord1 { 457 field bits<32> Word1; 458 459 bits<12> arraySize; 460 bits<4> compMask; 461 bits<1> eop; 462 bits<8> inst; 463 464 let Word1{11-0} = arraySize; 465 let Word1{15-12} = compMask; 466} 467 468multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> { 469 def : R600Pat<(R600_EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type), 470 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)), 471 (ExportInst R600_Reg128:$src, imm:$type, imm:$base, 472 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0) 473 >; 474 475} 476 477multiclass SteamOutputExportPattern<Instruction ExportInst, 478 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> { 479// Stream0 480 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src), 481 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)), 482 (ExportInst R600_Reg128:$src, 0, imm:$arraybase, 483 4095, imm:$mask, buf0inst, 0)>; 484// Stream1 485 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src), 486 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)), 487 (ExportInst $src, 0, imm:$arraybase, 488 4095, imm:$mask, buf1inst, 0)>; 489// Stream2 490 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src), 491 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)), 492 (ExportInst $src, 0, imm:$arraybase, 493 4095, imm:$mask, buf2inst, 0)>; 494// Stream3 495 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src), 496 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)), 497 (ExportInst $src, 0, imm:$arraybase, 498 4095, imm:$mask, buf3inst, 0)>; 499} 500 501// Export Instructions should not be duplicated by TailDuplication pass 502// (which assumes that duplicable instruction are affected by exec mask) 503let usesCustomInserter = 1, isNotDuplicable = 1 in { 504 505class ExportSwzInst : InstR600ISA<( 506 outs), 507 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase, 508 RSel:$sw_x, RSel:$sw_y, RSel:$sw_z, RSel:$sw_w, i32imm:$inst, 509 i32imm:$eop), 510 !strconcat("EXPORT", " $gpr.$sw_x$sw_y$sw_z$sw_w"), 511 []>, ExportWord0, ExportSwzWord1 { 512 let elem_size = 3; 513 let Inst{31-0} = Word0; 514 let Inst{63-32} = Word1; 515 let IsExport = 1; 516} 517 518} // End usesCustomInserter = 1 519 520class ExportBufInst : InstR600ISA<( 521 outs), 522 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase, 523 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop), 524 !strconcat("EXPORT", " $gpr"), 525 []>, ExportWord0, ExportBufWord1 { 526 let elem_size = 0; 527 let Inst{31-0} = Word0; 528 let Inst{63-32} = Word1; 529 let IsExport = 1; 530} 531 532//===----------------------------------------------------------------------===// 533// Control Flow Instructions 534//===----------------------------------------------------------------------===// 535 536 537def KCACHE : InstFlag<"printKCache">; 538 539class ALU_CLAUSE<bits<4> inst, string OpName> : R600WrapperInst <(outs), 540(ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1, 541KCACHE:$KCACHE_MODE0, KCACHE:$KCACHE_MODE1, 542i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1, 543i32imm:$COUNT, i32imm:$Enabled), 544!strconcat(OpName, " $COUNT, @$ADDR, " 545"KC0[$KCACHE_MODE0], KC1[$KCACHE_MODE1]"), 546[] >, CF_ALU_WORD0, CF_ALU_WORD1 { 547 field bits<64> Inst; 548 549 let CF_INST = inst; 550 let ALT_CONST = 0; 551 let WHOLE_QUAD_MODE = 0; 552 let BARRIER = 1; 553 let isCodeGenOnly = 1; 554 let UseNamedOperandTable = 1; 555 556 let Inst{31-0} = Word0; 557 let Inst{63-32} = Word1; 558} 559 560class CF_WORD0_R600 { 561 field bits<32> Word0; 562 563 bits<32> ADDR; 564 565 let Word0 = ADDR; 566} 567 568class CF_CLAUSE_R600 <bits<7> inst, dag ins, string AsmPrint> : R600WrapperInst <(outs), 569ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 { 570 field bits<64> Inst; 571 bits<4> CNT; 572 573 let CF_INST = inst; 574 let BARRIER = 1; 575 let CF_CONST = 0; 576 let VALID_PIXEL_MODE = 0; 577 let COND = 0; 578 let COUNT = CNT{2-0}; 579 let CALL_COUNT = 0; 580 let COUNT_3 = CNT{3}; 581 let END_OF_PROGRAM = 0; 582 let WHOLE_QUAD_MODE = 0; 583 584 let Inst{31-0} = Word0; 585 let Inst{63-32} = Word1; 586} 587 588class CF_CLAUSE_EG <bits<8> inst, dag ins, string AsmPrint> : R600WrapperInst <(outs), 589ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG { 590 field bits<64> Inst; 591 592 let CF_INST = inst; 593 let BARRIER = 1; 594 let JUMPTABLE_SEL = 0; 595 let CF_CONST = 0; 596 let VALID_PIXEL_MODE = 0; 597 let COND = 0; 598 let END_OF_PROGRAM = 0; 599 600 let Inst{31-0} = Word0; 601 let Inst{63-32} = Word1; 602} 603 604def CF_ALU : ALU_CLAUSE<8, "ALU">; 605def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">; 606def CF_ALU_POP_AFTER : ALU_CLAUSE<10, "ALU_POP_AFTER">; 607def CF_ALU_CONTINUE : ALU_CLAUSE<13, "ALU_CONTINUE">; 608def CF_ALU_BREAK : ALU_CLAUSE<14, "ALU_BREAK">; 609def CF_ALU_ELSE_AFTER : ALU_CLAUSE<15, "ALU_ELSE_AFTER">; 610 611def FETCH_CLAUSE : R600WrapperInst <(outs), 612(ins i32imm:$addr), "Fetch clause starting at $addr:", [] > { 613 field bits<8> Inst; 614 bits<8> num; 615 let Inst = num; 616 let isCodeGenOnly = 1; 617} 618 619def ALU_CLAUSE : R600WrapperInst <(outs), 620(ins i32imm:$addr), "ALU clause starting at $addr:", [] > { 621 field bits<8> Inst; 622 bits<8> num; 623 let Inst = num; 624 let isCodeGenOnly = 1; 625} 626 627def LITERALS : R600WrapperInst <(outs), 628(ins LITERAL:$literal1, LITERAL:$literal2), "$literal1, $literal2", [] > { 629 let isCodeGenOnly = 1; 630 631 field bits<64> Inst; 632 bits<32> literal1; 633 bits<32> literal2; 634 635 let Inst{31-0} = literal1; 636 let Inst{63-32} = literal2; 637} 638 639def PAD : R600WrapperInst <(outs), (ins), "PAD", [] > { 640 field bits<64> Inst; 641} 642 643//===----------------------------------------------------------------------===// 644// Common Instructions R600, R700, Evergreen, Cayman 645//===----------------------------------------------------------------------===// 646 647let isCodeGenOnly = 1, isPseudo = 1 in { 648 649let Namespace = "R600", usesCustomInserter = 1 in { 650 651class FABS <RegisterClass rc> : AMDGPUShaderInst < 652 (outs rc:$dst), 653 (ins rc:$src0), 654 "FABS $dst, $src0", 655 [(set f32:$dst, (fabs f32:$src0))] 656>; 657 658class FNEG <RegisterClass rc> : AMDGPUShaderInst < 659 (outs rc:$dst), 660 (ins rc:$src0), 661 "FNEG $dst, $src0", 662 [(set f32:$dst, (fneg f32:$src0))] 663>; 664 665} // usesCustomInserter = 1 666 667multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass, 668 ComplexPattern addrPat> { 669let UseNamedOperandTable = 1 in { 670 671 def RegisterLoad : AMDGPUShaderInst < 672 (outs dstClass:$dst), 673 (ins addrClass:$addr, i32imm:$chan), 674 "RegisterLoad $dst, $addr", 675 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))] 676 > { 677 let isRegisterLoad = 1; 678 } 679 680 def RegisterStore : AMDGPUShaderInst < 681 (outs), 682 (ins dstClass:$val, addrClass:$addr, i32imm:$chan), 683 "RegisterStore $val, $addr", 684 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))] 685 > { 686 let isRegisterStore = 1; 687 } 688} 689} 690 691} // End isCodeGenOnly = 1, isPseudo = 1 692 693 694def ADD : R600_2OP_Helper <0x0, "ADD", fadd>; 695// Non-IEEE MUL: 0 * anything = 0 696def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE">; 697def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>; 698// TODO: Do these actually match the regular fmin/fmax behavior? 699def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax_legacy>; 700def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin_legacy>; 701// According to https://msdn.microsoft.com/en-us/library/windows/desktop/cc308050%28v=vs.85%29.aspx 702// DX10 min/max returns the other operand if one is NaN, 703// this matches http://llvm.org/docs/LangRef.html#llvm-minnum-intrinsic 704def MAX_DX10 : R600_2OP_Helper <0x5, "MAX_DX10", fmaxnum>; 705def MIN_DX10 : R600_2OP_Helper <0x6, "MIN_DX10", fminnum>; 706 707// For the SET* instructions there is a naming conflict in TargetSelectionDAG.td, 708// so some of the instruction names don't match the asm string. 709// XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics. 710def SETE : R600_2OP < 711 0x08, "SETE", 712 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OEQ))] 713>; 714 715def SGT : R600_2OP < 716 0x09, "SETGT", 717 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGT))] 718>; 719 720def SGE : R600_2OP < 721 0xA, "SETGE", 722 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGE))] 723>; 724 725def SNE : R600_2OP < 726 0xB, "SETNE", 727 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_UNE_NE))] 728>; 729 730def SETE_DX10 : R600_2OP < 731 0xC, "SETE_DX10", 732 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OEQ))] 733>; 734 735def SETGT_DX10 : R600_2OP < 736 0xD, "SETGT_DX10", 737 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGT))] 738>; 739 740def SETGE_DX10 : R600_2OP < 741 0xE, "SETGE_DX10", 742 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGE))] 743>; 744 745// FIXME: This should probably be COND_ONE 746def SETNE_DX10 : R600_2OP < 747 0xF, "SETNE_DX10", 748 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_UNE_NE))] 749>; 750 751// FIXME: Need combine for AMDGPUfract 752def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>; 753def TRUNC : R600_1OP_Helper <0x11, "TRUNC", ftrunc>; 754def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>; 755def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>; 756def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>; 757 758def MOV : R600_1OP <0x19, "MOV", []>; 759 760 761// This is a hack to get rid of DUMMY_CHAIN nodes. 762// Most DUMMY_CHAINs should be eliminated during legalization, but undef 763// values can sneak in some to selection. 764let isPseudo = 1, isCodeGenOnly = 1 in { 765def DUMMY_CHAIN : R600WrapperInst < 766 (outs), 767 (ins), 768 "DUMMY_CHAIN", 769 [(R600dummy_chain)] 770>; 771} // end let isPseudo = 1, isCodeGenOnly = 1 772 773 774let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in { 775 776class MOV_IMM <ValueType vt, Operand immType> : R600WrapperInst < 777 (outs R600_Reg32:$dst), 778 (ins immType:$imm), 779 "", 780 [] 781> { 782 let Namespace = "R600"; 783} 784 785} // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 786 787def MOV_IMM_I32 : MOV_IMM<i32, i32imm>; 788def : R600Pat < 789 (imm:$val), 790 (MOV_IMM_I32 imm:$val) 791>; 792 793def MOV_IMM_GLOBAL_ADDR : MOV_IMM<iPTR, i32imm>; 794def : R600Pat < 795 (AMDGPUconstdata_ptr tglobaladdr:$addr), 796 (MOV_IMM_GLOBAL_ADDR tglobaladdr:$addr) 797>; 798 799 800def MOV_IMM_F32 : MOV_IMM<f32, f32imm>; 801def : R600Pat < 802 (fpimm:$val), 803 (MOV_IMM_F32 fpimm:$val) 804>; 805 806def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>; 807def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>; 808def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>; 809def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>; 810 811let hasSideEffects = 1 in { 812 813def KILLGT : R600_2OP <0x2D, "KILLGT", []>; 814 815} // end hasSideEffects 816 817def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>; 818def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>; 819def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>; 820def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>; 821def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>; 822def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>; 823def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", smax>; 824def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", smin>; 825def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", umax>; 826def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", umin>; 827 828def SETE_INT : R600_2OP < 829 0x3A, "SETE_INT", 830 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETEQ))] 831>; 832 833def SETGT_INT : R600_2OP < 834 0x3B, "SETGT_INT", 835 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))] 836>; 837 838def SETGE_INT : R600_2OP < 839 0x3C, "SETGE_INT", 840 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))] 841>; 842 843def SETNE_INT : R600_2OP < 844 0x3D, "SETNE_INT", 845 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETNE))] 846>; 847 848def SETGT_UINT : R600_2OP < 849 0x3E, "SETGT_UINT", 850 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGT))] 851>; 852 853def SETGE_UINT : R600_2OP < 854 0x3F, "SETGE_UINT", 855 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGE))] 856>; 857 858def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>; 859def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>; 860def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>; 861def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>; 862 863def CNDE_INT : R600_3OP < 864 0x1C, "CNDE_INT", 865 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_EQ))] 866>; 867 868def CNDGE_INT : R600_3OP < 869 0x1E, "CNDGE_INT", 870 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGE))] 871>; 872 873def CNDGT_INT : R600_3OP < 874 0x1D, "CNDGT_INT", 875 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGT))] 876>; 877 878//===----------------------------------------------------------------------===// 879// Texture instructions 880//===----------------------------------------------------------------------===// 881 882let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { 883 884class R600_TEX <bits<11> inst, string opName> : 885 InstR600 <(outs R600_Reg128:$DST_GPR), 886 (ins R600_Reg128:$SRC_GPR, 887 RSel:$srcx, RSel:$srcy, RSel:$srcz, RSel:$srcw, 888 i32imm:$offsetx, i32imm:$offsety, i32imm:$offsetz, 889 RSel:$DST_SEL_X, RSel:$DST_SEL_Y, RSel:$DST_SEL_Z, RSel:$DST_SEL_W, 890 i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID, 891 CT:$COORD_TYPE_X, CT:$COORD_TYPE_Y, CT:$COORD_TYPE_Z, 892 CT:$COORD_TYPE_W), 893 !strconcat(" ", opName, 894 " $DST_GPR.$DST_SEL_X$DST_SEL_Y$DST_SEL_Z$DST_SEL_W, " 895 "$SRC_GPR.$srcx$srcy$srcz$srcw " 896 "RID:$RESOURCE_ID SID:$SAMPLER_ID " 897 "CT:$COORD_TYPE_X$COORD_TYPE_Y$COORD_TYPE_Z$COORD_TYPE_W"), 898 [], 899 NullALU>, TEX_WORD0, TEX_WORD1, TEX_WORD2 { 900 let Inst{31-0} = Word0; 901 let Inst{63-32} = Word1; 902 903 let TEX_INST = inst{4-0}; 904 let SRC_REL = 0; 905 let DST_REL = 0; 906 let LOD_BIAS = 0; 907 908 let INST_MOD = 0; 909 let FETCH_WHOLE_QUAD = 0; 910 let ALT_CONST = 0; 911 let SAMPLER_INDEX_MODE = 0; 912 let RESOURCE_INDEX_MODE = 0; 913 914 let TEXInst = 1; 915} 916 917} // End mayLoad = 0, mayStore = 0, hasSideEffects = 0 918 919 920 921def TEX_SAMPLE : R600_TEX <0x10, "TEX_SAMPLE">; 922def TEX_SAMPLE_C : R600_TEX <0x18, "TEX_SAMPLE_C">; 923def TEX_SAMPLE_L : R600_TEX <0x11, "TEX_SAMPLE_L">; 924def TEX_SAMPLE_C_L : R600_TEX <0x19, "TEX_SAMPLE_C_L">; 925def TEX_SAMPLE_LB : R600_TEX <0x12, "TEX_SAMPLE_LB">; 926def TEX_SAMPLE_C_LB : R600_TEX <0x1A, "TEX_SAMPLE_C_LB">; 927def TEX_LD : R600_TEX <0x03, "TEX_LD">; 928def TEX_LDPTR : R600_TEX <0x03, "TEX_LDPTR"> { 929 let INST_MOD = 1; 930} 931def TEX_GET_TEXTURE_RESINFO : R600_TEX <0x04, "TEX_GET_TEXTURE_RESINFO">; 932def TEX_GET_GRADIENTS_H : R600_TEX <0x07, "TEX_GET_GRADIENTS_H">; 933def TEX_GET_GRADIENTS_V : R600_TEX <0x08, "TEX_GET_GRADIENTS_V">; 934def TEX_SET_GRADIENTS_H : R600_TEX <0x0B, "TEX_SET_GRADIENTS_H">; 935def TEX_SET_GRADIENTS_V : R600_TEX <0x0C, "TEX_SET_GRADIENTS_V">; 936def TEX_SAMPLE_G : R600_TEX <0x14, "TEX_SAMPLE_G">; 937def TEX_SAMPLE_C_G : R600_TEX <0x1C, "TEX_SAMPLE_C_G">; 938 939defm : TexPattern<0, TEX_SAMPLE>; 940defm : TexPattern<1, TEX_SAMPLE_C>; 941defm : TexPattern<2, TEX_SAMPLE_L>; 942defm : TexPattern<3, TEX_SAMPLE_C_L>; 943defm : TexPattern<4, TEX_SAMPLE_LB>; 944defm : TexPattern<5, TEX_SAMPLE_C_LB>; 945defm : TexPattern<6, TEX_LD, v4i32>; 946defm : TexPattern<7, TEX_GET_TEXTURE_RESINFO, v4i32>; 947defm : TexPattern<8, TEX_GET_GRADIENTS_H>; 948defm : TexPattern<9, TEX_GET_GRADIENTS_V>; 949defm : TexPattern<10, TEX_LDPTR, v4i32>; 950 951//===----------------------------------------------------------------------===// 952// Helper classes for common instructions 953//===----------------------------------------------------------------------===// 954 955class MUL_LIT_Common <bits<5> inst> : R600_3OP < 956 inst, "MUL_LIT", 957 [] 958>; 959 960class MULADD_Common <bits<5> inst> : R600_3OP < 961 inst, "MULADD", 962 [] 963>; 964 965class MULADD_IEEE_Common <bits<5> inst> : R600_3OP < 966 inst, "MULADD_IEEE", 967 [(set f32:$dst, (fmad f32:$src0, f32:$src1, f32:$src2))] 968>; 969 970class FMA_Common <bits<5> inst> : R600_3OP < 971 inst, "FMA", 972 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))], VecALU 973> 974{ 975 let OtherPredicates = [FMA]; 976} 977 978class CNDE_Common <bits<5> inst> : R600_3OP < 979 inst, "CNDE", 980 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OEQ))] 981>; 982 983class CNDGT_Common <bits<5> inst> : R600_3OP < 984 inst, "CNDGT", 985 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGT))] 986> { 987 let Itinerary = VecALU; 988} 989 990class CNDGE_Common <bits<5> inst> : R600_3OP < 991 inst, "CNDGE", 992 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGE))] 993> { 994 let Itinerary = VecALU; 995} 996 997 998let isCodeGenOnly = 1, isPseudo = 1, Namespace = "R600" in { 999class R600_VEC2OP<list<dag> pattern> : InstR600 <(outs R600_Reg32:$dst), (ins 1000// Slot X 1001 UEM:$update_exec_mask_X, UP:$update_pred_X, WRITE:$write_X, 1002 OMOD:$omod_X, REL:$dst_rel_X, CLAMP:$clamp_X, 1003 R600_TReg32_X:$src0_X, NEG:$src0_neg_X, REL:$src0_rel_X, ABS:$src0_abs_X, SEL:$src0_sel_X, 1004 R600_TReg32_X:$src1_X, NEG:$src1_neg_X, REL:$src1_rel_X, ABS:$src1_abs_X, SEL:$src1_sel_X, 1005 R600_Pred:$pred_sel_X, 1006// Slot Y 1007 UEM:$update_exec_mask_Y, UP:$update_pred_Y, WRITE:$write_Y, 1008 OMOD:$omod_Y, REL:$dst_rel_Y, CLAMP:$clamp_Y, 1009 R600_TReg32_Y:$src0_Y, NEG:$src0_neg_Y, REL:$src0_rel_Y, ABS:$src0_abs_Y, SEL:$src0_sel_Y, 1010 R600_TReg32_Y:$src1_Y, NEG:$src1_neg_Y, REL:$src1_rel_Y, ABS:$src1_abs_Y, SEL:$src1_sel_Y, 1011 R600_Pred:$pred_sel_Y, 1012// Slot Z 1013 UEM:$update_exec_mask_Z, UP:$update_pred_Z, WRITE:$write_Z, 1014 OMOD:$omod_Z, REL:$dst_rel_Z, CLAMP:$clamp_Z, 1015 R600_TReg32_Z:$src0_Z, NEG:$src0_neg_Z, REL:$src0_rel_Z, ABS:$src0_abs_Z, SEL:$src0_sel_Z, 1016 R600_TReg32_Z:$src1_Z, NEG:$src1_neg_Z, REL:$src1_rel_Z, ABS:$src1_abs_Z, SEL:$src1_sel_Z, 1017 R600_Pred:$pred_sel_Z, 1018// Slot W 1019 UEM:$update_exec_mask_W, UP:$update_pred_W, WRITE:$write_W, 1020 OMOD:$omod_W, REL:$dst_rel_W, CLAMP:$clamp_W, 1021 R600_TReg32_W:$src0_W, NEG:$src0_neg_W, REL:$src0_rel_W, ABS:$src0_abs_W, SEL:$src0_sel_W, 1022 R600_TReg32_W:$src1_W, NEG:$src1_neg_W, REL:$src1_rel_W, ABS:$src1_abs_W, SEL:$src1_sel_W, 1023 R600_Pred:$pred_sel_W, 1024 LITERAL:$literal0, LITERAL:$literal1), 1025 "", 1026 pattern, 1027 AnyALU> { 1028 1029 let UseNamedOperandTable = 1; 1030 1031} 1032} 1033 1034def DOT_4 : R600_VEC2OP<[(set R600_Reg32:$dst, (DOT4 1035 R600_TReg32_X:$src0_X, R600_TReg32_X:$src1_X, 1036 R600_TReg32_Y:$src0_Y, R600_TReg32_Y:$src1_Y, 1037 R600_TReg32_Z:$src0_Z, R600_TReg32_Z:$src1_Z, 1038 R600_TReg32_W:$src0_W, R600_TReg32_W:$src1_W))]>; 1039 1040 1041class DOT4_Common <bits<11> inst> : R600_2OP <inst, "DOT4", []>; 1042 1043 1044let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { 1045multiclass CUBE_Common <bits<11> inst> { 1046 1047 def _pseudo : InstR600 < 1048 (outs R600_Reg128:$dst), 1049 (ins R600_Reg128:$src0), 1050 "CUBE $dst $src0", 1051 [(set v4f32:$dst, (int_r600_cube v4f32:$src0))], 1052 VecALU 1053 > { 1054 let isPseudo = 1; 1055 let UseNamedOperandTable = 1; 1056 } 1057 1058 def _real : R600_2OP <inst, "CUBE", []>; 1059} 1060} // End mayLoad = 0, mayStore = 0, hasSideEffects = 0 1061 1062class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper < 1063 inst, "EXP_IEEE", fexp2 1064> { 1065 let Itinerary = TransALU; 1066} 1067 1068class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper < 1069 inst, "FLT_TO_INT", fp_to_sint 1070> { 1071 let Itinerary = TransALU; 1072} 1073 1074class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper < 1075 inst, "INT_TO_FLT", sint_to_fp 1076> { 1077 let Itinerary = TransALU; 1078} 1079 1080class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper < 1081 inst, "FLT_TO_UINT", fp_to_uint 1082> { 1083 let Itinerary = TransALU; 1084} 1085 1086class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper < 1087 inst, "UINT_TO_FLT", uint_to_fp 1088> { 1089 let Itinerary = TransALU; 1090} 1091 1092class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP < 1093 inst, "LOG_CLAMPED", [] 1094>; 1095 1096class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper < 1097 inst, "LOG_IEEE", flog2 1098> { 1099 let Itinerary = TransALU; 1100} 1101 1102class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>; 1103class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>; 1104class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>; 1105class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper < 1106 inst, "MULHI_INT", mulhs> { 1107 let Itinerary = TransALU; 1108} 1109 1110class MULHI_INT24_Common <bits<11> inst> : R600_2OP_Helper < 1111 inst, "MULHI_INT24", AMDGPUmulhi_i24> { 1112 let Itinerary = VecALU; 1113} 1114 1115class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper < 1116 inst, "MULHI", mulhu> { 1117 let Itinerary = TransALU; 1118} 1119 1120class MULHI_UINT24_Common <bits<11> inst> : R600_2OP_Helper < 1121 inst, "MULHI_UINT24", AMDGPUmulhi_u24> { 1122 let Itinerary = VecALU; 1123} 1124 1125class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper < 1126 inst, "MULLO_INT", mul> { 1127 let Itinerary = TransALU; 1128} 1129class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []> { 1130 let Itinerary = TransALU; 1131} 1132 1133class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP < 1134 inst, "RECIP_CLAMPED", [] 1135> { 1136 let Itinerary = TransALU; 1137} 1138 1139class RECIP_IEEE_Common <bits<11> inst> : R600_1OP < 1140 inst, "RECIP_IEEE", [(set f32:$dst, (AMDGPUrcp f32:$src0))] 1141> { 1142 let Itinerary = TransALU; 1143} 1144 1145class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper < 1146 inst, "RECIP_UINT", AMDGPUurecip 1147> { 1148 let Itinerary = TransALU; 1149} 1150 1151// Clamped to maximum. 1152class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper < 1153 inst, "RECIPSQRT_CLAMPED", AMDGPUrsq_clamp 1154> { 1155 let Itinerary = TransALU; 1156} 1157 1158class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP_Helper < 1159 inst, "RECIPSQRT_IEEE", AMDGPUrsq> { 1160 let Itinerary = TransALU; 1161} 1162 1163// TODO: There is also RECIPSQRT_FF which clamps to zero. 1164 1165class SIN_Common <bits<11> inst> : R600_1OP < 1166 inst, "SIN", [(set f32:$dst, (SIN_HW f32:$src0))]>{ 1167 let Trig = 1; 1168 let Itinerary = TransALU; 1169} 1170 1171class COS_Common <bits<11> inst> : R600_1OP < 1172 inst, "COS", [(set f32:$dst, (COS_HW f32:$src0))]> { 1173 let Trig = 1; 1174 let Itinerary = TransALU; 1175} 1176 1177def FABS_R600 : FABS<R600_Reg32>; 1178def FNEG_R600 : FNEG<R600_Reg32>; 1179 1180//===----------------------------------------------------------------------===// 1181// Helper patterns for complex intrinsics 1182//===----------------------------------------------------------------------===// 1183 1184// FIXME: Should be predicated on unsafe fp math. 1185multiclass DIV_Common <InstR600 recip_ieee> { 1186def : R600Pat< 1187 (fdiv f32:$src0, f32:$src1), 1188 (MUL_IEEE $src0, (recip_ieee $src1)) 1189>; 1190 1191def : RcpPat<recip_ieee, f32>; 1192} 1193 1194//===----------------------------------------------------------------------===// 1195// R600 / R700 Instructions 1196//===----------------------------------------------------------------------===// 1197 1198let Predicates = [isR600] in { 1199 1200 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>; 1201 def MULADD_r600 : MULADD_Common<0x10>; 1202 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>; 1203 def CNDE_r600 : CNDE_Common<0x18>; 1204 def CNDGT_r600 : CNDGT_Common<0x19>; 1205 def CNDGE_r600 : CNDGE_Common<0x1A>; 1206 def DOT4_r600 : DOT4_Common<0x50>; 1207 defm CUBE_r600 : CUBE_Common<0x52>; 1208 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>; 1209 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>; 1210 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>; 1211 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>; 1212 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>; 1213 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>; 1214 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>; 1215 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>; 1216 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>; 1217 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>; 1218 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>; 1219 def SIN_r600 : SIN_Common<0x6E>; 1220 def COS_r600 : COS_Common<0x6F>; 1221 def ASHR_r600 : ASHR_Common<0x70>; 1222 def LSHR_r600 : LSHR_Common<0x71>; 1223 def LSHL_r600 : LSHL_Common<0x72>; 1224 def MULLO_INT_r600 : MULLO_INT_Common<0x73>; 1225 def MULHI_INT_r600 : MULHI_INT_Common<0x74>; 1226 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>; 1227 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>; 1228 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>; 1229 1230 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>; 1231 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL>; 1232 1233 def : R600Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>; 1234 def : RsqPat<RECIPSQRT_IEEE_r600, f32>; 1235 1236 def R600_ExportSwz : ExportSwzInst { 1237 let Word1{20-17} = 0; // BURST_COUNT 1238 let Word1{21} = eop; 1239 let Word1{22} = 0; // VALID_PIXEL_MODE 1240 let Word1{30-23} = inst; 1241 let Word1{31} = 1; // BARRIER 1242 } 1243 defm : ExportPattern<R600_ExportSwz, 39>; 1244 1245 def R600_ExportBuf : ExportBufInst { 1246 let Word1{20-17} = 0; // BURST_COUNT 1247 let Word1{21} = eop; 1248 let Word1{22} = 0; // VALID_PIXEL_MODE 1249 let Word1{30-23} = inst; 1250 let Word1{31} = 1; // BARRIER 1251 } 1252 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>; 1253 1254 def CF_TC_R600 : CF_CLAUSE_R600<1, (ins i32imm:$ADDR, i32imm:$CNT), 1255 "TEX $CNT @$ADDR"> { 1256 let POP_COUNT = 0; 1257 } 1258 def CF_VC_R600 : CF_CLAUSE_R600<2, (ins i32imm:$ADDR, i32imm:$CNT), 1259 "VTX $CNT @$ADDR"> { 1260 let POP_COUNT = 0; 1261 } 1262 def WHILE_LOOP_R600 : CF_CLAUSE_R600<6, (ins i32imm:$ADDR), 1263 "LOOP_START_DX10 @$ADDR"> { 1264 let POP_COUNT = 0; 1265 let CNT = 0; 1266 } 1267 def END_LOOP_R600 : CF_CLAUSE_R600<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> { 1268 let POP_COUNT = 0; 1269 let CNT = 0; 1270 } 1271 def LOOP_BREAK_R600 : CF_CLAUSE_R600<9, (ins i32imm:$ADDR), 1272 "LOOP_BREAK @$ADDR"> { 1273 let POP_COUNT = 0; 1274 let CNT = 0; 1275 } 1276 def CF_CONTINUE_R600 : CF_CLAUSE_R600<8, (ins i32imm:$ADDR), 1277 "CONTINUE @$ADDR"> { 1278 let POP_COUNT = 0; 1279 let CNT = 0; 1280 } 1281 def CF_JUMP_R600 : CF_CLAUSE_R600<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 1282 "JUMP @$ADDR POP:$POP_COUNT"> { 1283 let CNT = 0; 1284 } 1285 def CF_PUSH_ELSE_R600 : CF_CLAUSE_R600<12, (ins i32imm:$ADDR), 1286 "PUSH_ELSE @$ADDR"> { 1287 let CNT = 0; 1288 let POP_COUNT = 0; // FIXME? 1289 } 1290 def CF_ELSE_R600 : CF_CLAUSE_R600<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 1291 "ELSE @$ADDR POP:$POP_COUNT"> { 1292 let CNT = 0; 1293 } 1294 def CF_CALL_FS_R600 : CF_CLAUSE_R600<19, (ins), "CALL_FS"> { 1295 let ADDR = 0; 1296 let CNT = 0; 1297 let POP_COUNT = 0; 1298 } 1299 def POP_R600 : CF_CLAUSE_R600<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 1300 "POP @$ADDR POP:$POP_COUNT"> { 1301 let CNT = 0; 1302 } 1303 def CF_END_R600 : CF_CLAUSE_R600<0, (ins), "CF_END"> { 1304 let CNT = 0; 1305 let POP_COUNT = 0; 1306 let ADDR = 0; 1307 let END_OF_PROGRAM = 1; 1308 } 1309 1310} 1311 1312 1313//===----------------------------------------------------------------------===// 1314// Regist loads and stores - for indirect addressing 1315//===----------------------------------------------------------------------===// 1316 1317let Namespace = "R600" in { 1318defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>; 1319} 1320 1321// Hardcode channel to 0 1322// NOTE: LSHR is not available here. LSHR is per family instruction 1323def : R600Pat < 1324 (i32 (load_private ADDRIndirect:$addr) ), 1325 (R600_RegisterLoad FRAMEri:$addr, (i32 0)) 1326>; 1327def : R600Pat < 1328 (store_private i32:$val, ADDRIndirect:$addr), 1329 (R600_RegisterStore i32:$val, FRAMEri:$addr, (i32 0)) 1330>; 1331 1332 1333//===----------------------------------------------------------------------===// 1334// Pseudo instructions 1335//===----------------------------------------------------------------------===// 1336 1337let isPseudo = 1 in { 1338 1339def PRED_X : InstR600 < 1340 (outs R600_Predicate_Bit:$dst), 1341 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags), 1342 "", [], NullALU> { 1343 let FlagOperandIdx = 3; 1344} 1345 1346let isTerminator = 1, isBranch = 1 in { 1347def JUMP_COND : InstR600 < 1348 (outs), 1349 (ins brtarget:$target, R600_Predicate_Bit:$p), 1350 "JUMP $target ($p)", 1351 [], AnyALU 1352 >; 1353 1354def JUMP : InstR600 < 1355 (outs), 1356 (ins brtarget:$target), 1357 "JUMP $target", 1358 [], AnyALU 1359 > 1360{ 1361 let isPredicable = 1; 1362 let isBarrier = 1; 1363} 1364 1365} // End isTerminator = 1, isBranch = 1 1366 1367let usesCustomInserter = 1 in { 1368 1369let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in { 1370 1371def MASK_WRITE : InstR600 < 1372 (outs), 1373 (ins R600_Reg32:$src), 1374 "MASK_WRITE $src", 1375 [], 1376 NullALU 1377>; 1378 1379} // End mayLoad = 0, mayStore = 0, hasSideEffects = 1 1380 1381 1382def TXD: InstR600 < 1383 (outs R600_Reg128:$dst), 1384 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, 1385 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget), 1386 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget", [], 1387 NullALU > { 1388 let TEXInst = 1; 1389} 1390 1391def TXD_SHADOW: InstR600 < 1392 (outs R600_Reg128:$dst), 1393 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, 1394 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget), 1395 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget", 1396 [], NullALU> { 1397 let TEXInst = 1; 1398} 1399} // End isPseudo = 1 1400} // End usesCustomInserter = 1 1401 1402 1403//===----------------------------------------------------------------------===// 1404// Constant Buffer Addressing Support 1405//===----------------------------------------------------------------------===// 1406 1407let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "R600" in { 1408def CONST_COPY : Instruction { 1409 let OutOperandList = (outs R600_Reg32:$dst); 1410 let InOperandList = (ins i32imm:$src); 1411 let Pattern = 1412 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))]; 1413 let AsmString = "CONST_COPY"; 1414 let hasSideEffects = 0; 1415 let isAsCheapAsAMove = 1; 1416 let Itinerary = NullALU; 1417} 1418} // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" 1419 1420def TEX_VTX_CONSTBUF : 1421 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$buffer_id), "VTX_READ_eg $dst, $ptr", 1422 [(set v4i32:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$buffer_id)))]>, 1423 VTX_WORD1_GPR, VTX_WORD0_eg { 1424 1425 let VC_INST = 0; 1426 let FETCH_TYPE = 2; 1427 let FETCH_WHOLE_QUAD = 0; 1428 let SRC_REL = 0; 1429 let SRC_SEL_X = 0; 1430 let DST_REL = 0; 1431 let USE_CONST_FIELDS = 0; 1432 let NUM_FORMAT_ALL = 2; 1433 let FORMAT_COMP_ALL = 1; 1434 let SRF_MODE_ALL = 1; 1435 let MEGA_FETCH_COUNT = 16; 1436 let DST_SEL_X = 0; 1437 let DST_SEL_Y = 1; 1438 let DST_SEL_Z = 2; 1439 let DST_SEL_W = 3; 1440 let DATA_FORMAT = 35; 1441 1442 let Inst{31-0} = Word0; 1443 let Inst{63-32} = Word1; 1444 1445// LLVM can only encode 64-bit instructions, so these fields are manually 1446// encoded in R600CodeEmitter 1447// 1448// bits<16> OFFSET; 1449// bits<2> ENDIAN_SWAP = 0; 1450// bits<1> CONST_BUF_NO_STRIDE = 0; 1451// bits<1> MEGA_FETCH = 0; 1452// bits<1> ALT_CONST = 0; 1453// bits<2> BUFFER_INDEX_MODE = 0; 1454 1455 1456 1457// VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 1458// is done in R600CodeEmitter 1459// 1460// Inst{79-64} = OFFSET; 1461// Inst{81-80} = ENDIAN_SWAP; 1462// Inst{82} = CONST_BUF_NO_STRIDE; 1463// Inst{83} = MEGA_FETCH; 1464// Inst{84} = ALT_CONST; 1465// Inst{86-85} = BUFFER_INDEX_MODE; 1466// Inst{95-86} = 0; Reserved 1467 1468// VTX_WORD3 (Padding) 1469// 1470// Inst{127-96} = 0; 1471 let VTXInst = 1; 1472} 1473 1474def TEX_VTX_TEXBUF: 1475 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$buffer_id), "TEX_VTX_EXPLICIT_READ $dst, $ptr">, 1476VTX_WORD1_GPR, VTX_WORD0_eg { 1477 1478let VC_INST = 0; 1479let FETCH_TYPE = 2; 1480let FETCH_WHOLE_QUAD = 0; 1481let SRC_REL = 0; 1482let SRC_SEL_X = 0; 1483let DST_REL = 0; 1484let USE_CONST_FIELDS = 1; 1485let NUM_FORMAT_ALL = 0; 1486let FORMAT_COMP_ALL = 0; 1487let SRF_MODE_ALL = 1; 1488let MEGA_FETCH_COUNT = 16; 1489let DST_SEL_X = 0; 1490let DST_SEL_Y = 1; 1491let DST_SEL_Z = 2; 1492let DST_SEL_W = 3; 1493let DATA_FORMAT = 0; 1494 1495let Inst{31-0} = Word0; 1496let Inst{63-32} = Word1; 1497 1498// LLVM can only encode 64-bit instructions, so these fields are manually 1499// encoded in R600CodeEmitter 1500// 1501// bits<16> OFFSET; 1502// bits<2> ENDIAN_SWAP = 0; 1503// bits<1> CONST_BUF_NO_STRIDE = 0; 1504// bits<1> MEGA_FETCH = 0; 1505// bits<1> ALT_CONST = 0; 1506// bits<2> BUFFER_INDEX_MODE = 0; 1507 1508 1509 1510// VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 1511// is done in R600CodeEmitter 1512// 1513// Inst{79-64} = OFFSET; 1514// Inst{81-80} = ENDIAN_SWAP; 1515// Inst{82} = CONST_BUF_NO_STRIDE; 1516// Inst{83} = MEGA_FETCH; 1517// Inst{84} = ALT_CONST; 1518// Inst{86-85} = BUFFER_INDEX_MODE; 1519// Inst{95-86} = 0; Reserved 1520 1521// VTX_WORD3 (Padding) 1522// 1523// Inst{127-96} = 0; 1524 let VTXInst = 1; 1525} 1526 1527//===---------------------------------------------------------------------===// 1528// Flow and Program control Instructions 1529//===---------------------------------------------------------------------===// 1530 1531multiclass BranchConditional<SDNode Op, RegisterClass rci, RegisterClass rcf> { 1532 def _i32 : ILFormat<(outs), 1533 (ins brtarget:$target, rci:$src0), 1534 "; i32 Pseudo branch instruction", 1535 [(Op bb:$target, (i32 rci:$src0))]>; 1536 def _f32 : ILFormat<(outs), 1537 (ins brtarget:$target, rcf:$src0), 1538 "; f32 Pseudo branch instruction", 1539 [(Op bb:$target, (f32 rcf:$src0))]>; 1540} 1541 1542// Only scalar types should generate flow control 1543multiclass BranchInstr<string name> { 1544 def _i32 : ILFormat<(outs), (ins R600_Reg32:$src), 1545 !strconcat(name, " $src"), []>; 1546 def _f32 : ILFormat<(outs), (ins R600_Reg32:$src), 1547 !strconcat(name, " $src"), []>; 1548} 1549// Only scalar types should generate flow control 1550multiclass BranchInstr2<string name> { 1551 def _i32 : ILFormat<(outs), (ins R600_Reg32:$src0, R600_Reg32:$src1), 1552 !strconcat(name, " $src0, $src1"), []>; 1553 def _f32 : ILFormat<(outs), (ins R600_Reg32:$src0, R600_Reg32:$src1), 1554 !strconcat(name, " $src0, $src1"), []>; 1555} 1556 1557//===---------------------------------------------------------------------===// 1558// Custom Inserter for Branches and returns, this eventually will be a 1559// separate pass 1560//===---------------------------------------------------------------------===// 1561let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1, 1562 Namespace = "R600" in { 1563 def BRANCH : ILFormat<(outs), (ins brtarget:$target), 1564 "; Pseudo unconditional branch instruction", 1565 [(br bb:$target)]>; 1566 defm BRANCH_COND : BranchConditional<IL_brcond, R600_Reg32, R600_Reg32>; 1567} 1568 1569//===----------------------------------------------------------------------===// 1570// Branch Instructions 1571//===----------------------------------------------------------------------===// 1572 1573def IF_PREDICATE_SET : ILFormat<(outs), (ins R600_Reg32:$src), 1574 "IF_PREDICATE_SET $src", []>; 1575 1576let isTerminator=1 in { 1577 def BREAK : ILFormat< (outs), (ins), 1578 "BREAK", []>; 1579 def CONTINUE : ILFormat< (outs), (ins), 1580 "CONTINUE", []>; 1581 def DEFAULT : ILFormat< (outs), (ins), 1582 "DEFAULT", []>; 1583 def ELSE : ILFormat< (outs), (ins), 1584 "ELSE", []>; 1585 def ENDSWITCH : ILFormat< (outs), (ins), 1586 "ENDSWITCH", []>; 1587 def ENDMAIN : ILFormat< (outs), (ins), 1588 "ENDMAIN", []>; 1589 def END : ILFormat< (outs), (ins), 1590 "END", []>; 1591 def ENDFUNC : ILFormat< (outs), (ins), 1592 "ENDFUNC", []>; 1593 def ENDIF : ILFormat< (outs), (ins), 1594 "ENDIF", []>; 1595 def WHILELOOP : ILFormat< (outs), (ins), 1596 "WHILE", []>; 1597 def ENDLOOP : ILFormat< (outs), (ins), 1598 "ENDLOOP", []>; 1599 def FUNC : ILFormat< (outs), (ins), 1600 "FUNC", []>; 1601 def RETDYN : ILFormat< (outs), (ins), 1602 "RET_DYN", []>; 1603 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1604 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">; 1605 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1606 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">; 1607 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1608 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">; 1609 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1610 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">; 1611 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1612 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">; 1613 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1614 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">; 1615 defm IFC : BranchInstr2<"IFC">; 1616 defm BREAKC : BranchInstr2<"BREAKC">; 1617 defm CONTINUEC : BranchInstr2<"CONTINUEC">; 1618} 1619 1620//===----------------------------------------------------------------------===// 1621// Indirect addressing pseudo instructions 1622//===----------------------------------------------------------------------===// 1623 1624let isPseudo = 1 in { 1625 1626class ExtractVertical <RegisterClass vec_rc> : InstR600 < 1627 (outs R600_Reg32:$dst), 1628 (ins vec_rc:$vec, R600_Reg32:$index), "", 1629 [], 1630 AnyALU 1631>; 1632 1633let Constraints = "$dst = $vec" in { 1634 1635class InsertVertical <RegisterClass vec_rc> : InstR600 < 1636 (outs vec_rc:$dst), 1637 (ins vec_rc:$vec, R600_Reg32:$value, R600_Reg32:$index), "", 1638 [], 1639 AnyALU 1640>; 1641 1642} // End Constraints = "$dst = $vec" 1643 1644} // End isPseudo = 1 1645 1646def R600_EXTRACT_ELT_V2 : ExtractVertical <R600_Reg64Vertical>; 1647def R600_EXTRACT_ELT_V4 : ExtractVertical <R600_Reg128Vertical>; 1648 1649def R600_INSERT_ELT_V2 : InsertVertical <R600_Reg64Vertical>; 1650def R600_INSERT_ELT_V4 : InsertVertical <R600_Reg128Vertical>; 1651 1652class ExtractVerticalPat <Instruction inst, ValueType vec_ty, 1653 ValueType scalar_ty> : R600Pat < 1654 (scalar_ty (extractelt vec_ty:$vec, i32:$index)), 1655 (inst $vec, $index) 1656>; 1657 1658def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2i32, i32>; 1659def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2f32, f32>; 1660def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4i32, i32>; 1661def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4f32, f32>; 1662 1663class InsertVerticalPat <Instruction inst, ValueType vec_ty, 1664 ValueType scalar_ty> : R600Pat < 1665 (vec_ty (insertelt vec_ty:$vec, scalar_ty:$value, i32:$index)), 1666 (inst $vec, $value, $index) 1667>; 1668 1669def : InsertVerticalPat <R600_INSERT_ELT_V2, v2i32, i32>; 1670def : InsertVerticalPat <R600_INSERT_ELT_V2, v2f32, f32>; 1671def : InsertVerticalPat <R600_INSERT_ELT_V4, v4i32, i32>; 1672def : InsertVerticalPat <R600_INSERT_ELT_V4, v4f32, f32>; 1673 1674//===----------------------------------------------------------------------===// 1675// ISel Patterns 1676//===----------------------------------------------------------------------===// 1677 1678let SubtargetPredicate = isR600toCayman in { 1679 1680// CND*_INT Patterns for f32 True / False values 1681 1682class CND_INT_f32 <InstR600 cnd, CondCode cc> : R600Pat < 1683 (selectcc i32:$src0, 0, f32:$src1, f32:$src2, cc), 1684 (cnd $src0, $src1, $src2) 1685>; 1686 1687def : CND_INT_f32 <CNDE_INT, SETEQ>; 1688def : CND_INT_f32 <CNDGT_INT, SETGT>; 1689def : CND_INT_f32 <CNDGE_INT, SETGE>; 1690 1691//CNDGE_INT extra pattern 1692def : R600Pat < 1693 (selectcc i32:$src0, -1, i32:$src1, i32:$src2, COND_SGT), 1694 (CNDGE_INT $src0, $src1, $src2) 1695>; 1696 1697// KIL Patterns 1698def KIL : R600Pat < 1699 (int_r600_kill f32:$src0), 1700 (MASK_WRITE (KILLGT (f32 ZERO), $src0)) 1701>; 1702 1703def : Extract_Element <f32, v4f32, 0, sub0>; 1704def : Extract_Element <f32, v4f32, 1, sub1>; 1705def : Extract_Element <f32, v4f32, 2, sub2>; 1706def : Extract_Element <f32, v4f32, 3, sub3>; 1707 1708def : Insert_Element <f32, v4f32, 0, sub0>; 1709def : Insert_Element <f32, v4f32, 1, sub1>; 1710def : Insert_Element <f32, v4f32, 2, sub2>; 1711def : Insert_Element <f32, v4f32, 3, sub3>; 1712 1713def : Extract_Element <i32, v4i32, 0, sub0>; 1714def : Extract_Element <i32, v4i32, 1, sub1>; 1715def : Extract_Element <i32, v4i32, 2, sub2>; 1716def : Extract_Element <i32, v4i32, 3, sub3>; 1717 1718def : Insert_Element <i32, v4i32, 0, sub0>; 1719def : Insert_Element <i32, v4i32, 1, sub1>; 1720def : Insert_Element <i32, v4i32, 2, sub2>; 1721def : Insert_Element <i32, v4i32, 3, sub3>; 1722 1723def : Extract_Element <f32, v2f32, 0, sub0>; 1724def : Extract_Element <f32, v2f32, 1, sub1>; 1725 1726def : Insert_Element <f32, v2f32, 0, sub0>; 1727def : Insert_Element <f32, v2f32, 1, sub1>; 1728 1729def : Extract_Element <i32, v2i32, 0, sub0>; 1730def : Extract_Element <i32, v2i32, 1, sub1>; 1731 1732def : Insert_Element <i32, v2i32, 0, sub0>; 1733def : Insert_Element <i32, v2i32, 1, sub1>; 1734 1735// bitconvert patterns 1736 1737def : BitConvert <i32, f32, R600_Reg32>; 1738def : BitConvert <f32, i32, R600_Reg32>; 1739def : BitConvert <v2f32, v2i32, R600_Reg64>; 1740def : BitConvert <v2i32, v2f32, R600_Reg64>; 1741def : BitConvert <v4f32, v4i32, R600_Reg128>; 1742def : BitConvert <v4i32, v4f32, R600_Reg128>; 1743 1744// DWORDADDR pattern 1745def : DwordAddrPat <i32, R600_Reg32>; 1746 1747} // End SubtargetPredicate = isR600toCayman 1748 1749def getLDSNoRetOp : InstrMapping { 1750 let FilterClass = "R600_LDS_1A1D"; 1751 let RowFields = ["BaseOp"]; 1752 let ColFields = ["DisableEncoding"]; 1753 let KeyCol = ["$dst"]; 1754 let ValueCols = [[""""]]; 1755} 1756