1//===-- VOP2Instructions.td - Vector Instruction Defintions ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// VOP2 Classes 12//===----------------------------------------------------------------------===// 13 14class VOP2e <bits<6> op, VOPProfile P> : Enc32 { 15 bits<8> vdst; 16 bits<9> src0; 17 bits<8> src1; 18 19 let Inst{8-0} = !if(P.HasSrc0, src0, 0); 20 let Inst{16-9} = !if(P.HasSrc1, src1, 0); 21 let Inst{24-17} = !if(P.EmitDst, vdst, 0); 22 let Inst{30-25} = op; 23 let Inst{31} = 0x0; //encoding 24} 25 26class VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 { 27 bits<8> vdst; 28 bits<9> src0; 29 bits<8> src1; 30 bits<32> imm; 31 32 let Inst{8-0} = !if(P.HasSrc0, src0, 0); 33 let Inst{16-9} = !if(P.HasSrc1, src1, 0); 34 let Inst{24-17} = !if(P.EmitDst, vdst, 0); 35 let Inst{30-25} = op; 36 let Inst{31} = 0x0; // encoding 37 let Inst{63-32} = imm; 38} 39 40class VOP2_SDWAe <bits<6> op, VOPProfile P> : VOP_SDWAe <P> { 41 bits<8> vdst; 42 bits<8> src1; 43 44 let Inst{8-0} = 0xf9; // sdwa 45 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 46 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 47 let Inst{30-25} = op; 48 let Inst{31} = 0x0; // encoding 49} 50 51class VOP2_SDWA9Ae <bits<6> op, VOPProfile P> : VOP_SDWA9Ae <P> { 52 bits<8> vdst; 53 bits<9> src1; 54 55 let Inst{8-0} = 0xf9; // sdwa 56 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 57 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 58 let Inst{30-25} = op; 59 let Inst{31} = 0x0; // encoding 60 let Inst{63} = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr 61} 62 63class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> : 64 VOP_Pseudo <opName, suffix, P, P.Outs32, P.Ins32, "", pattern> { 65 66 let AsmOperands = P.Asm32; 67 68 let Size = 4; 69 let mayLoad = 0; 70 let mayStore = 0; 71 let hasSideEffects = 0; 72 let SubtargetPredicate = isGCN; 73 74 let VOP2 = 1; 75 let VALU = 1; 76 let Uses = [EXEC]; 77 78 let AsmVariantName = AMDGPUAsmVariants.Default; 79} 80 81class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> : 82 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 83 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 84 85 let isPseudo = 0; 86 let isCodeGenOnly = 0; 87 88 let Constraints = ps.Constraints; 89 let DisableEncoding = ps.DisableEncoding; 90 91 // copy relevant pseudo op flags 92 let SubtargetPredicate = ps.SubtargetPredicate; 93 let AsmMatchConverter = ps.AsmMatchConverter; 94 let AsmVariantName = ps.AsmVariantName; 95 let Constraints = ps.Constraints; 96 let DisableEncoding = ps.DisableEncoding; 97 let TSFlags = ps.TSFlags; 98 let UseNamedOperandTable = ps.UseNamedOperandTable; 99 let Uses = ps.Uses; 100 let Defs = ps.Defs; 101} 102 103class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> : 104 VOP_SDWA_Pseudo <OpName, P, pattern> { 105 let AsmMatchConverter = "cvtSdwaVOP2"; 106} 107 108class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies { 109 list<dag> ret = !if(P.HasModifiers, 110 [(set P.DstVT:$vdst, 111 (node (P.Src0VT 112 !if(P.HasOMod, 113 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 114 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))), 115 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], 116 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]); 117} 118 119multiclass VOP2Inst <string opName, 120 VOPProfile P, 121 SDPatternOperator node = null_frag, 122 string revOp = opName, 123 bit GFX9Renamed = 0> { 124 125 let renamedInGFX9 = GFX9Renamed in { 126 127 def _e32 : VOP2_Pseudo <opName, P>, 128 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>; 129 130 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>, 131 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>; 132 133 def _sdwa : VOP2_SDWA_Pseudo <opName, P>; 134 135 } 136} 137 138multiclass VOP2bInst <string opName, 139 VOPProfile P, 140 SDPatternOperator node = null_frag, 141 string revOp = opName, 142 bit GFX9Renamed = 0, 143 bit useSGPRInput = !eq(P.NumSrcArgs, 3)> { 144 let renamedInGFX9 = GFX9Renamed in { 145 let SchedRW = [Write32Bit, WriteSALU] in { 146 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in { 147 def _e32 : VOP2_Pseudo <opName, P>, 148 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>; 149 150 def _sdwa : VOP2_SDWA_Pseudo <opName, P> { 151 let AsmMatchConverter = "cvtSdwaVOP2b"; 152 } 153 } 154 155 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>, 156 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>; 157 } 158 } 159} 160 161multiclass VOP2eInst <string opName, 162 VOPProfile P, 163 SDPatternOperator node = null_frag, 164 string revOp = opName, 165 bit useSGPRInput = !eq(P.NumSrcArgs, 3)> { 166 167 let SchedRW = [Write32Bit] in { 168 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in { 169 def _e32 : VOP2_Pseudo <opName, P>, 170 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>; 171 172 def _sdwa : VOP2_SDWA_Pseudo <opName, P> { 173 let AsmMatchConverter = "cvtSdwaVOP2b"; 174 } 175 } 176 177 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>, 178 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>; 179 } 180} 181 182class VOP_MADAK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> { 183 field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm); 184 field dag Ins32 = (ins VCSrc_f32:$src0, VGPR_32:$src1, ImmOpType:$imm); 185 field bit HasExt = 0; 186 187 // Hack to stop printing _e64 188 let DstRC = RegisterOperand<VGPR_32>; 189 field string Asm32 = " $vdst, $src0, $src1, $imm"; 190} 191 192def VOP_MADAK_F16 : VOP_MADAK <f16>; 193def VOP_MADAK_F32 : VOP_MADAK <f32>; 194 195class VOP_MADMK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> { 196 field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm); 197 field dag Ins32 = (ins VCSrc_f32:$src0, ImmOpType:$imm, VGPR_32:$src1); 198 field bit HasExt = 0; 199 200 // Hack to stop printing _e64 201 let DstRC = RegisterOperand<VGPR_32>; 202 field string Asm32 = " $vdst, $src0, $imm, $src1"; 203} 204 205def VOP_MADMK_F16 : VOP_MADMK <f16>; 206def VOP_MADMK_F32 : VOP_MADMK <f32>; 207 208// FIXME: Remove src2_modifiers. It isn't used, so is wasting memory 209// and processing time but it makes it easier to convert to mad. 210class VOP_MAC <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> { 211 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2); 212 let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3, 213 0, HasModifiers, HasOMod, Src0Mod, Src1Mod, Src2Mod>.ret; 214 let InsDPP = (ins DstRCDPP:$old, 215 Src0ModDPP:$src0_modifiers, Src0DPP:$src0, 216 Src1ModDPP:$src1_modifiers, Src1DPP:$src1, 217 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 218 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 219 220 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 221 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 222 VGPR_32:$src2, // stub argument 223 clampmod:$clamp, omod:$omod, 224 dst_sel:$dst_sel, dst_unused:$dst_unused, 225 src0_sel:$src0_sel, src1_sel:$src1_sel); 226 let Asm32 = getAsm32<1, 2, vt>.ret; 227 let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, vt>.ret; 228 let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt>.ret; 229 let AsmSDWA = getAsmSDWA<1, 2, vt>.ret; 230 let AsmSDWA9 = getAsmSDWA9<1, 1, 2, vt>.ret; 231 let HasSrc2 = 0; 232 let HasSrc2Mods = 0; 233 let HasExt = 1; 234 let HasSDWA9 = 0; 235} 236 237def VOP_MAC_F16 : VOP_MAC <f16> { 238 // FIXME: Move 'Asm64' definition to VOP_MAC, and use 'vt'. Currently it gives 239 // 'not a string initializer' error. 240 let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, f16>.ret; 241} 242 243def VOP_MAC_F32 : VOP_MAC <f32> { 244 // FIXME: Move 'Asm64' definition to VOP_MAC, and use 'vt'. Currently it gives 245 // 'not a string initializer' error. 246 let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, f32>.ret; 247} 248 249// Write out to vcc or arbitrary SGPR. 250def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped]> { 251 let Asm32 = "$vdst, vcc, $src0, $src1"; 252 let Asm64 = "$vdst, $sdst, $src0, $src1"; 253 let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 254 let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 255 let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 256 let Outs32 = (outs DstRC:$vdst); 257 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst); 258} 259 260// Write out to vcc or arbitrary SGPR and read in from vcc or 261// arbitrary SGPR. 262def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> { 263 // We use VCSrc_b32 to exclude literal constants, even though the 264 // encoding normally allows them since the implicit VCC use means 265 // using one would always violate the constant bus 266 // restriction. SGPRs are still allowed because it should 267 // technically be possible to use VCC again as src0. 268 let Src0RC32 = VCSrc_b32; 269 let Asm32 = "$vdst, vcc, $src0, $src1, vcc"; 270 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2"; 271 let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 272 let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 273 let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 274 let Outs32 = (outs DstRC:$vdst); 275 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst); 276 277 // Suppress src2 implied by type since the 32-bit encoding uses an 278 // implicit VCC use. 279 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1); 280 281 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 282 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 283 clampmod:$clamp, 284 dst_sel:$dst_sel, dst_unused:$dst_unused, 285 src0_sel:$src0_sel, src1_sel:$src1_sel); 286 287 let InsDPP = (ins DstRCDPP:$old, 288 Src0DPP:$src0, 289 Src1DPP:$src1, 290 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 291 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 292 let HasExt = 1; 293 let HasSDWA9 = 1; 294} 295 296// Read in from vcc or arbitrary SGPR 297def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> { 298 let Src0RC32 = VCSrc_b32; // See comment in def VOP2b_I32_I1_I32_I32_I1 above. 299 let Asm32 = "$vdst, $src0, $src1, vcc"; 300 let Asm64 = "$vdst, $src0, $src1, $src2"; 301 let AsmSDWA = "$vdst, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 302 let AsmSDWA9 = "$vdst, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 303 let AsmDPP = "$vdst, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 304 305 let Outs32 = (outs DstRC:$vdst); 306 let Outs64 = (outs DstRC:$vdst); 307 308 // Suppress src2 implied by type since the 32-bit encoding uses an 309 // implicit VCC use. 310 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1); 311 312 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 313 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 314 clampmod:$clamp, 315 dst_sel:$dst_sel, dst_unused:$dst_unused, 316 src0_sel:$src0_sel, src1_sel:$src1_sel); 317 318 let InsDPP = (ins DstRCDPP:$old, 319 Src0DPP:$src0, 320 Src1DPP:$src1, 321 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 322 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 323 let HasExt = 1; 324 let HasSDWA9 = 1; 325} 326 327def VOP_READLANE : VOPProfile<[i32, i32, i32]> { 328 let Outs32 = (outs SReg_32:$vdst); 329 let Outs64 = Outs32; 330 let Ins32 = (ins VGPR_32:$src0, SCSrc_b32:$src1); 331 let Ins64 = Ins32; 332 let Asm32 = " $vdst, $src0, $src1"; 333 let Asm64 = Asm32; 334 let HasExt = 0; 335 let HasSDWA9 = 0; 336} 337 338def VOP_WRITELANE : VOPProfile<[i32, i32, i32, i32]> { 339 let Outs32 = (outs VGPR_32:$vdst); 340 let Outs64 = Outs32; 341 let Ins32 = (ins SCSrc_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in); 342 let Ins64 = Ins32; 343 let Asm32 = " $vdst, $src0, $src1"; 344 let Asm64 = Asm32; 345 let HasExt = 0; 346 let HasSDWA9 = 0; 347 let HasSrc2 = 0; 348 let HasSrc2Mods = 0; 349} 350 351//===----------------------------------------------------------------------===// 352// VOP2 Instructions 353//===----------------------------------------------------------------------===// 354 355let SubtargetPredicate = isGCN in { 356 357defm V_CNDMASK_B32 : VOP2eInst <"v_cndmask_b32", VOP2e_I32_I32_I32_I1>; 358def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, [], "">; 359 360let isCommutable = 1 in { 361defm V_ADD_F32 : VOP2Inst <"v_add_f32", VOP_F32_F32_F32, fadd>; 362defm V_SUB_F32 : VOP2Inst <"v_sub_f32", VOP_F32_F32_F32, fsub>; 363defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32">; 364defm V_MUL_LEGACY_F32 : VOP2Inst <"v_mul_legacy_f32", VOP_F32_F32_F32, AMDGPUfmul_legacy>; 365defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, fmul>; 366defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32, AMDGPUmul_i24>; 367defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_I32_I32_I32, AMDGPUmulhi_i24>; 368defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32, AMDGPUmul_u24>; 369defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_I32_I32_I32, AMDGPUmulhi_u24>; 370defm V_MIN_F32 : VOP2Inst <"v_min_f32", VOP_F32_F32_F32, fminnum>; 371defm V_MAX_F32 : VOP2Inst <"v_max_f32", VOP_F32_F32_F32, fmaxnum>; 372defm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_I32_I32_I32>; 373defm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_I32_I32_I32>; 374defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_I32_I32_I32>; 375defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_I32_I32_I32>; 376defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, null_frag, "v_lshr_b32">; 377defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, null_frag, "v_ashr_i32">; 378defm V_LSHLREV_B32 : VOP2Inst <"v_lshlrev_b32", VOP_I32_I32_I32, null_frag, "v_lshl_b32">; 379defm V_AND_B32 : VOP2Inst <"v_and_b32", VOP_I32_I32_I32>; 380defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_I32_I32_I32>; 381defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_I32_I32_I32>; 382 383let Constraints = "$vdst = $src2", DisableEncoding="$src2", 384 isConvertibleToThreeAddress = 1 in { 385defm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>; 386} 387 388def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32, [], "">; 389 390// No patterns so that the scalar instructions are always selected. 391// The scalar versions will be replaced with vector when needed later. 392 393// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in VI, 394// but the VI instructions behave the same as the SI versions. 395defm V_ADD_I32 : VOP2bInst <"v_add_i32", VOP2b_I32_I1_I32_I32, null_frag, "v_add_i32", 1>; 396defm V_SUB_I32 : VOP2bInst <"v_sub_i32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_i32", 1>; 397defm V_SUBREV_I32 : VOP2bInst <"v_subrev_i32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_i32", 1>; 398defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_addc_u32", 1>; 399defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>; 400defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>; 401 402 403let SubtargetPredicate = HasAddNoCarryInsts in { 404defm V_ADD_U32 : VOP2Inst <"v_add_u32", VOP_I32_I32_I32, null_frag, "v_add_u32", 1>; 405defm V_SUB_U32 : VOP2Inst <"v_sub_u32", VOP_I32_I32_I32, null_frag, "v_sub_u32", 1>; 406defm V_SUBREV_U32 : VOP2Inst <"v_subrev_u32", VOP_I32_I32_I32, null_frag, "v_sub_u32", 1>; 407} 408 409} // End isCommutable = 1 410 411// These are special and do not read the exec mask. 412let isConvergent = 1, Uses = []<Register> in { 413def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE, 414 [(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))], "">; 415 416let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in { 417def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE, 418 [(set i32:$vdst, (int_amdgcn_writelane i32:$src0, i32:$src1, i32:$vdst_in))], "">; 419} // End $vdst = $vdst_in, DisableEncoding $vdst_in 420} // End isConvergent = 1 421 422defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_NO_EXT<VOP_I32_I32_I32>>; 423defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>>; 424defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_lo>; 425defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_hi>; 426defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_NO_EXT<VOP_F32_F32_I32>, AMDGPUldexp>; 427defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_NO_EXT<VOP_I32_F32_I32>>; // TODO: set "Uses = dst" 428defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_NO_EXT<VOP_I32_F32_F32>, AMDGPUpknorm_i16_f32>; 429defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_NO_EXT<VOP_I32_F32_F32>, AMDGPUpknorm_u16_f32>; 430defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_NO_EXT<VOP_I32_F32_F32>, AMDGPUpkrtz_f16_f32>; 431defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_NO_EXT<VOP_I32_I32_I32>, AMDGPUpk_u16_u32>; 432defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT<VOP_I32_I32_I32>, AMDGPUpk_i16_i32>; 433 434} // End SubtargetPredicate = isGCN 435 436def : GCNPat< 437 (AMDGPUadde i32:$src0, i32:$src1, i1:$src2), 438 (V_ADDC_U32_e64 $src0, $src1, $src2) 439>; 440 441def : GCNPat< 442 (AMDGPUsube i32:$src0, i32:$src1, i1:$src2), 443 (V_SUBB_U32_e64 $src0, $src1, $src2) 444>; 445 446// These instructions only exist on SI and CI 447let SubtargetPredicate = isSICI in { 448 449defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>; 450defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>; 451 452let isCommutable = 1 in { 453defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_F32_F32_F32>; 454defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_I32_I32_I32>; 455defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_I32_I32_I32>; 456defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_I32_I32_I32>; 457} // End isCommutable = 1 458 459} // End let SubtargetPredicate = SICI 460 461let SubtargetPredicate = Has16BitInsts in { 462 463def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16, [], "">; 464defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16>; 465defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16>; 466defm V_ASHRREV_I16 : VOP2Inst <"v_ashrrev_i16", VOP_I16_I16_I16>; 467defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>; 468 469let isCommutable = 1 in { 470defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, fadd>; 471defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, fsub>; 472defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">; 473defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, fmul>; 474def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">; 475defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16>; 476defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16>; 477defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16, null_frag, "v_sub_u16">; 478defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16>; 479defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum>; 480defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum>; 481defm V_MAX_U16 : VOP2Inst <"v_max_u16", VOP_I16_I16_I16>; 482defm V_MAX_I16 : VOP2Inst <"v_max_i16", VOP_I16_I16_I16>; 483defm V_MIN_U16 : VOP2Inst <"v_min_u16", VOP_I16_I16_I16>; 484defm V_MIN_I16 : VOP2Inst <"v_min_i16", VOP_I16_I16_I16>; 485 486let Constraints = "$vdst = $src2", DisableEncoding="$src2", 487 isConvertibleToThreeAddress = 1 in { 488defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>; 489} 490} // End isCommutable = 1 491 492} // End SubtargetPredicate = Has16BitInsts 493 494let SubtargetPredicate = HasDLInsts in { 495 496defm V_XNOR_B32 : VOP2Inst <"v_xnor_b32", VOP_I32_I32_I32>; 497 498let Constraints = "$vdst = $src2", 499 DisableEncoding="$src2", 500 isConvertibleToThreeAddress = 1, 501 isCommutable = 1 in { 502defm V_FMAC_F32 : VOP2Inst <"v_fmac_f32", VOP_MAC_F32>; 503} 504 505} // End SubtargetPredicate = HasDLInsts 506 507// Note: 16-bit instructions produce a 0 result in the high 16-bits. 508multiclass Arithmetic_i16_Pats <SDPatternOperator op, Instruction inst> { 509 510def : GCNPat< 511 (op i16:$src0, i16:$src1), 512 (inst $src0, $src1) 513>; 514 515def : GCNPat< 516 (i32 (zext (op i16:$src0, i16:$src1))), 517 (inst $src0, $src1) 518>; 519 520def : GCNPat< 521 (i64 (zext (op i16:$src0, i16:$src1))), 522 (REG_SEQUENCE VReg_64, 523 (inst $src0, $src1), sub0, 524 (V_MOV_B32_e32 (i32 0)), sub1) 525>; 526 527} 528 529multiclass Bits_OpsRev_i16_Pats <SDPatternOperator op, Instruction inst> { 530 531def : GCNPat< 532 (op i16:$src0, i16:$src1), 533 (inst $src1, $src0) 534>; 535 536def : GCNPat< 537 (i32 (zext (op i16:$src0, i16:$src1))), 538 (inst $src1, $src0) 539>; 540 541 542def : GCNPat< 543 (i64 (zext (op i16:$src0, i16:$src1))), 544 (REG_SEQUENCE VReg_64, 545 (inst $src1, $src0), sub0, 546 (V_MOV_B32_e32 (i32 0)), sub1) 547>; 548} 549 550class ZExt_i16_i1_Pat <SDNode ext> : GCNPat < 551 (i16 (ext i1:$src)), 552 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src) 553>; 554 555let Predicates = [Has16BitInsts] in { 556 557defm : Arithmetic_i16_Pats<add, V_ADD_U16_e64>; 558defm : Arithmetic_i16_Pats<mul, V_MUL_LO_U16_e64>; 559defm : Arithmetic_i16_Pats<sub, V_SUB_U16_e64>; 560defm : Arithmetic_i16_Pats<smin, V_MIN_I16_e64>; 561defm : Arithmetic_i16_Pats<smax, V_MAX_I16_e64>; 562defm : Arithmetic_i16_Pats<umin, V_MIN_U16_e64>; 563defm : Arithmetic_i16_Pats<umax, V_MAX_U16_e64>; 564 565def : GCNPat < 566 (and i16:$src0, i16:$src1), 567 (V_AND_B32_e64 $src0, $src1) 568>; 569 570def : GCNPat < 571 (or i16:$src0, i16:$src1), 572 (V_OR_B32_e64 $src0, $src1) 573>; 574 575def : GCNPat < 576 (xor i16:$src0, i16:$src1), 577 (V_XOR_B32_e64 $src0, $src1) 578>; 579 580defm : Bits_OpsRev_i16_Pats<shl, V_LSHLREV_B16_e64>; 581defm : Bits_OpsRev_i16_Pats<srl, V_LSHRREV_B16_e64>; 582defm : Bits_OpsRev_i16_Pats<sra, V_ASHRREV_I16_e64>; 583 584def : ZExt_i16_i1_Pat<zext>; 585def : ZExt_i16_i1_Pat<anyext>; 586 587def : GCNPat < 588 (i16 (sext i1:$src)), 589 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src) 590>; 591 592// Undo sub x, c -> add x, -c canonicalization since c is more likely 593// an inline immediate than -c. 594// TODO: Also do for 64-bit. 595def : GCNPat< 596 (add i16:$src0, (i16 NegSubInlineConst16:$src1)), 597 (V_SUB_U16_e64 $src0, NegSubInlineConst16:$src1) 598>; 599 600} // End Predicates = [Has16BitInsts] 601 602//===----------------------------------------------------------------------===// 603// SI 604//===----------------------------------------------------------------------===// 605 606let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in { 607 608multiclass VOP2_Real_si <bits<6> op> { 609 def _si : 610 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>, 611 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 612} 613 614multiclass VOP2_Real_MADK_si <bits<6> op> { 615 def _si : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>, 616 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 617} 618 619multiclass VOP2_Real_e32_si <bits<6> op> { 620 def _e32_si : 621 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>, 622 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>; 623} 624 625multiclass VOP2_Real_e32e64_si <bits<6> op> : VOP2_Real_e32_si<op> { 626 def _e64_si : 627 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 628 VOP3e_si <{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 629} 630 631multiclass VOP2be_Real_e32e64_si <bits<6> op> : VOP2_Real_e32_si<op> { 632 def _e64_si : 633 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 634 VOP3be_si <{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 635} 636 637} // End AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" 638 639defm V_CNDMASK_B32 : VOP2_Real_e32e64_si <0x0>; 640defm V_ADD_F32 : VOP2_Real_e32e64_si <0x3>; 641defm V_SUB_F32 : VOP2_Real_e32e64_si <0x4>; 642defm V_SUBREV_F32 : VOP2_Real_e32e64_si <0x5>; 643defm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_si <0x7>; 644defm V_MUL_F32 : VOP2_Real_e32e64_si <0x8>; 645defm V_MUL_I32_I24 : VOP2_Real_e32e64_si <0x9>; 646defm V_MUL_HI_I32_I24 : VOP2_Real_e32e64_si <0xa>; 647defm V_MUL_U32_U24 : VOP2_Real_e32e64_si <0xb>; 648defm V_MUL_HI_U32_U24 : VOP2_Real_e32e64_si <0xc>; 649defm V_MIN_F32 : VOP2_Real_e32e64_si <0xf>; 650defm V_MAX_F32 : VOP2_Real_e32e64_si <0x10>; 651defm V_MIN_I32 : VOP2_Real_e32e64_si <0x11>; 652defm V_MAX_I32 : VOP2_Real_e32e64_si <0x12>; 653defm V_MIN_U32 : VOP2_Real_e32e64_si <0x13>; 654defm V_MAX_U32 : VOP2_Real_e32e64_si <0x14>; 655defm V_LSHRREV_B32 : VOP2_Real_e32e64_si <0x16>; 656defm V_ASHRREV_I32 : VOP2_Real_e32e64_si <0x18>; 657defm V_LSHLREV_B32 : VOP2_Real_e32e64_si <0x1a>; 658defm V_AND_B32 : VOP2_Real_e32e64_si <0x1b>; 659defm V_OR_B32 : VOP2_Real_e32e64_si <0x1c>; 660defm V_XOR_B32 : VOP2_Real_e32e64_si <0x1d>; 661defm V_MAC_F32 : VOP2_Real_e32e64_si <0x1f>; 662defm V_MADMK_F32 : VOP2_Real_MADK_si <0x20>; 663defm V_MADAK_F32 : VOP2_Real_MADK_si <0x21>; 664defm V_ADD_I32 : VOP2be_Real_e32e64_si <0x25>; 665defm V_SUB_I32 : VOP2be_Real_e32e64_si <0x26>; 666defm V_SUBREV_I32 : VOP2be_Real_e32e64_si <0x27>; 667defm V_ADDC_U32 : VOP2be_Real_e32e64_si <0x28>; 668defm V_SUBB_U32 : VOP2be_Real_e32e64_si <0x29>; 669defm V_SUBBREV_U32 : VOP2be_Real_e32e64_si <0x2a>; 670 671defm V_READLANE_B32 : VOP2_Real_si <0x01>; 672 673let InOperandList = (ins SSrc_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in) in { 674defm V_WRITELANE_B32 : VOP2_Real_si <0x02>; 675} 676 677defm V_MAC_LEGACY_F32 : VOP2_Real_e32e64_si <0x6>; 678defm V_MIN_LEGACY_F32 : VOP2_Real_e32e64_si <0xd>; 679defm V_MAX_LEGACY_F32 : VOP2_Real_e32e64_si <0xe>; 680defm V_LSHR_B32 : VOP2_Real_e32e64_si <0x15>; 681defm V_ASHR_I32 : VOP2_Real_e32e64_si <0x17>; 682defm V_LSHL_B32 : VOP2_Real_e32e64_si <0x19>; 683 684defm V_BFM_B32 : VOP2_Real_e32e64_si <0x1e>; 685defm V_BCNT_U32_B32 : VOP2_Real_e32e64_si <0x22>; 686defm V_MBCNT_LO_U32_B32 : VOP2_Real_e32e64_si <0x23>; 687defm V_MBCNT_HI_U32_B32 : VOP2_Real_e32e64_si <0x24>; 688defm V_LDEXP_F32 : VOP2_Real_e32e64_si <0x2b>; 689defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e32e64_si <0x2c>; 690defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e32e64_si <0x2d>; 691defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e32e64_si <0x2e>; 692defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_e32e64_si <0x2f>; 693defm V_CVT_PK_U16_U32 : VOP2_Real_e32e64_si <0x30>; 694defm V_CVT_PK_I16_I32 : VOP2_Real_e32e64_si <0x31>; 695 696 697//===----------------------------------------------------------------------===// 698// VI 699//===----------------------------------------------------------------------===// 700 701class VOP2_DPP <bits<6> op, VOP2_Pseudo ps, string OpName = ps.OpName, VOPProfile P = ps.Pfl> : 702 VOP_DPP <OpName, P> { 703 let Defs = ps.Defs; 704 let Uses = ps.Uses; 705 let SchedRW = ps.SchedRW; 706 let hasSideEffects = ps.hasSideEffects; 707 708 bits<8> vdst; 709 bits<8> src1; 710 let Inst{8-0} = 0xfa; //dpp 711 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 712 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 713 let Inst{30-25} = op; 714 let Inst{31} = 0x0; //encoding 715} 716 717let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in { 718 719multiclass VOP32_Real_vi <bits<10> op> { 720 def _vi : 721 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>, 722 VOP3e_vi<op, !cast<VOP2_Pseudo>(NAME).Pfl>; 723} 724 725multiclass VOP2_Real_MADK_vi <bits<6> op> { 726 def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>, 727 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 728} 729 730multiclass VOP2_Real_e32_vi <bits<6> op> { 731 def _e32_vi : 732 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>, 733 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>; 734} 735 736multiclass VOP2_Real_e64_vi <bits<10> op> { 737 def _e64_vi : 738 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 739 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 740} 741 742multiclass VOP2_Real_e64only_vi <bits<10> op> { 743 def _e64_vi : 744 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 745 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 746 // Hack to stop printing _e64 747 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME#"_e64"); 748 let OutOperandList = (outs VGPR_32:$vdst); 749 let AsmString = ps.Mnemonic # " " # ps.AsmOperands; 750 } 751} 752 753multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> : 754 VOP2_Real_e32_vi<op>, 755 VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>; 756 757} // End AssemblerPredicates = [isVI], DecoderNamespace = "VI" 758 759multiclass VOP2_SDWA_Real <bits<6> op> { 760 def _sdwa_vi : 761 VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 762 VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 763} 764 765multiclass VOP2_SDWA9_Real <bits<6> op> { 766 def _sdwa_gfx9 : 767 VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 768 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 769} 770 771let AssemblerPredicates = [isVIOnly] in { 772 773multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName> { 774 def _e32_vi : 775 VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.VI>, 776 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> { 777 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32"); 778 let AsmString = AsmName # ps.AsmOperands; 779 let DecoderNamespace = "VI"; 780 } 781 def _e64_vi : 782 VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.VI>, 783 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> { 784 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64"); 785 let AsmString = AsmName # ps.AsmOperands; 786 let DecoderNamespace = "VI"; 787 } 788 def _sdwa_vi : 789 VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>, 790 VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> { 791 VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa"); 792 let AsmString = AsmName # ps.AsmOperands; 793 } 794 def _dpp : 795 VOP2_DPP<op, !cast<VOP2_Pseudo>(OpName#"_e32"), AsmName>; 796} 797} 798 799let AssemblerPredicates = [isGFX9] in { 800 801multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> { 802 def _e32_gfx9 : 803 VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.GFX9>, 804 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> { 805 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32"); 806 let AsmString = AsmName # ps.AsmOperands; 807 let DecoderNamespace = "GFX9"; 808 } 809 def _e64_gfx9 : 810 VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>, 811 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> { 812 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64"); 813 let AsmString = AsmName # ps.AsmOperands; 814 let DecoderNamespace = "GFX9"; 815 } 816 def _sdwa_gfx9 : 817 VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>, 818 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> { 819 VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa"); 820 let AsmString = AsmName # ps.AsmOperands; 821 } 822 def _dpp_gfx9 : 823 VOP2_DPP<op, !cast<VOP2_Pseudo>(OpName#"_e32"), AsmName> { 824 let DecoderNamespace = "SDWA9"; 825 } 826} 827 828multiclass VOP2_Real_e32e64_gfx9 <bits<6> op> { 829 def _e32_gfx9 : 830 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX9>, 831 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>{ 832 let DecoderNamespace = "GFX9"; 833 } 834 def _e64_gfx9 : 835 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>, 836 VOP3e_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 837 let DecoderNamespace = "GFX9"; 838 } 839 def _sdwa_gfx9 : 840 VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 841 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> { 842 } 843 def _dpp_gfx9 : 844 VOP2_DPP<op, !cast<VOP2_Pseudo>(NAME#"_e32")> { 845 let DecoderNamespace = "SDWA9"; 846 } 847} 848 849} // AssemblerPredicates = [isGFX9] 850 851multiclass VOP2_Real_e32e64_vi <bits<6> op> : 852 Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> { 853 // For now left dpp only for asm/dasm 854 // TODO: add corresponding pseudo 855 def _dpp : VOP2_DPP<op, !cast<VOP2_Pseudo>(NAME#"_e32")>; 856} 857 858defm V_CNDMASK_B32 : VOP2_Real_e32e64_vi <0x0>; 859defm V_ADD_F32 : VOP2_Real_e32e64_vi <0x1>; 860defm V_SUB_F32 : VOP2_Real_e32e64_vi <0x2>; 861defm V_SUBREV_F32 : VOP2_Real_e32e64_vi <0x3>; 862defm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_vi <0x4>; 863defm V_MUL_F32 : VOP2_Real_e32e64_vi <0x5>; 864defm V_MUL_I32_I24 : VOP2_Real_e32e64_vi <0x6>; 865defm V_MUL_HI_I32_I24 : VOP2_Real_e32e64_vi <0x7>; 866defm V_MUL_U32_U24 : VOP2_Real_e32e64_vi <0x8>; 867defm V_MUL_HI_U32_U24 : VOP2_Real_e32e64_vi <0x9>; 868defm V_MIN_F32 : VOP2_Real_e32e64_vi <0xa>; 869defm V_MAX_F32 : VOP2_Real_e32e64_vi <0xb>; 870defm V_MIN_I32 : VOP2_Real_e32e64_vi <0xc>; 871defm V_MAX_I32 : VOP2_Real_e32e64_vi <0xd>; 872defm V_MIN_U32 : VOP2_Real_e32e64_vi <0xe>; 873defm V_MAX_U32 : VOP2_Real_e32e64_vi <0xf>; 874defm V_LSHRREV_B32 : VOP2_Real_e32e64_vi <0x10>; 875defm V_ASHRREV_I32 : VOP2_Real_e32e64_vi <0x11>; 876defm V_LSHLREV_B32 : VOP2_Real_e32e64_vi <0x12>; 877defm V_AND_B32 : VOP2_Real_e32e64_vi <0x13>; 878defm V_OR_B32 : VOP2_Real_e32e64_vi <0x14>; 879defm V_XOR_B32 : VOP2_Real_e32e64_vi <0x15>; 880defm V_MAC_F32 : VOP2_Real_e32e64_vi <0x16>; 881defm V_MADMK_F32 : VOP2_Real_MADK_vi <0x17>; 882defm V_MADAK_F32 : VOP2_Real_MADK_vi <0x18>; 883 884defm V_ADD_U32 : VOP2be_Real_e32e64_vi_only <0x19, "V_ADD_I32", "v_add_u32">; 885defm V_SUB_U32 : VOP2be_Real_e32e64_vi_only <0x1a, "V_SUB_I32", "v_sub_u32">; 886defm V_SUBREV_U32 : VOP2be_Real_e32e64_vi_only <0x1b, "V_SUBREV_I32", "v_subrev_u32">; 887defm V_ADDC_U32 : VOP2be_Real_e32e64_vi_only <0x1c, "V_ADDC_U32", "v_addc_u32">; 888defm V_SUBB_U32 : VOP2be_Real_e32e64_vi_only <0x1d, "V_SUBB_U32", "v_subb_u32">; 889defm V_SUBBREV_U32 : VOP2be_Real_e32e64_vi_only <0x1e, "V_SUBBREV_U32", "v_subbrev_u32">; 890 891defm V_ADD_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x19, "V_ADD_I32", "v_add_co_u32">; 892defm V_SUB_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1a, "V_SUB_I32", "v_sub_co_u32">; 893defm V_SUBREV_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1b, "V_SUBREV_I32", "v_subrev_co_u32">; 894defm V_ADDC_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1c, "V_ADDC_U32", "v_addc_co_u32">; 895defm V_SUBB_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1d, "V_SUBB_U32", "v_subb_co_u32">; 896defm V_SUBBREV_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1e, "V_SUBBREV_U32", "v_subbrev_co_u32">; 897 898defm V_ADD_U32 : VOP2_Real_e32e64_gfx9 <0x34>; 899defm V_SUB_U32 : VOP2_Real_e32e64_gfx9 <0x35>; 900defm V_SUBREV_U32 : VOP2_Real_e32e64_gfx9 <0x36>; 901 902defm V_READLANE_B32 : VOP32_Real_vi <0x289>; 903defm V_WRITELANE_B32 : VOP32_Real_vi <0x28a>; 904 905defm V_BFM_B32 : VOP2_Real_e64only_vi <0x293>; 906defm V_BCNT_U32_B32 : VOP2_Real_e64only_vi <0x28b>; 907defm V_MBCNT_LO_U32_B32 : VOP2_Real_e64only_vi <0x28c>; 908defm V_MBCNT_HI_U32_B32 : VOP2_Real_e64only_vi <0x28d>; 909defm V_LDEXP_F32 : VOP2_Real_e64only_vi <0x288>; 910defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e64only_vi <0x1f0>; 911defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e64only_vi <0x294>; 912defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e64only_vi <0x295>; 913defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_e64only_vi <0x296>; 914defm V_CVT_PK_U16_U32 : VOP2_Real_e64only_vi <0x297>; 915defm V_CVT_PK_I16_I32 : VOP2_Real_e64only_vi <0x298>; 916 917defm V_ADD_F16 : VOP2_Real_e32e64_vi <0x1f>; 918defm V_SUB_F16 : VOP2_Real_e32e64_vi <0x20>; 919defm V_SUBREV_F16 : VOP2_Real_e32e64_vi <0x21>; 920defm V_MUL_F16 : VOP2_Real_e32e64_vi <0x22>; 921defm V_MAC_F16 : VOP2_Real_e32e64_vi <0x23>; 922defm V_MADMK_F16 : VOP2_Real_MADK_vi <0x24>; 923defm V_MADAK_F16 : VOP2_Real_MADK_vi <0x25>; 924defm V_ADD_U16 : VOP2_Real_e32e64_vi <0x26>; 925defm V_SUB_U16 : VOP2_Real_e32e64_vi <0x27>; 926defm V_SUBREV_U16 : VOP2_Real_e32e64_vi <0x28>; 927defm V_MUL_LO_U16 : VOP2_Real_e32e64_vi <0x29>; 928defm V_LSHLREV_B16 : VOP2_Real_e32e64_vi <0x2a>; 929defm V_LSHRREV_B16 : VOP2_Real_e32e64_vi <0x2b>; 930defm V_ASHRREV_I16 : VOP2_Real_e32e64_vi <0x2c>; 931defm V_MAX_F16 : VOP2_Real_e32e64_vi <0x2d>; 932defm V_MIN_F16 : VOP2_Real_e32e64_vi <0x2e>; 933defm V_MAX_U16 : VOP2_Real_e32e64_vi <0x2f>; 934defm V_MAX_I16 : VOP2_Real_e32e64_vi <0x30>; 935defm V_MIN_U16 : VOP2_Real_e32e64_vi <0x31>; 936defm V_MIN_I16 : VOP2_Real_e32e64_vi <0x32>; 937defm V_LDEXP_F16 : VOP2_Real_e32e64_vi <0x33>; 938 939let SubtargetPredicate = isVI in { 940 941// Aliases to simplify matching of floating-point instructions that 942// are VOP2 on SI and VOP3 on VI. 943class SI2_VI3Alias <string name, VOP3_Real inst> : InstAlias < 944 name#" $dst, $src0, $src1", 945 !if(inst.Pfl.HasOMod, 946 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0), 947 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0)) 948>, PredicateControl { 949 let UseInstAsmMatchConverter = 0; 950 let AsmVariantName = AMDGPUAsmVariants.VOP3; 951} 952 953def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>; 954def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>; 955def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>; 956def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>; 957def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>; 958 959} // End SubtargetPredicate = isVI 960 961let SubtargetPredicate = HasDLInsts in { 962 963defm V_FMAC_F32 : VOP2_Real_e32e64_vi <0x3b>; 964defm V_XNOR_B32 : VOP2_Real_e32e64_vi <0x3d>; 965 966} // End SubtargetPredicate = HasDLInsts 967