1//===-- VOP3Instructions.td - Vector Instruction Defintions ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// VOP3 Classes
12//===----------------------------------------------------------------------===//
13
14class getVOP3ModPat<VOPProfile P, SDPatternOperator node> {
15  dag src0 = !if(P.HasOMod,
16    (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
17    (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp));
18
19  list<dag> ret3 = [(set P.DstVT:$vdst,
20    (node (P.Src0VT src0),
21          (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
22          (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))];
23
24  list<dag> ret2 = [(set P.DstVT:$vdst,
25    (node (P.Src0VT src0),
26          (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))];
27
28  list<dag> ret1 = [(set P.DstVT:$vdst,
29    (node (P.Src0VT src0)))];
30
31  list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
32                  !if(!eq(P.NumSrcArgs, 2), ret2,
33                  ret1));
34}
35
36class getVOP3PModPat<VOPProfile P, SDPatternOperator node> {
37  list<dag> ret3 = [(set P.DstVT:$vdst,
38    (node (P.Src0VT !if(P.HasClamp, (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
39                                    (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers))),
40          (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers)),
41          (P.Src2VT (VOP3PMods P.Src2VT:$src2, i32:$src2_modifiers))))];
42
43  list<dag> ret2 = [(set P.DstVT:$vdst,
44    (node !if(P.HasClamp, (P.Src0VT (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
45                          (P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers))),
46          (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers))))];
47
48  list<dag> ret1 = [(set P.DstVT:$vdst,
49    (node (P.Src0VT (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
50
51  list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
52                  !if(!eq(P.NumSrcArgs, 2), ret2,
53                  ret1));
54}
55
56class getVOP3OpSelPat<VOPProfile P, SDPatternOperator node> {
57  list<dag> ret3 = [(set P.DstVT:$vdst,
58    (node (P.Src0VT !if(P.HasClamp, (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
59                                    (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))),
60          (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers)),
61          (P.Src2VT (VOP3OpSel P.Src2VT:$src2, i32:$src2_modifiers))))];
62
63  list<dag> ret2 = [(set P.DstVT:$vdst,
64    (node !if(P.HasClamp, (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
65                          (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))),
66          (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers))))];
67
68  list<dag> ret1 = [(set P.DstVT:$vdst,
69    (node (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
70
71  list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
72                  !if(!eq(P.NumSrcArgs, 2), ret2,
73                  ret1));
74}
75
76class getVOP3OpSelModPat<VOPProfile P, SDPatternOperator node> {
77  list<dag> ret3 = [(set P.DstVT:$vdst,
78    (node (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
79                                    (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
80          (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers)),
81          (P.Src2VT (VOP3OpSelMods P.Src2VT:$src2, i32:$src2_modifiers))))];
82
83  list<dag> ret2 = [(set P.DstVT:$vdst,
84    (node !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
85                          (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
86          (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers))))];
87
88  list<dag> ret1 = [(set P.DstVT:$vdst,
89    (node (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
90
91  list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
92                  !if(!eq(P.NumSrcArgs, 2), ret2,
93                  ret1));
94}
95
96class getVOP3Pat<VOPProfile P, SDPatternOperator node> {
97  list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))];
98  list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))];
99  list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0))];
100  list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
101                  !if(!eq(P.NumSrcArgs, 2), ret2,
102                  ret1));
103}
104
105class getVOP3ClampPat<VOPProfile P, SDPatternOperator node> {
106  list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i1:$clamp))];
107  list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, i1:$clamp))];
108  list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, i1:$clamp))];
109  list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
110                  !if(!eq(P.NumSrcArgs, 2), ret2,
111                  ret1));
112}
113
114class VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit VOP3Only = 0> :
115  VOP3_Pseudo<OpName, P,
116    !if(P.HasOpSel,
117        !if(P.HasModifiers,
118            getVOP3OpSelModPat<P, node>.ret,
119            getVOP3OpSelPat<P, node>.ret),
120        !if(P.HasModifiers,
121            getVOP3ModPat<P, node>.ret,
122            !if(P.HasIntClamp,
123                getVOP3ClampPat<P, node>.ret,
124                getVOP3Pat<P, node>.ret))),
125    VOP3Only, 0, P.HasOpSel> {
126
127  let IntClamp = P.HasIntClamp;
128  let AsmMatchConverter =
129    !if(P.HasOpSel,
130        "cvtVOP3OpSel",
131        !if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)),
132            "cvtVOP3",
133            ""));
134}
135
136// Special case for v_div_fmas_{f32|f64}, since it seems to be the
137// only VOP instruction that implicitly reads VCC.
138let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in {
139def VOP_F32_F32_F32_F32_VCC : VOPProfile<[f32, f32, f32, f32]> {
140  let Outs64 = (outs DstRC.RegClass:$vdst);
141}
142def VOP_F64_F64_F64_F64_VCC : VOPProfile<[f64, f64, f64, f64]> {
143  let Outs64 = (outs DstRC.RegClass:$vdst);
144}
145}
146
147class getVOP3VCC<VOPProfile P, SDPatternOperator node> {
148  list<dag> ret =
149    [(set P.DstVT:$vdst,
150      (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
151            (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
152            (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
153            (i1 VCC)))];
154}
155
156class VOP3Features<bit Clamp, bit OpSel, bit Packed> {
157  bit HasClamp = Clamp;
158  bit HasOpSel = OpSel;
159  bit IsPacked = Packed;
160}
161
162def VOP3_REGULAR : VOP3Features<0, 0, 0>;
163def VOP3_CLAMP   : VOP3Features<1, 0, 0>;
164def VOP3_OPSEL   : VOP3Features<1, 1, 0>;
165def VOP3_PACKED  : VOP3Features<1, 1, 1>;
166
167class VOP3_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOPProfile<P.ArgVT> {
168
169  let HasClamp = !if(Features.HasClamp, 1, P.HasClamp);
170  let HasOpSel = !if(Features.HasOpSel, 1, P.HasOpSel);
171  let IsPacked = !if(Features.IsPacked, 1, P.IsPacked);
172
173  let HasModifiers = !if(Features.IsPacked, 1, P.HasModifiers);
174
175  // FIXME: Hack to stop printing _e64
176  let Outs64 = (outs DstRC.RegClass:$vdst);
177  let Asm64 =
178    " " # !if(Features.HasOpSel,
179              getAsmVOP3OpSel<NumSrcArgs,
180                              HasIntClamp,
181                              HasSrc0FloatMods,
182                              HasSrc1FloatMods,
183                              HasSrc2FloatMods>.ret,
184              !if(Features.HasClamp,
185                  getAsm64<HasDst, NumSrcArgs, HasIntClamp,
186                           HasModifiers, HasOMod, DstVT>.ret,
187                  P.Asm64));
188}
189
190class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> {
191  // v_div_scale_{f32|f64} do not support input modifiers.
192  let HasModifiers = 0;
193  let HasOMod = 0;
194  let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
195  let Asm64 = " $vdst, $sdst, $src0, $src1, $src2";
196}
197
198def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32> {
199  // FIXME: Hack to stop printing _e64
200  let DstRC = RegisterOperand<VGPR_32>;
201}
202
203def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> {
204  // FIXME: Hack to stop printing _e64
205  let DstRC = RegisterOperand<VReg_64>;
206}
207
208def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> {
209  let HasClamp = 1;
210
211  // FIXME: Hack to stop printing _e64
212  let DstRC = RegisterOperand<VReg_64>;
213
214  let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
215  let Asm64 = " $vdst, $sdst, $src0, $src1, $src2$clamp";
216}
217
218//===----------------------------------------------------------------------===//
219// VOP3 INTERP
220//===----------------------------------------------------------------------===//
221
222class VOP3Interp<string OpName, VOPProfile P> : VOP3_Pseudo<OpName, P> {
223  let AsmMatchConverter = "cvtVOP3Interp";
224}
225
226def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> {
227  let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
228                   Attr:$attr, AttrChan:$attrchan,
229                   clampmod:$clamp, omod:$omod);
230
231  let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod";
232}
233
234def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> {
235  let Ins64 = (ins InterpSlot:$src0,
236                   Attr:$attr, AttrChan:$attrchan,
237                   clampmod:$clamp, omod:$omod);
238
239  let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod";
240
241  let HasClamp = 1;
242}
243
244class getInterp16Asm <bit HasSrc2, bit HasOMod> {
245  string src2 = !if(HasSrc2, ", $src2_modifiers", "");
246  string omod = !if(HasOMod, "$omod", "");
247  string ret =
248    " $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod;
249}
250
251class getInterp16Ins <bit HasSrc2, bit HasOMod,
252                      Operand Src0Mod, Operand Src2Mod> {
253  dag ret = !if(HasSrc2,
254                !if(HasOMod,
255                    (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
256                         Attr:$attr, AttrChan:$attrchan,
257                         Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
258                         highmod:$high, clampmod:$clamp, omod:$omod),
259                    (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
260                         Attr:$attr, AttrChan:$attrchan,
261                         Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
262                         highmod:$high, clampmod:$clamp)
263                ),
264                (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
265                     Attr:$attr, AttrChan:$attrchan,
266                     highmod:$high, clampmod:$clamp, omod:$omod)
267            );
268}
269
270class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
271
272  let HasOMod = !if(!eq(DstVT.Value, f16.Value), 0, 1);
273  let HasHigh = 1;
274
275  let Outs64 = (outs VGPR_32:$vdst);
276  let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret;
277  let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret;
278}
279
280//===----------------------------------------------------------------------===//
281// VOP3 Instructions
282//===----------------------------------------------------------------------===//
283
284let isCommutable = 1 in {
285
286def V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
287def V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fmad>;
288def V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
289def V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
290def V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fma>;
291def V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_lerp>;
292
293let SchedRW = [WriteDoubleAdd] in {
294def V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, fma>;
295def V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, fadd, 1>;
296def V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, fmul, 1>;
297def V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum, 1>;
298def V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaxnum, 1>;
299} // End SchedRW = [WriteDoubleAdd]
300
301let SchedRW = [WriteQuarterRate32] in {
302def V_MUL_LO_U32 : VOP3Inst <"v_mul_lo_u32", VOP3_Profile<VOP_I32_I32_I32>>;
303def V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", VOP3_Profile<VOP_I32_I32_I32>, mulhu>;
304def V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", VOP3_Profile<VOP_I32_I32_I32>>;
305def V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", VOP3_Profile<VOP_I32_I32_I32>, mulhs>;
306} // End SchedRW = [WriteQuarterRate32]
307
308let Uses = [VCC, EXEC] in {
309// v_div_fmas_f32:
310//   result = src0 * src1 + src2
311//   if (vcc)
312//     result *= 2^32
313//
314def V_DIV_FMAS_F32 : VOP3_Pseudo <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC,
315  getVOP3VCC<VOP_F32_F32_F32_F32_VCC, AMDGPUdiv_fmas>.ret> {
316  let SchedRW = [WriteFloatFMA];
317}
318// v_div_fmas_f64:
319//   result = src0 * src1 + src2
320//   if (vcc)
321//     result *= 2^64
322//
323def V_DIV_FMAS_F64 : VOP3_Pseudo <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC,
324  getVOP3VCC<VOP_F64_F64_F64_F64_VCC, AMDGPUdiv_fmas>.ret> {
325  let SchedRW = [WriteDouble];
326}
327} // End Uses = [VCC, EXEC]
328
329} // End isCommutable = 1
330
331def V_CUBEID_F32 : VOP3Inst <"v_cubeid_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubeid>;
332def V_CUBESC_F32 : VOP3Inst <"v_cubesc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubesc>;
333def V_CUBETC_F32 : VOP3Inst <"v_cubetc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubetc>;
334def V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubema>;
335def V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>;
336def V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>;
337def V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>;
338def V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbit>;
339def V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>;
340def V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmin3>;
341def V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmin3>;
342def V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumin3>;
343def V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmax3>;
344def V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmax3>;
345def V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumax3>;
346def V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>;
347def V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmed3>;
348def V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumed3>;
349def V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
350def V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
351def V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
352def V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
353def V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_I32>, int_amdgcn_cvt_pk_u8_f32>;
354def V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUdiv_fixup>;
355
356let SchedRW = [WriteDoubleAdd] in {
357def V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>;
358def V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUldexp, 1>;
359} // End SchedRW = [WriteDoubleAdd]
360
361def V_DIV_SCALE_F32 : VOP3_Pseudo <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> {
362  let SchedRW = [WriteFloatFMA, WriteSALU];
363  let AsmMatchConverter = "";
364}
365
366// Double precision division pre-scale.
367def V_DIV_SCALE_F64 : VOP3_Pseudo <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1> {
368  let SchedRW = [WriteDouble, WriteSALU];
369  let AsmMatchConverter = "";
370}
371
372def V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
373
374let Constraints = "@earlyclobber $vdst" in {
375def V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>;
376} // End Constraints = "@earlyclobber $vdst"
377
378def V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUtrig_preop> {
379  let SchedRW = [WriteDouble];
380}
381
382let SchedRW = [Write64Bit] in {
383// These instructions only exist on SI and CI
384let SubtargetPredicate = isSICI in {
385def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>>;
386def V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>>;
387def V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>>;
388def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
389} // End SubtargetPredicate = isSICI
390
391let SubtargetPredicate = isVI in {
392def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
393def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
394def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>>;
395} // End SubtargetPredicate = isVI
396} // End SchedRW = [Write64Bit]
397
398let SubtargetPredicate = isCIVI in {
399
400let Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] in {
401def V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>;
402def V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_V4I32, VOP3_CLAMP>>;
403} // End Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32]
404
405let isCommutable = 1 in {
406let SchedRW = [WriteQuarterRate32, WriteSALU] in {
407def V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>;
408def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>;
409} // End SchedRW = [WriteDouble, WriteSALU]
410} // End isCommutable = 1
411
412} // End SubtargetPredicate = isCIVI
413
414
415def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup> {
416  let Predicates = [Has16BitInsts, isVIOnly];
417}
418def V_DIV_FIXUP_F16_gfx9 : VOP3Inst <"v_div_fixup_f16_gfx9",
419                                      VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUdiv_fixup> {
420  let renamedInGFX9 = 1;
421  let Predicates = [Has16BitInsts, isGFX9];
422}
423
424let SubtargetPredicate = Has16BitInsts, isCommutable = 1 in {
425
426let renamedInGFX9 = 1 in {
427def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
428def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;
429def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;
430def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>;
431def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>>;
432}
433
434let SubtargetPredicate = isGFX9 in {
435def V_MAD_F16_gfx9   : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>;
436def V_MAD_U16_gfx9   : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
437def V_MAD_I16_gfx9   : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
438def V_FMA_F16_gfx9   : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>;
439def V_INTERP_P2_F16_gfx9 : VOP3Interp <"v_interp_p2_f16_gfx9", VOP3_INTERP16<[f16, f32, i32, f32]>>;
440} // End SubtargetPredicate = isGFX9
441
442def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>>;
443def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>;
444
445} // End SubtargetPredicate = Has16BitInsts, isCommutable = 1
446
447let SubtargetPredicate = isVI in {
448def V_INTERP_P1_F32_e64  : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>;
449def V_INTERP_P2_F32_e64  : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>;
450def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>;
451
452def V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUperm>;
453} // End SubtargetPredicate = isVI
454
455let Predicates = [Has16BitInsts] in {
456
457multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2,
458                             Instruction inst, SDPatternOperator op3> {
459def : GCNPat <
460  (op2 (op1 i16:$src0, i16:$src1), i16:$src2),
461  (inst i16:$src0, i16:$src1, i16:$src2, (i1 0))
462>;
463
464}
465
466defm: Ternary_i16_Pats<mul, add, V_MAD_U16, zext>;
467defm: Ternary_i16_Pats<mul, add, V_MAD_I16, sext>;
468
469} // End Predicates = [Has16BitInsts]
470
471let SubtargetPredicate = isGFX9 in {
472def V_PACK_B32_F16 : VOP3Inst <"v_pack_b32_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
473def V_LSHL_ADD_U32 : VOP3Inst <"v_lshl_add_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
474def V_ADD_LSHL_U32 : VOP3Inst <"v_add_lshl_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
475def V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
476def V_LSHL_OR_B32 : VOP3Inst <"v_lshl_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
477def V_AND_OR_B32 : VOP3Inst <"v_and_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
478def V_OR3_B32 : VOP3Inst <"v_or3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
479
480def V_XAD_U32 : VOP3Inst <"v_xad_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
481
482def V_MED3_F16 : VOP3Inst <"v_med3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmed3>;
483def V_MED3_I16 : VOP3Inst <"v_med3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmed3>;
484def V_MED3_U16 : VOP3Inst <"v_med3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumed3>;
485
486def V_MIN3_F16 : VOP3Inst <"v_min3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmin3>;
487def V_MIN3_I16 : VOP3Inst <"v_min3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmin3>;
488def V_MIN3_U16 : VOP3Inst <"v_min3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumin3>;
489
490def V_MAX3_F16 : VOP3Inst <"v_max3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmax3>;
491def V_MAX3_I16 : VOP3Inst <"v_max3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmax3>;
492def V_MAX3_U16 : VOP3Inst <"v_max3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumax3>;
493
494def V_ADD_I16 : VOP3Inst <"v_add_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>;
495def V_SUB_I16 : VOP3Inst <"v_sub_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>;
496
497def V_MAD_U32_U16 : VOP3Inst <"v_mad_u32_u16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>;
498def V_MAD_I32_I16 : VOP3Inst <"v_mad_i32_i16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>;
499
500def V_CVT_PKNORM_I16_F16 : VOP3Inst <"v_cvt_pknorm_i16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
501def V_CVT_PKNORM_U16_F16 : VOP3Inst <"v_cvt_pknorm_u16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
502
503def V_ADD_I32_gfx9 : VOP3Inst <"v_add_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32>>;
504def V_SUB_I32_gfx9 : VOP3Inst <"v_sub_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32>>;
505} // End SubtargetPredicate = isGFX9
506
507//===----------------------------------------------------------------------===//
508// Integer Clamp Patterns
509//===----------------------------------------------------------------------===//
510
511class getClampPat<VOPProfile P, SDPatternOperator node> {
512  dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2));
513  dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1));
514  dag ret1 = (P.DstVT (node P.Src0VT:$src0));
515  dag ret = !if(!eq(P.NumSrcArgs, 3), ret3,
516            !if(!eq(P.NumSrcArgs, 2), ret2,
517            ret1));
518}
519
520class getClampRes<VOPProfile P, Instruction inst> {
521  dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0));
522  dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0));
523  dag ret1 = (inst P.Src0VT:$src0, (i1 0));
524  dag ret = !if(!eq(P.NumSrcArgs, 3), ret3,
525            !if(!eq(P.NumSrcArgs, 2), ret2,
526            ret1));
527}
528
529class IntClampPat<VOP3Inst inst, SDPatternOperator node> : GCNPat<
530  getClampPat<inst.Pfl, node>.ret,
531  getClampRes<inst.Pfl, inst>.ret
532>;
533
534def : IntClampPat<V_MAD_I32_I24, AMDGPUmad_i24>;
535def : IntClampPat<V_MAD_U32_U24, AMDGPUmad_u24>;
536
537def : IntClampPat<V_SAD_U8, int_amdgcn_sad_u8>;
538def : IntClampPat<V_SAD_HI_U8, int_amdgcn_sad_hi_u8>;
539def : IntClampPat<V_SAD_U16, int_amdgcn_sad_u16>;
540
541def : IntClampPat<V_MSAD_U8, int_amdgcn_msad_u8>;
542def : IntClampPat<V_MQSAD_PK_U16_U8, int_amdgcn_mqsad_pk_u16_u8>;
543
544def : IntClampPat<V_QSAD_PK_U16_U8, int_amdgcn_qsad_pk_u16_u8>;
545def : IntClampPat<V_MQSAD_U32_U8, int_amdgcn_mqsad_u32_u8>;
546
547//===----------------------------------------------------------------------===//
548// Target
549//===----------------------------------------------------------------------===//
550
551//===----------------------------------------------------------------------===//
552// SI
553//===----------------------------------------------------------------------===//
554
555let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in {
556
557multiclass VOP3_Real_si<bits<9> op> {
558  def _si : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
559            VOP3e_si <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
560}
561
562multiclass VOP3be_Real_si<bits<9> op> {
563  def _si : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
564            VOP3be_si <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
565}
566
567} // End AssemblerPredicates = [isSICI], DecoderNamespace = "SICI"
568
569defm V_MAD_LEGACY_F32   : VOP3_Real_si <0x140>;
570defm V_MAD_F32          : VOP3_Real_si <0x141>;
571defm V_MAD_I32_I24      : VOP3_Real_si <0x142>;
572defm V_MAD_U32_U24      : VOP3_Real_si <0x143>;
573defm V_CUBEID_F32       : VOP3_Real_si <0x144>;
574defm V_CUBESC_F32       : VOP3_Real_si <0x145>;
575defm V_CUBETC_F32       : VOP3_Real_si <0x146>;
576defm V_CUBEMA_F32       : VOP3_Real_si <0x147>;
577defm V_BFE_U32          : VOP3_Real_si <0x148>;
578defm V_BFE_I32          : VOP3_Real_si <0x149>;
579defm V_BFI_B32          : VOP3_Real_si <0x14a>;
580defm V_FMA_F32          : VOP3_Real_si <0x14b>;
581defm V_FMA_F64          : VOP3_Real_si <0x14c>;
582defm V_LERP_U8          : VOP3_Real_si <0x14d>;
583defm V_ALIGNBIT_B32     : VOP3_Real_si <0x14e>;
584defm V_ALIGNBYTE_B32    : VOP3_Real_si <0x14f>;
585defm V_MULLIT_F32       : VOP3_Real_si <0x150>;
586defm V_MIN3_F32         : VOP3_Real_si <0x151>;
587defm V_MIN3_I32         : VOP3_Real_si <0x152>;
588defm V_MIN3_U32         : VOP3_Real_si <0x153>;
589defm V_MAX3_F32         : VOP3_Real_si <0x154>;
590defm V_MAX3_I32         : VOP3_Real_si <0x155>;
591defm V_MAX3_U32         : VOP3_Real_si <0x156>;
592defm V_MED3_F32         : VOP3_Real_si <0x157>;
593defm V_MED3_I32         : VOP3_Real_si <0x158>;
594defm V_MED3_U32         : VOP3_Real_si <0x159>;
595defm V_SAD_U8           : VOP3_Real_si <0x15a>;
596defm V_SAD_HI_U8        : VOP3_Real_si <0x15b>;
597defm V_SAD_U16          : VOP3_Real_si <0x15c>;
598defm V_SAD_U32          : VOP3_Real_si <0x15d>;
599defm V_CVT_PK_U8_F32    : VOP3_Real_si <0x15e>;
600defm V_DIV_FIXUP_F32    : VOP3_Real_si <0x15f>;
601defm V_DIV_FIXUP_F64    : VOP3_Real_si <0x160>;
602defm V_LSHL_B64         : VOP3_Real_si <0x161>;
603defm V_LSHR_B64         : VOP3_Real_si <0x162>;
604defm V_ASHR_I64         : VOP3_Real_si <0x163>;
605defm V_ADD_F64          : VOP3_Real_si <0x164>;
606defm V_MUL_F64          : VOP3_Real_si <0x165>;
607defm V_MIN_F64          : VOP3_Real_si <0x166>;
608defm V_MAX_F64          : VOP3_Real_si <0x167>;
609defm V_LDEXP_F64        : VOP3_Real_si <0x168>;
610defm V_MUL_LO_U32       : VOP3_Real_si <0x169>;
611defm V_MUL_HI_U32       : VOP3_Real_si <0x16a>;
612defm V_MUL_LO_I32       : VOP3_Real_si <0x16b>;
613defm V_MUL_HI_I32       : VOP3_Real_si <0x16c>;
614defm V_DIV_SCALE_F32    : VOP3be_Real_si <0x16d>;
615defm V_DIV_SCALE_F64    : VOP3be_Real_si <0x16e>;
616defm V_DIV_FMAS_F32     : VOP3_Real_si <0x16f>;
617defm V_DIV_FMAS_F64     : VOP3_Real_si <0x170>;
618defm V_MSAD_U8          : VOP3_Real_si <0x171>;
619defm V_MQSAD_PK_U16_U8  : VOP3_Real_si <0x173>;
620defm V_TRIG_PREOP_F64   : VOP3_Real_si <0x174>;
621
622//===----------------------------------------------------------------------===//
623// CI
624//===----------------------------------------------------------------------===//
625
626multiclass VOP3_Real_ci<bits<9> op> {
627  def _ci : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
628            VOP3e_si <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
629    let AssemblerPredicates = [isCIOnly];
630    let DecoderNamespace = "CI";
631  }
632}
633
634multiclass VOP3be_Real_ci<bits<9> op> {
635  def _ci : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
636            VOP3be_si <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
637    let AssemblerPredicates = [isCIOnly];
638    let DecoderNamespace = "CI";
639  }
640}
641
642defm V_QSAD_PK_U16_U8   : VOP3_Real_ci <0x172>;
643defm V_MQSAD_U32_U8     : VOP3_Real_ci <0x175>;
644defm V_MAD_U64_U32      : VOP3be_Real_ci <0x176>;
645defm V_MAD_I64_I32      : VOP3be_Real_ci <0x177>;
646
647//===----------------------------------------------------------------------===//
648// VI
649//===----------------------------------------------------------------------===//
650
651let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
652
653multiclass VOP3_Real_vi<bits<10> op> {
654  def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
655            VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
656}
657
658multiclass VOP3be_Real_vi<bits<10> op> {
659  def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
660            VOP3be_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
661}
662
663multiclass VOP3OpSel_Real_gfx9<bits<10> op> {
664  def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
665            VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
666}
667
668multiclass VOP3Interp_Real_vi<bits<10> op> {
669  def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
670            VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
671}
672
673} // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
674
675let AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI" in {
676
677multiclass VOP3_F16_Real_vi<bits<10> op> {
678  def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
679            VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
680}
681
682multiclass VOP3Interp_F16_Real_vi<bits<10> op> {
683  def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
684            VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
685}
686
687} // End AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI"
688
689let AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9" in {
690
691multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
692  def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
693            VOP3e_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> {
694              VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName);
695              let AsmString = AsmName # ps.AsmOperands;
696            }
697}
698
699multiclass VOP3OpSel_F16_Real_gfx9<bits<10> op, string AsmName> {
700  def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX9>,
701            VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
702              VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME);
703              let AsmString = AsmName # ps.AsmOperands;
704            }
705}
706
707multiclass VOP3Interp_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
708  def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
709            VOP3Interp_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> {
710              VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName);
711              let AsmString = AsmName # ps.AsmOperands;
712            }
713}
714
715multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> {
716  def _gfx9 : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX9>,
717              VOP3e_vi <op, !cast<VOP_Pseudo>(NAME).Pfl> {
718              VOP_Pseudo ps = !cast<VOP_Pseudo>(NAME);
719              let AsmString = AsmName # ps.AsmOperands;
720            }
721}
722
723} // End AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9"
724
725defm V_MAD_U64_U32      : VOP3be_Real_vi <0x1E8>;
726defm V_MAD_I64_I32      : VOP3be_Real_vi <0x1E9>;
727
728defm V_MAD_LEGACY_F32   : VOP3_Real_vi <0x1c0>;
729defm V_MAD_F32          : VOP3_Real_vi <0x1c1>;
730defm V_MAD_I32_I24      : VOP3_Real_vi <0x1c2>;
731defm V_MAD_U32_U24      : VOP3_Real_vi <0x1c3>;
732defm V_CUBEID_F32       : VOP3_Real_vi <0x1c4>;
733defm V_CUBESC_F32       : VOP3_Real_vi <0x1c5>;
734defm V_CUBETC_F32       : VOP3_Real_vi <0x1c6>;
735defm V_CUBEMA_F32       : VOP3_Real_vi <0x1c7>;
736defm V_BFE_U32          : VOP3_Real_vi <0x1c8>;
737defm V_BFE_I32          : VOP3_Real_vi <0x1c9>;
738defm V_BFI_B32          : VOP3_Real_vi <0x1ca>;
739defm V_FMA_F32          : VOP3_Real_vi <0x1cb>;
740defm V_FMA_F64          : VOP3_Real_vi <0x1cc>;
741defm V_LERP_U8          : VOP3_Real_vi <0x1cd>;
742defm V_ALIGNBIT_B32     : VOP3_Real_vi <0x1ce>;
743defm V_ALIGNBYTE_B32    : VOP3_Real_vi <0x1cf>;
744defm V_MIN3_F32         : VOP3_Real_vi <0x1d0>;
745defm V_MIN3_I32         : VOP3_Real_vi <0x1d1>;
746defm V_MIN3_U32         : VOP3_Real_vi <0x1d2>;
747defm V_MAX3_F32         : VOP3_Real_vi <0x1d3>;
748defm V_MAX3_I32         : VOP3_Real_vi <0x1d4>;
749defm V_MAX3_U32         : VOP3_Real_vi <0x1d5>;
750defm V_MED3_F32         : VOP3_Real_vi <0x1d6>;
751defm V_MED3_I32         : VOP3_Real_vi <0x1d7>;
752defm V_MED3_U32         : VOP3_Real_vi <0x1d8>;
753defm V_SAD_U8           : VOP3_Real_vi <0x1d9>;
754defm V_SAD_HI_U8        : VOP3_Real_vi <0x1da>;
755defm V_SAD_U16          : VOP3_Real_vi <0x1db>;
756defm V_SAD_U32          : VOP3_Real_vi <0x1dc>;
757defm V_CVT_PK_U8_F32    : VOP3_Real_vi <0x1dd>;
758defm V_DIV_FIXUP_F32    : VOP3_Real_vi <0x1de>;
759defm V_DIV_FIXUP_F64    : VOP3_Real_vi <0x1df>;
760defm V_DIV_SCALE_F32    : VOP3be_Real_vi <0x1e0>;
761defm V_DIV_SCALE_F64    : VOP3be_Real_vi <0x1e1>;
762defm V_DIV_FMAS_F32     : VOP3_Real_vi <0x1e2>;
763defm V_DIV_FMAS_F64     : VOP3_Real_vi <0x1e3>;
764defm V_MSAD_U8          : VOP3_Real_vi <0x1e4>;
765defm V_QSAD_PK_U16_U8   : VOP3_Real_vi <0x1e5>;
766defm V_MQSAD_PK_U16_U8  : VOP3_Real_vi <0x1e6>;
767defm V_MQSAD_U32_U8     : VOP3_Real_vi <0x1e7>;
768
769defm V_PERM_B32         : VOP3_Real_vi <0x1ed>;
770
771defm V_MAD_F16          : VOP3_F16_Real_vi <0x1ea>;
772defm V_MAD_U16          : VOP3_F16_Real_vi <0x1eb>;
773defm V_MAD_I16          : VOP3_F16_Real_vi <0x1ec>;
774defm V_FMA_F16          : VOP3_F16_Real_vi <0x1ee>;
775defm V_DIV_FIXUP_F16    : VOP3_F16_Real_vi <0x1ef>;
776defm V_INTERP_P2_F16    : VOP3Interp_F16_Real_vi <0x276>;
777
778defm V_MAD_LEGACY_F16       : VOP3_F16_Real_gfx9 <0x1ea, "V_MAD_F16",       "v_mad_legacy_f16">;
779defm V_MAD_LEGACY_U16       : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16",       "v_mad_legacy_u16">;
780defm V_MAD_LEGACY_I16       : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16",       "v_mad_legacy_i16">;
781defm V_FMA_LEGACY_F16       : VOP3_F16_Real_gfx9 <0x1ee, "V_FMA_F16",       "v_fma_legacy_f16">;
782defm V_DIV_FIXUP_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ef, "V_DIV_FIXUP_F16", "v_div_fixup_legacy_f16">;
783defm V_INTERP_P2_LEGACY_F16 : VOP3Interp_F16_Real_gfx9 <0x276, "V_INTERP_P2_F16", "v_interp_p2_legacy_f16">;
784
785defm V_MAD_F16_gfx9         : VOP3OpSel_F16_Real_gfx9 <0x203, "v_mad_f16">;
786defm V_MAD_U16_gfx9         : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">;
787defm V_MAD_I16_gfx9         : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">;
788defm V_FMA_F16_gfx9         : VOP3OpSel_F16_Real_gfx9 <0x206, "v_fma_f16">;
789defm V_DIV_FIXUP_F16_gfx9   : VOP3OpSel_F16_Real_gfx9 <0x207, "v_div_fixup_f16">;
790defm V_INTERP_P2_F16_gfx9   : VOP3Interp_F16_Real_gfx9 <0x277, "V_INTERP_P2_F16_gfx9", "v_interp_p2_f16">;
791
792defm V_ADD_I32_gfx9         : VOP3_Real_gfx9 <0x29c, "v_add_i32">;
793defm V_SUB_I32_gfx9         : VOP3_Real_gfx9 <0x29d, "v_sub_i32">;
794
795defm V_INTERP_P1_F32_e64  : VOP3Interp_Real_vi <0x270>;
796defm V_INTERP_P2_F32_e64  : VOP3Interp_Real_vi <0x271>;
797defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>;
798
799defm V_INTERP_P1LL_F16  : VOP3Interp_Real_vi <0x274>;
800defm V_INTERP_P1LV_F16  : VOP3Interp_Real_vi <0x275>;
801defm V_ADD_F64          : VOP3_Real_vi <0x280>;
802defm V_MUL_F64          : VOP3_Real_vi <0x281>;
803defm V_MIN_F64          : VOP3_Real_vi <0x282>;
804defm V_MAX_F64          : VOP3_Real_vi <0x283>;
805defm V_LDEXP_F64        : VOP3_Real_vi <0x284>;
806defm V_MUL_LO_U32       : VOP3_Real_vi <0x285>;
807
808// removed from VI as identical to V_MUL_LO_U32
809let isAsmParserOnly = 1 in {
810defm V_MUL_LO_I32       : VOP3_Real_vi <0x285>;
811}
812
813defm V_MUL_HI_U32       : VOP3_Real_vi <0x286>;
814defm V_MUL_HI_I32       : VOP3_Real_vi <0x287>;
815
816defm V_LSHLREV_B64      : VOP3_Real_vi <0x28f>;
817defm V_LSHRREV_B64      : VOP3_Real_vi <0x290>;
818defm V_ASHRREV_I64      : VOP3_Real_vi <0x291>;
819defm V_TRIG_PREOP_F64   : VOP3_Real_vi <0x292>;
820
821defm V_LSHL_ADD_U32 : VOP3_Real_vi <0x1fd>;
822defm V_ADD_LSHL_U32 : VOP3_Real_vi <0x1fe>;
823defm V_ADD3_U32 : VOP3_Real_vi <0x1ff>;
824defm V_LSHL_OR_B32 : VOP3_Real_vi <0x200>;
825defm V_AND_OR_B32 : VOP3_Real_vi <0x201>;
826defm V_OR3_B32 : VOP3_Real_vi <0x202>;
827defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx9 <0x2a0>;
828
829defm V_XAD_U32 : VOP3_Real_vi <0x1f3>;
830
831defm V_MIN3_F16 : VOP3OpSel_Real_gfx9 <0x1f4>;
832defm V_MIN3_I16 : VOP3OpSel_Real_gfx9 <0x1f5>;
833defm V_MIN3_U16 : VOP3OpSel_Real_gfx9 <0x1f6>;
834
835defm V_MAX3_F16 : VOP3OpSel_Real_gfx9 <0x1f7>;
836defm V_MAX3_I16 : VOP3OpSel_Real_gfx9 <0x1f8>;
837defm V_MAX3_U16 : VOP3OpSel_Real_gfx9 <0x1f9>;
838
839defm V_MED3_F16 : VOP3OpSel_Real_gfx9 <0x1fa>;
840defm V_MED3_I16 : VOP3OpSel_Real_gfx9 <0x1fb>;
841defm V_MED3_U16 : VOP3OpSel_Real_gfx9 <0x1fc>;
842
843defm V_ADD_I16  : VOP3OpSel_Real_gfx9 <0x29e>;
844defm V_SUB_I16  : VOP3OpSel_Real_gfx9 <0x29f>;
845
846defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx9 <0x1f1>;
847defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx9 <0x1f2>;
848
849defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx9 <0x299>;
850defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx9 <0x29a>;
851