1 //===-- ARMFixupKinds.h - ARM Specific Fixup Entries ------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMFIXUPKINDS_H 11 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMFIXUPKINDS_H 12 13 #include "llvm/MC/MCFixup.h" 14 15 namespace llvm { 16 namespace ARM { 17 enum Fixups { 18 // 12-bit PC relative relocation for symbol addresses 19 fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind, 20 21 // Equivalent to fixup_arm_ldst_pcrel_12, with the 16-bit halfwords reordered. 22 fixup_t2_ldst_pcrel_12, 23 24 // 10-bit PC relative relocation for symbol addresses used in 25 // LDRD/LDRH/LDRB/etc. instructions. All bits are encoded. 26 fixup_arm_pcrel_10_unscaled, 27 // 10-bit PC relative relocation for symbol addresses used in VFP instructions 28 // where the lower 2 bits are not encoded (so it's encoded as an 8-bit 29 // immediate). 30 fixup_arm_pcrel_10, 31 // Equivalent to fixup_arm_pcrel_10, accounting for the short-swapped encoding 32 // of Thumb2 instructions. 33 fixup_t2_pcrel_10, 34 // 9-bit PC relative relocation for symbol addresses used in VFP instructions 35 // where bit 0 not encoded (so it's encoded as an 8-bit immediate). 36 fixup_arm_pcrel_9, 37 // Equivalent to fixup_arm_pcrel_9, accounting for the short-swapped encoding 38 // of Thumb2 instructions. 39 fixup_t2_pcrel_9, 40 // 10-bit PC relative relocation for symbol addresses where the lower 2 bits 41 // are not encoded (so it's encoded as an 8-bit immediate). 42 fixup_thumb_adr_pcrel_10, 43 // 12-bit PC relative relocation for the ADR instruction. 44 fixup_arm_adr_pcrel_12, 45 // 12-bit PC relative relocation for the ADR instruction. 46 fixup_t2_adr_pcrel_12, 47 // 24-bit PC relative relocation for conditional branch instructions. 48 fixup_arm_condbranch, 49 // 24-bit PC relative relocation for branch instructions. (unconditional) 50 fixup_arm_uncondbranch, 51 // 20-bit PC relative relocation for Thumb2 direct uconditional branch 52 // instructions. 53 fixup_t2_condbranch, 54 // 20-bit PC relative relocation for Thumb2 direct branch unconditional branch 55 // instructions. 56 fixup_t2_uncondbranch, 57 58 // 12-bit fixup for Thumb B instructions. 59 fixup_arm_thumb_br, 60 61 // The following fixups handle the ARM BL instructions. These can be 62 // conditionalised; however, the ARM ELF ABI requires a different relocation 63 // in that case: R_ARM_JUMP24 instead of R_ARM_CALL. The difference is that 64 // R_ARM_CALL is allowed to change the instruction to a BLX inline, which has 65 // no conditional version; R_ARM_JUMP24 would have to insert a veneer. 66 // 67 // MachO does not draw a distinction between the two cases, so it will treat 68 // fixup_arm_uncondbl and fixup_arm_condbl as identical fixups. 69 70 // Fixup for unconditional ARM BL instructions. 71 fixup_arm_uncondbl, 72 73 // Fixup for ARM BL instructions with nontrivial conditionalisation. 74 fixup_arm_condbl, 75 76 // Fixup for ARM BLX instructions. 77 fixup_arm_blx, 78 79 // Fixup for Thumb BL instructions. 80 fixup_arm_thumb_bl, 81 82 // Fixup for Thumb BLX instructions. 83 fixup_arm_thumb_blx, 84 85 // Fixup for Thumb branch instructions. 86 fixup_arm_thumb_cb, 87 88 // Fixup for Thumb load/store from constant pool instrs. 89 fixup_arm_thumb_cp, 90 91 // Fixup for Thumb conditional branching instructions. 92 fixup_arm_thumb_bcc, 93 94 // The next two are for the movt/movw pair 95 // the 16bit imm field are split into imm{15-12} and imm{11-0} 96 fixup_arm_movt_hi16, // :upper16: 97 fixup_arm_movw_lo16, // :lower16: 98 fixup_t2_movt_hi16, // :upper16: 99 fixup_t2_movw_lo16, // :lower16: 100 101 // Fixup for mod_imm 102 fixup_arm_mod_imm, 103 104 // Fixup for Thumb2 8-bit rotated operand 105 fixup_t2_so_imm, 106 107 // Marker 108 LastTargetFixupKind, 109 NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind 110 }; 111 } 112 } // namespace llvm 113 114 #endif 115