1 //===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides ARM specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H 15 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H 16 17 #include "llvm/Support/DataTypes.h" 18 #include <memory> 19 #include <string> 20 21 namespace llvm { 22 class formatted_raw_ostream; 23 class MCAsmBackend; 24 class MCCodeEmitter; 25 class MCContext; 26 class MCInstrInfo; 27 class MCInstPrinter; 28 class MCObjectTargetWriter; 29 class MCObjectWriter; 30 class MCRegisterInfo; 31 class MCSubtargetInfo; 32 class MCStreamer; 33 class MCTargetOptions; 34 class MCRelocationInfo; 35 class MCTargetStreamer; 36 class StringRef; 37 class Target; 38 class Triple; 39 class raw_ostream; 40 class raw_pwrite_stream; 41 42 Target &getTheARMLETarget(); 43 Target &getTheThumbLETarget(); 44 Target &getTheARMBETarget(); 45 Target &getTheThumbBETarget(); 46 47 namespace ARM_MC { 48 std::string ParseARMTriple(const Triple &TT, StringRef CPU); 49 50 /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc. 51 /// do not need to go through TargetRegistry. 52 MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, 53 StringRef FS); 54 } 55 56 MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S); 57 MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S, 58 formatted_raw_ostream &OS, 59 MCInstPrinter *InstPrint, 60 bool isVerboseAsm); 61 MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S, 62 const MCSubtargetInfo &STI); 63 64 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII, 65 const MCRegisterInfo &MRI, 66 MCContext &Ctx); 67 68 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII, 69 const MCRegisterInfo &MRI, 70 MCContext &Ctx); 71 72 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, 73 const MCRegisterInfo &MRI, 74 const MCTargetOptions &Options); 75 76 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, 77 const MCRegisterInfo &MRI, 78 const MCTargetOptions &Options); 79 80 // Construct a PE/COFF machine code streamer which will generate a PE/COFF 81 // object file. 82 MCStreamer *createARMWinCOFFStreamer(MCContext &Context, 83 std::unique_ptr<MCAsmBackend> &&MAB, 84 std::unique_ptr<MCObjectWriter> &&OW, 85 std::unique_ptr<MCCodeEmitter> &&Emitter, 86 bool RelaxAll, 87 bool IncrementalLinkerCompatible); 88 89 /// Construct an ELF Mach-O object writer. 90 std::unique_ptr<MCObjectTargetWriter> createARMELFObjectWriter(uint8_t OSABI); 91 92 /// Construct an ARM Mach-O object writer. 93 std::unique_ptr<MCObjectTargetWriter> 94 createARMMachObjectWriter(bool Is64Bit, uint32_t CPUType, 95 uint32_t CPUSubtype); 96 97 /// Construct an ARM PE/COFF object writer. 98 std::unique_ptr<MCObjectTargetWriter> 99 createARMWinCOFFObjectWriter(bool Is64Bit); 100 101 /// Construct ARM Mach-O relocation info. 102 MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx); 103 } // End llvm namespace 104 105 // Defines symbolic names for ARM registers. This defines a mapping from 106 // register name to register number. 107 // 108 #define GET_REGINFO_ENUM 109 #include "ARMGenRegisterInfo.inc" 110 111 // Defines symbolic names for the ARM instructions. 112 // 113 #define GET_INSTRINFO_ENUM 114 #include "ARMGenInstrInfo.inc" 115 116 #define GET_SUBTARGETINFO_ENUM 117 #include "ARMGenSubtargetInfo.inc" 118 119 #endif 120