1//===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// This is populated based on the following specs: 10// Hexagon V2 Architecture 11// Application-Level Specification 12// 80-V9418-8 Rev. B 13// March 4, 2008 14//===----------------------------------------------------------------------===// 15 16class T_I_pat <InstHexagon MI, Intrinsic IntID> 17 : Pat <(IntID imm:$Is), 18 (MI imm:$Is)>; 19 20class T_R_pat <InstHexagon MI, Intrinsic IntID> 21 : Pat <(IntID I32:$Rs), 22 (MI I32:$Rs)>; 23 24class T_P_pat <InstHexagon MI, Intrinsic IntID> 25 : Pat <(IntID I64:$Rs), 26 (MI I64:$Rs)>; 27 28class T_II_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2> 29 : Pat<(IntID Imm1:$Is, Imm2:$It), 30 (MI Imm1:$Is, Imm2:$It)>; 31 32class T_RI_pat <InstHexagon MI, Intrinsic IntID, 33 PatLeaf ImmPred = PatLeaf<(i32 imm)>> 34 : Pat<(IntID I32:$Rs, ImmPred:$It), 35 (MI I32:$Rs, ImmPred:$It)>; 36 37class T_IR_pat <InstHexagon MI, Intrinsic IntID, 38 PatFrag ImmPred = PatLeaf<(i32 imm)>> 39 : Pat<(IntID ImmPred:$Is, I32:$Rt), 40 (MI ImmPred:$Is, I32:$Rt)>; 41 42class T_PI_pat <InstHexagon MI, Intrinsic IntID> 43 : Pat<(IntID I64:$Rs, imm:$It), 44 (MI I64:$Rs, imm:$It)>; 45 46class T_RP_pat <InstHexagon MI, Intrinsic IntID> 47 : Pat<(IntID I32:$Rs, I64:$Rt), 48 (MI I32:$Rs, I64:$Rt)>; 49 50class T_RR_pat <InstHexagon MI, Intrinsic IntID> 51 : Pat <(IntID I32:$Rs, I32:$Rt), 52 (MI I32:$Rs, I32:$Rt)>; 53 54class T_PP_pat <InstHexagon MI, Intrinsic IntID> 55 : Pat <(IntID I64:$Rs, I64:$Rt), 56 (MI I64:$Rs, I64:$Rt)>; 57 58class T_QQ_pat <InstHexagon MI, Intrinsic IntID> 59 : Pat <(IntID I32:$Rs, I32:$Rt), 60 (MI (C2_tfrrp I32:$Rs), (C2_tfrrp I32:$Rt))>; 61 62class T_QII_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2> 63 : Pat <(IntID I32:$Rp, Imm1:$Is, Imm2:$It), 64 (MI (C2_tfrrp I32:$Rp), Imm1:$Is, Imm2:$It)>; 65 66class T_QRR_pat <InstHexagon MI, Intrinsic IntID> 67 : Pat <(IntID I32:$Rp, I32:$Rs, I32:$Rt), 68 (MI (C2_tfrrp I32:$Rp), I32:$Rs, I32:$Rt)>; 69 70class T_QRI_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred> 71 : Pat <(IntID I32:$Rp, I32:$Rs, ImmPred:$Is), 72 (MI (C2_tfrrp I32:$Rp), I32:$Rs, ImmPred:$Is)>; 73 74class T_QIR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred> 75 : Pat <(IntID I32:$Rp, ImmPred:$Is, I32:$Rs), 76 (MI (C2_tfrrp I32:$Rp), ImmPred:$Is, I32:$Rs)>; 77 78class T_QPP_pat <InstHexagon MI, Intrinsic IntID> 79 : Pat <(IntID I32:$Rp, I64:$Rs, I64:$Rt), 80 (MI (C2_tfrrp I32:$Rp), I64:$Rs, I64:$Rt)>; 81 82class T_RRI_pat <InstHexagon MI, Intrinsic IntID> 83 : Pat <(IntID I32:$Rs, I32:$Rt, imm:$Iu), 84 (MI I32:$Rs, I32:$Rt, imm:$Iu)>; 85 86class T_RII_pat <InstHexagon MI, Intrinsic IntID> 87 : Pat <(IntID I32:$Rs, imm:$It, imm:$Iu), 88 (MI I32:$Rs, imm:$It, imm:$Iu)>; 89 90class T_IRI_pat <InstHexagon MI, Intrinsic IntID> 91 : Pat <(IntID imm:$It, I32:$Rs, imm:$Iu), 92 (MI imm:$It, I32:$Rs, imm:$Iu)>; 93 94class T_IRR_pat <InstHexagon MI, Intrinsic IntID> 95 : Pat <(IntID imm:$Is, I32:$Rs, I32:$Rt), 96 (MI imm:$Is, I32:$Rs, I32:$Rt)>; 97 98class T_RIR_pat <InstHexagon MI, Intrinsic IntID> 99 : Pat <(IntID I32:$Rs, imm:$Is, I32:$Rt), 100 (MI I32:$Rs, imm:$Is, I32:$Rt)>; 101 102class T_RRR_pat <InstHexagon MI, Intrinsic IntID> 103 : Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru), 104 (MI I32:$Rs, I32:$Rt, I32:$Ru)>; 105 106class T_PPI_pat <InstHexagon MI, Intrinsic IntID> 107 : Pat <(IntID I64:$Rs, I64:$Rt, imm:$Iu), 108 (MI I64:$Rs, I64:$Rt, imm:$Iu)>; 109 110class T_PII_pat <InstHexagon MI, Intrinsic IntID> 111 : Pat <(IntID I64:$Rs, imm:$It, imm:$Iu), 112 (MI I64:$Rs, imm:$It, imm:$Iu)>; 113 114class T_PPP_pat <InstHexagon MI, Intrinsic IntID> 115 : Pat <(IntID I64:$Rs, I64:$Rt, I64:$Ru), 116 (MI I64:$Rs, I64:$Rt, I64:$Ru)>; 117 118class T_PPR_pat <InstHexagon MI, Intrinsic IntID> 119 : Pat <(IntID I64:$Rs, I64:$Rt, I32:$Ru), 120 (MI I64:$Rs, I64:$Rt, I32:$Ru)>; 121 122class T_PRR_pat <InstHexagon MI, Intrinsic IntID> 123 : Pat <(IntID I64:$Rs, I32:$Rt, I32:$Ru), 124 (MI I64:$Rs, I32:$Rt, I32:$Ru)>; 125 126class T_PPQ_pat <InstHexagon MI, Intrinsic IntID> 127 : Pat <(IntID I64:$Rs, I64:$Rt, I32:$Rp), 128 (MI I64:$Rs, I64:$Rt, (C2_tfrrp I32:$Rp))>; 129 130class T_PR_pat <InstHexagon MI, Intrinsic IntID> 131 : Pat <(IntID I64:$Rs, I32:$Rt), 132 (MI I64:$Rs, I32:$Rt)>; 133 134class T_D_pat <InstHexagon MI, Intrinsic IntID> 135 : Pat<(IntID (F64:$Rs)), 136 (MI (F64:$Rs))>; 137 138class T_DI_pat <InstHexagon MI, Intrinsic IntID, 139 PatLeaf ImmPred = PatLeaf<(i32 imm)>> 140 : Pat<(IntID F64:$Rs, ImmPred:$It), 141 (MI F64:$Rs, ImmPred:$It)>; 142 143class T_F_pat <InstHexagon MI, Intrinsic IntID> 144 : Pat<(IntID F32:$Rs), 145 (MI F32:$Rs)>; 146 147class T_FI_pat <InstHexagon MI, Intrinsic IntID, 148 PatLeaf ImmPred = PatLeaf<(i32 imm)>> 149 : Pat<(IntID F32:$Rs, ImmPred:$It), 150 (MI F32:$Rs, ImmPred:$It)>; 151 152class T_FF_pat <InstHexagon MI, Intrinsic IntID> 153 : Pat<(IntID F32:$Rs, F32:$Rt), 154 (MI F32:$Rs, F32:$Rt)>; 155 156class T_DD_pat <InstHexagon MI, Intrinsic IntID> 157 : Pat<(IntID F64:$Rs, F64:$Rt), 158 (MI F64:$Rs, F64:$Rt)>; 159 160class T_FFF_pat <InstHexagon MI, Intrinsic IntID> 161 : Pat<(IntID F32:$Rs, F32:$Rt, F32:$Ru), 162 (MI F32:$Rs, F32:$Rt, F32:$Ru)>; 163 164class T_FFFQ_pat <InstHexagon MI, Intrinsic IntID> 165 : Pat <(IntID F32:$Rs, F32:$Rt, F32:$Ru, I32:$Rp), 166 (MI F32:$Rs, F32:$Rt, F32:$Ru, (C2_tfrrp I32:$Rp))>; 167 168class T_Q_RI_pat <InstHexagon MI, Intrinsic IntID, 169 PatLeaf ImmPred = PatLeaf<(i32 imm)>> 170 : Pat<(IntID I32:$Rs, ImmPred:$It), 171 (C2_tfrpr (MI I32:$Rs, ImmPred:$It))>; 172 173class T_Q_RR_pat <InstHexagon MI, Intrinsic IntID> 174 : Pat <(IntID I32:$Rs, I32:$Rt), 175 (C2_tfrpr (MI I32:$Rs, I32:$Rt))>; 176 177class T_Q_RP_pat <InstHexagon MI, Intrinsic IntID> 178 : Pat <(IntID I32:$Rs, I64:$Rt), 179 (C2_tfrpr (MI I32:$Rs, I64:$Rt))>; 180 181class T_Q_PR_pat <InstHexagon MI, Intrinsic IntID> 182 : Pat <(IntID I64:$Rs, I32:$Rt), 183 (C2_tfrpr (MI I64:$Rs, I32:$Rt))>; 184 185class T_Q_PI_pat <InstHexagon MI, Intrinsic IntID> 186 : Pat<(IntID I64:$Rs, imm:$It), 187 (C2_tfrpr (MI I64:$Rs, imm:$It))>; 188 189class T_Q_PP_pat <InstHexagon MI, Intrinsic IntID> 190 : Pat <(IntID I64:$Rs, I64:$Rt), 191 (C2_tfrpr (MI I64:$Rs, I64:$Rt))>; 192 193class T_Q_Q_pat <InstHexagon MI, Intrinsic IntID> 194 : Pat <(IntID I32:$Rp), 195 (C2_tfrpr (MI (C2_tfrrp I32:$Rp)))>; 196 197class T_Q_QQ_pat <InstHexagon MI, Intrinsic IntID> 198 : Pat <(IntID I32:$Rp, I32:$Rq), 199 (C2_tfrpr (MI (C2_tfrrp I32:$Rp), (C2_tfrrp I32:$Rq)))>; 200 201class T_Q_FF_pat <InstHexagon MI, Intrinsic IntID> 202 : Pat<(IntID F32:$Rs, F32:$Rt), 203 (C2_tfrpr (MI F32:$Rs, F32:$Rt))>; 204 205class T_Q_DD_pat <InstHexagon MI, Intrinsic IntID> 206 : Pat<(IntID F64:$Rs, F64:$Rt), 207 (C2_tfrpr (MI F64:$Rs, F64:$Rt))>; 208 209class T_Q_FI_pat <InstHexagon MI, Intrinsic IntID> 210 : Pat<(IntID F32:$Rs, imm:$It), 211 (C2_tfrpr (MI F32:$Rs, imm:$It))>; 212 213class T_Q_DI_pat <InstHexagon MI, Intrinsic IntID> 214 : Pat<(IntID F64:$Rs, imm:$It), 215 (C2_tfrpr (MI F64:$Rs, imm:$It))>; 216 217class T_Q_QQQ_pat <InstHexagon MI, Intrinsic IntID> 218 : Pat <(IntID I32:$Rp, I32:$Rq, I32:$Rs), 219 (C2_tfrpr (MI (C2_tfrrp I32:$Rp), (C2_tfrrp I32:$Rq), 220 (C2_tfrrp I32:$Rs)))>; 221 222//===----------------------------------------------------------------------===// 223// MPYS / Multipy signed/unsigned halfwords 224//Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat] 225//===----------------------------------------------------------------------===// 226 227def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>; 228def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>; 229def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>; 230def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>; 231def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>; 232def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>; 233def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>; 234def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>; 235 236def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>; 237def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>; 238def : T_RR_pat <M2_mpyu_lh_s1, int_hexagon_M2_mpyu_lh_s1>; 239def : T_RR_pat <M2_mpyu_lh_s0, int_hexagon_M2_mpyu_lh_s0>; 240def : T_RR_pat <M2_mpyu_hl_s1, int_hexagon_M2_mpyu_hl_s1>; 241def : T_RR_pat <M2_mpyu_hl_s0, int_hexagon_M2_mpyu_hl_s0>; 242def : T_RR_pat <M2_mpyu_hh_s1, int_hexagon_M2_mpyu_hh_s1>; 243def : T_RR_pat <M2_mpyu_hh_s0, int_hexagon_M2_mpyu_hh_s0>; 244 245def : T_RR_pat <M2_mpy_sat_ll_s1, int_hexagon_M2_mpy_sat_ll_s1>; 246def : T_RR_pat <M2_mpy_sat_ll_s0, int_hexagon_M2_mpy_sat_ll_s0>; 247def : T_RR_pat <M2_mpy_sat_lh_s1, int_hexagon_M2_mpy_sat_lh_s1>; 248def : T_RR_pat <M2_mpy_sat_lh_s0, int_hexagon_M2_mpy_sat_lh_s0>; 249def : T_RR_pat <M2_mpy_sat_hl_s1, int_hexagon_M2_mpy_sat_hl_s1>; 250def : T_RR_pat <M2_mpy_sat_hl_s0, int_hexagon_M2_mpy_sat_hl_s0>; 251def : T_RR_pat <M2_mpy_sat_hh_s1, int_hexagon_M2_mpy_sat_hh_s1>; 252def : T_RR_pat <M2_mpy_sat_hh_s0, int_hexagon_M2_mpy_sat_hh_s0>; 253 254def : T_RR_pat <M2_mpy_rnd_ll_s1, int_hexagon_M2_mpy_rnd_ll_s1>; 255def : T_RR_pat <M2_mpy_rnd_ll_s0, int_hexagon_M2_mpy_rnd_ll_s0>; 256def : T_RR_pat <M2_mpy_rnd_lh_s1, int_hexagon_M2_mpy_rnd_lh_s1>; 257def : T_RR_pat <M2_mpy_rnd_lh_s0, int_hexagon_M2_mpy_rnd_lh_s0>; 258def : T_RR_pat <M2_mpy_rnd_hl_s1, int_hexagon_M2_mpy_rnd_hl_s1>; 259def : T_RR_pat <M2_mpy_rnd_hl_s0, int_hexagon_M2_mpy_rnd_hl_s0>; 260def : T_RR_pat <M2_mpy_rnd_hh_s1, int_hexagon_M2_mpy_rnd_hh_s1>; 261def : T_RR_pat <M2_mpy_rnd_hh_s0, int_hexagon_M2_mpy_rnd_hh_s0>; 262 263def : T_RR_pat <M2_mpy_sat_rnd_ll_s1, int_hexagon_M2_mpy_sat_rnd_ll_s1>; 264def : T_RR_pat <M2_mpy_sat_rnd_ll_s0, int_hexagon_M2_mpy_sat_rnd_ll_s0>; 265def : T_RR_pat <M2_mpy_sat_rnd_lh_s1, int_hexagon_M2_mpy_sat_rnd_lh_s1>; 266def : T_RR_pat <M2_mpy_sat_rnd_lh_s0, int_hexagon_M2_mpy_sat_rnd_lh_s0>; 267def : T_RR_pat <M2_mpy_sat_rnd_hl_s1, int_hexagon_M2_mpy_sat_rnd_hl_s1>; 268def : T_RR_pat <M2_mpy_sat_rnd_hl_s0, int_hexagon_M2_mpy_sat_rnd_hl_s0>; 269def : T_RR_pat <M2_mpy_sat_rnd_hh_s1, int_hexagon_M2_mpy_sat_rnd_hh_s1>; 270def : T_RR_pat <M2_mpy_sat_rnd_hh_s0, int_hexagon_M2_mpy_sat_rnd_hh_s0>; 271 272 273//===----------------------------------------------------------------------===// 274// MPYS / Multipy signed/unsigned halfwords and add/subtract the 275// result from the accumulator. 276//Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat] 277//===----------------------------------------------------------------------===// 278 279def : T_RRR_pat <M2_mpy_acc_ll_s1, int_hexagon_M2_mpy_acc_ll_s1>; 280def : T_RRR_pat <M2_mpy_acc_ll_s0, int_hexagon_M2_mpy_acc_ll_s0>; 281def : T_RRR_pat <M2_mpy_acc_lh_s1, int_hexagon_M2_mpy_acc_lh_s1>; 282def : T_RRR_pat <M2_mpy_acc_lh_s0, int_hexagon_M2_mpy_acc_lh_s0>; 283def : T_RRR_pat <M2_mpy_acc_hl_s1, int_hexagon_M2_mpy_acc_hl_s1>; 284def : T_RRR_pat <M2_mpy_acc_hl_s0, int_hexagon_M2_mpy_acc_hl_s0>; 285def : T_RRR_pat <M2_mpy_acc_hh_s1, int_hexagon_M2_mpy_acc_hh_s1>; 286def : T_RRR_pat <M2_mpy_acc_hh_s0, int_hexagon_M2_mpy_acc_hh_s0>; 287 288def : T_RRR_pat <M2_mpyu_acc_ll_s1, int_hexagon_M2_mpyu_acc_ll_s1>; 289def : T_RRR_pat <M2_mpyu_acc_ll_s0, int_hexagon_M2_mpyu_acc_ll_s0>; 290def : T_RRR_pat <M2_mpyu_acc_lh_s1, int_hexagon_M2_mpyu_acc_lh_s1>; 291def : T_RRR_pat <M2_mpyu_acc_lh_s0, int_hexagon_M2_mpyu_acc_lh_s0>; 292def : T_RRR_pat <M2_mpyu_acc_hl_s1, int_hexagon_M2_mpyu_acc_hl_s1>; 293def : T_RRR_pat <M2_mpyu_acc_hl_s0, int_hexagon_M2_mpyu_acc_hl_s0>; 294def : T_RRR_pat <M2_mpyu_acc_hh_s1, int_hexagon_M2_mpyu_acc_hh_s1>; 295def : T_RRR_pat <M2_mpyu_acc_hh_s0, int_hexagon_M2_mpyu_acc_hh_s0>; 296 297def : T_RRR_pat <M2_mpy_nac_ll_s1, int_hexagon_M2_mpy_nac_ll_s1>; 298def : T_RRR_pat <M2_mpy_nac_ll_s0, int_hexagon_M2_mpy_nac_ll_s0>; 299def : T_RRR_pat <M2_mpy_nac_lh_s1, int_hexagon_M2_mpy_nac_lh_s1>; 300def : T_RRR_pat <M2_mpy_nac_lh_s0, int_hexagon_M2_mpy_nac_lh_s0>; 301def : T_RRR_pat <M2_mpy_nac_hl_s1, int_hexagon_M2_mpy_nac_hl_s1>; 302def : T_RRR_pat <M2_mpy_nac_hl_s0, int_hexagon_M2_mpy_nac_hl_s0>; 303def : T_RRR_pat <M2_mpy_nac_hh_s1, int_hexagon_M2_mpy_nac_hh_s1>; 304def : T_RRR_pat <M2_mpy_nac_hh_s0, int_hexagon_M2_mpy_nac_hh_s0>; 305 306def : T_RRR_pat <M2_mpyu_nac_ll_s1, int_hexagon_M2_mpyu_nac_ll_s1>; 307def : T_RRR_pat <M2_mpyu_nac_ll_s0, int_hexagon_M2_mpyu_nac_ll_s0>; 308def : T_RRR_pat <M2_mpyu_nac_lh_s1, int_hexagon_M2_mpyu_nac_lh_s1>; 309def : T_RRR_pat <M2_mpyu_nac_lh_s0, int_hexagon_M2_mpyu_nac_lh_s0>; 310def : T_RRR_pat <M2_mpyu_nac_hl_s1, int_hexagon_M2_mpyu_nac_hl_s1>; 311def : T_RRR_pat <M2_mpyu_nac_hl_s0, int_hexagon_M2_mpyu_nac_hl_s0>; 312def : T_RRR_pat <M2_mpyu_nac_hh_s1, int_hexagon_M2_mpyu_nac_hh_s1>; 313def : T_RRR_pat <M2_mpyu_nac_hh_s0, int_hexagon_M2_mpyu_nac_hh_s0>; 314 315def : T_RRR_pat <M2_mpy_acc_sat_ll_s1, int_hexagon_M2_mpy_acc_sat_ll_s1>; 316def : T_RRR_pat <M2_mpy_acc_sat_ll_s0, int_hexagon_M2_mpy_acc_sat_ll_s0>; 317def : T_RRR_pat <M2_mpy_acc_sat_lh_s1, int_hexagon_M2_mpy_acc_sat_lh_s1>; 318def : T_RRR_pat <M2_mpy_acc_sat_lh_s0, int_hexagon_M2_mpy_acc_sat_lh_s0>; 319def : T_RRR_pat <M2_mpy_acc_sat_hl_s1, int_hexagon_M2_mpy_acc_sat_hl_s1>; 320def : T_RRR_pat <M2_mpy_acc_sat_hl_s0, int_hexagon_M2_mpy_acc_sat_hl_s0>; 321def : T_RRR_pat <M2_mpy_acc_sat_hh_s1, int_hexagon_M2_mpy_acc_sat_hh_s1>; 322def : T_RRR_pat <M2_mpy_acc_sat_hh_s0, int_hexagon_M2_mpy_acc_sat_hh_s0>; 323 324def : T_RRR_pat <M2_mpy_nac_sat_ll_s1, int_hexagon_M2_mpy_nac_sat_ll_s1>; 325def : T_RRR_pat <M2_mpy_nac_sat_ll_s0, int_hexagon_M2_mpy_nac_sat_ll_s0>; 326def : T_RRR_pat <M2_mpy_nac_sat_lh_s1, int_hexagon_M2_mpy_nac_sat_lh_s1>; 327def : T_RRR_pat <M2_mpy_nac_sat_lh_s0, int_hexagon_M2_mpy_nac_sat_lh_s0>; 328def : T_RRR_pat <M2_mpy_nac_sat_hl_s1, int_hexagon_M2_mpy_nac_sat_hl_s1>; 329def : T_RRR_pat <M2_mpy_nac_sat_hl_s0, int_hexagon_M2_mpy_nac_sat_hl_s0>; 330def : T_RRR_pat <M2_mpy_nac_sat_hh_s1, int_hexagon_M2_mpy_nac_sat_hh_s1>; 331def : T_RRR_pat <M2_mpy_nac_sat_hh_s0, int_hexagon_M2_mpy_nac_sat_hh_s0>; 332 333 334//===----------------------------------------------------------------------===// 335// Multiply signed/unsigned halfwords with and without saturation and rounding 336// into a 64-bits destination register. 337//===----------------------------------------------------------------------===// 338 339def : T_RR_pat <M2_mpyd_hh_s0, int_hexagon_M2_mpyd_hh_s0>; 340def : T_RR_pat <M2_mpyd_hl_s0, int_hexagon_M2_mpyd_hl_s0>; 341def : T_RR_pat <M2_mpyd_lh_s0, int_hexagon_M2_mpyd_lh_s0>; 342def : T_RR_pat <M2_mpyd_ll_s0, int_hexagon_M2_mpyd_ll_s0>; 343def : T_RR_pat <M2_mpyd_hh_s1, int_hexagon_M2_mpyd_hh_s1>; 344def : T_RR_pat <M2_mpyd_hl_s1, int_hexagon_M2_mpyd_hl_s1>; 345def : T_RR_pat <M2_mpyd_lh_s1, int_hexagon_M2_mpyd_lh_s1>; 346def : T_RR_pat <M2_mpyd_ll_s1, int_hexagon_M2_mpyd_ll_s1>; 347 348def : T_RR_pat <M2_mpyd_rnd_hh_s0, int_hexagon_M2_mpyd_rnd_hh_s0>; 349def : T_RR_pat <M2_mpyd_rnd_hl_s0, int_hexagon_M2_mpyd_rnd_hl_s0>; 350def : T_RR_pat <M2_mpyd_rnd_lh_s0, int_hexagon_M2_mpyd_rnd_lh_s0>; 351def : T_RR_pat <M2_mpyd_rnd_ll_s0, int_hexagon_M2_mpyd_rnd_ll_s0>; 352def : T_RR_pat <M2_mpyd_rnd_hh_s1, int_hexagon_M2_mpyd_rnd_hh_s1>; 353def : T_RR_pat <M2_mpyd_rnd_hl_s1, int_hexagon_M2_mpyd_rnd_hl_s1>; 354def : T_RR_pat <M2_mpyd_rnd_lh_s1, int_hexagon_M2_mpyd_rnd_lh_s1>; 355def : T_RR_pat <M2_mpyd_rnd_ll_s1, int_hexagon_M2_mpyd_rnd_ll_s1>; 356 357def : T_RR_pat <M2_mpyud_hh_s0, int_hexagon_M2_mpyud_hh_s0>; 358def : T_RR_pat <M2_mpyud_hl_s0, int_hexagon_M2_mpyud_hl_s0>; 359def : T_RR_pat <M2_mpyud_lh_s0, int_hexagon_M2_mpyud_lh_s0>; 360def : T_RR_pat <M2_mpyud_ll_s0, int_hexagon_M2_mpyud_ll_s0>; 361def : T_RR_pat <M2_mpyud_hh_s1, int_hexagon_M2_mpyud_hh_s1>; 362def : T_RR_pat <M2_mpyud_hl_s1, int_hexagon_M2_mpyud_hl_s1>; 363def : T_RR_pat <M2_mpyud_lh_s1, int_hexagon_M2_mpyud_lh_s1>; 364def : T_RR_pat <M2_mpyud_ll_s1, int_hexagon_M2_mpyud_ll_s1>; 365 366//===----------------------------------------------------------------------===// 367// MPYS / Multipy signed/unsigned halfwords and add/subtract the 368// result from the 64-bit destination register. 369//Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat] 370//===----------------------------------------------------------------------===// 371 372def : T_PRR_pat <M2_mpyd_acc_hh_s0, int_hexagon_M2_mpyd_acc_hh_s0>; 373def : T_PRR_pat <M2_mpyd_acc_hl_s0, int_hexagon_M2_mpyd_acc_hl_s0>; 374def : T_PRR_pat <M2_mpyd_acc_lh_s0, int_hexagon_M2_mpyd_acc_lh_s0>; 375def : T_PRR_pat <M2_mpyd_acc_ll_s0, int_hexagon_M2_mpyd_acc_ll_s0>; 376 377def : T_PRR_pat <M2_mpyd_acc_hh_s1, int_hexagon_M2_mpyd_acc_hh_s1>; 378def : T_PRR_pat <M2_mpyd_acc_hl_s1, int_hexagon_M2_mpyd_acc_hl_s1>; 379def : T_PRR_pat <M2_mpyd_acc_lh_s1, int_hexagon_M2_mpyd_acc_lh_s1>; 380def : T_PRR_pat <M2_mpyd_acc_ll_s1, int_hexagon_M2_mpyd_acc_ll_s1>; 381 382def : T_PRR_pat <M2_mpyd_nac_hh_s0, int_hexagon_M2_mpyd_nac_hh_s0>; 383def : T_PRR_pat <M2_mpyd_nac_hl_s0, int_hexagon_M2_mpyd_nac_hl_s0>; 384def : T_PRR_pat <M2_mpyd_nac_lh_s0, int_hexagon_M2_mpyd_nac_lh_s0>; 385def : T_PRR_pat <M2_mpyd_nac_ll_s0, int_hexagon_M2_mpyd_nac_ll_s0>; 386 387def : T_PRR_pat <M2_mpyd_nac_hh_s1, int_hexagon_M2_mpyd_nac_hh_s1>; 388def : T_PRR_pat <M2_mpyd_nac_hl_s1, int_hexagon_M2_mpyd_nac_hl_s1>; 389def : T_PRR_pat <M2_mpyd_nac_lh_s1, int_hexagon_M2_mpyd_nac_lh_s1>; 390def : T_PRR_pat <M2_mpyd_nac_ll_s1, int_hexagon_M2_mpyd_nac_ll_s1>; 391 392def : T_PRR_pat <M2_mpyud_acc_hh_s0, int_hexagon_M2_mpyud_acc_hh_s0>; 393def : T_PRR_pat <M2_mpyud_acc_hl_s0, int_hexagon_M2_mpyud_acc_hl_s0>; 394def : T_PRR_pat <M2_mpyud_acc_lh_s0, int_hexagon_M2_mpyud_acc_lh_s0>; 395def : T_PRR_pat <M2_mpyud_acc_ll_s0, int_hexagon_M2_mpyud_acc_ll_s0>; 396 397def : T_PRR_pat <M2_mpyud_acc_hh_s1, int_hexagon_M2_mpyud_acc_hh_s1>; 398def : T_PRR_pat <M2_mpyud_acc_hl_s1, int_hexagon_M2_mpyud_acc_hl_s1>; 399def : T_PRR_pat <M2_mpyud_acc_lh_s1, int_hexagon_M2_mpyud_acc_lh_s1>; 400def : T_PRR_pat <M2_mpyud_acc_ll_s1, int_hexagon_M2_mpyud_acc_ll_s1>; 401 402def : T_PRR_pat <M2_mpyud_nac_hh_s0, int_hexagon_M2_mpyud_nac_hh_s0>; 403def : T_PRR_pat <M2_mpyud_nac_hl_s0, int_hexagon_M2_mpyud_nac_hl_s0>; 404def : T_PRR_pat <M2_mpyud_nac_lh_s0, int_hexagon_M2_mpyud_nac_lh_s0>; 405def : T_PRR_pat <M2_mpyud_nac_ll_s0, int_hexagon_M2_mpyud_nac_ll_s0>; 406 407def : T_PRR_pat <M2_mpyud_nac_hh_s1, int_hexagon_M2_mpyud_nac_hh_s1>; 408def : T_PRR_pat <M2_mpyud_nac_hl_s1, int_hexagon_M2_mpyud_nac_hl_s1>; 409def : T_PRR_pat <M2_mpyud_nac_lh_s1, int_hexagon_M2_mpyud_nac_lh_s1>; 410def : T_PRR_pat <M2_mpyud_nac_ll_s1, int_hexagon_M2_mpyud_nac_ll_s1>; 411 412// Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat 413def : T_PP_pat <M2_vcmpy_s1_sat_i, int_hexagon_M2_vcmpy_s1_sat_i>; 414def : T_PP_pat <M2_vcmpy_s0_sat_i, int_hexagon_M2_vcmpy_s0_sat_i>; 415 416// Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat 417def : T_PP_pat <M2_vcmpy_s1_sat_r, int_hexagon_M2_vcmpy_s1_sat_r>; 418def : T_PP_pat <M2_vcmpy_s0_sat_r, int_hexagon_M2_vcmpy_s0_sat_r>; 419 420// Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat 421def : T_PP_pat <M2_vdmpys_s1, int_hexagon_M2_vdmpys_s1>; 422def : T_PP_pat <M2_vdmpys_s0, int_hexagon_M2_vdmpys_s0>; 423 424// Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat 425def : T_PP_pat <M2_vmpy2es_s1, int_hexagon_M2_vmpy2es_s1>; 426def : T_PP_pat <M2_vmpy2es_s0, int_hexagon_M2_vmpy2es_s0>; 427 428//Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat 429def : T_PP_pat <M2_mmpyh_s0, int_hexagon_M2_mmpyh_s0>; 430def : T_PP_pat <M2_mmpyh_s1, int_hexagon_M2_mmpyh_s1>; 431def : T_PP_pat <M2_mmpyh_rs0, int_hexagon_M2_mmpyh_rs0>; 432def : T_PP_pat <M2_mmpyh_rs1, int_hexagon_M2_mmpyh_rs1>; 433 434//Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat 435def : T_PP_pat <M2_mmpyl_s0, int_hexagon_M2_mmpyl_s0>; 436def : T_PP_pat <M2_mmpyl_s1, int_hexagon_M2_mmpyl_s1>; 437def : T_PP_pat <M2_mmpyl_rs0, int_hexagon_M2_mmpyl_rs0>; 438def : T_PP_pat <M2_mmpyl_rs1, int_hexagon_M2_mmpyl_rs1>; 439 440//Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat 441def : T_PP_pat <M2_mmpyuh_s0, int_hexagon_M2_mmpyuh_s0>; 442def : T_PP_pat <M2_mmpyuh_s1, int_hexagon_M2_mmpyuh_s1>; 443def : T_PP_pat <M2_mmpyuh_rs0, int_hexagon_M2_mmpyuh_rs0>; 444def : T_PP_pat <M2_mmpyuh_rs1, int_hexagon_M2_mmpyuh_rs1>; 445 446//Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat 447def : T_PP_pat <M2_mmpyul_s0, int_hexagon_M2_mmpyul_s0>; 448def : T_PP_pat <M2_mmpyul_s1, int_hexagon_M2_mmpyul_s1>; 449def : T_PP_pat <M2_mmpyul_rs0, int_hexagon_M2_mmpyul_rs0>; 450def : T_PP_pat <M2_mmpyul_rs1, int_hexagon_M2_mmpyul_rs1>; 451 452// Vector reduce add unsigned bytes: Rdd32[+]=vrmpybu(Rss32,Rtt32) 453def : T_PP_pat <A2_vraddub, int_hexagon_A2_vraddub>; 454def : T_PPP_pat <A2_vraddub_acc, int_hexagon_A2_vraddub_acc>; 455 456// Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt) 457def : T_PP_pat <A2_vrsadub, int_hexagon_A2_vrsadub>; 458def : T_PPP_pat <A2_vrsadub_acc, int_hexagon_A2_vrsadub_acc>; 459 460// Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss) 461def : T_PP_pat <M2_vabsdiffh, int_hexagon_M2_vabsdiffh>; 462 463// Vector absolute difference words: Rdd=vabsdiffw(Rtt,Rss) 464def : T_PP_pat <M2_vabsdiffw, int_hexagon_M2_vabsdiffw>; 465 466// Vector reduce complex multiply real or imaginary: 467// Rdd[+]=vrcmpy[ir](Rss,Rtt[*]) 468def : T_PP_pat <M2_vrcmpyi_s0, int_hexagon_M2_vrcmpyi_s0>; 469def : T_PP_pat <M2_vrcmpyi_s0c, int_hexagon_M2_vrcmpyi_s0c>; 470def : T_PPP_pat <M2_vrcmaci_s0, int_hexagon_M2_vrcmaci_s0>; 471def : T_PPP_pat <M2_vrcmaci_s0c, int_hexagon_M2_vrcmaci_s0c>; 472 473def : T_PP_pat <M2_vrcmpyr_s0, int_hexagon_M2_vrcmpyr_s0>; 474def : T_PP_pat <M2_vrcmpyr_s0c, int_hexagon_M2_vrcmpyr_s0c>; 475def : T_PPP_pat <M2_vrcmacr_s0, int_hexagon_M2_vrcmacr_s0>; 476def : T_PPP_pat <M2_vrcmacr_s0c, int_hexagon_M2_vrcmacr_s0c>; 477 478// Vector reduce halfwords 479// Rdd[+]=vrmpyh(Rss,Rtt) 480def : T_PP_pat <M2_vrmpy_s0, int_hexagon_M2_vrmpy_s0>; 481def : T_PPP_pat <M2_vrmac_s0, int_hexagon_M2_vrmac_s0>; 482 483//===----------------------------------------------------------------------===// 484// Vector Multipy with accumulation 485//===----------------------------------------------------------------------===// 486 487// Vector multiply word by signed half with accumulation 488// Rxx+=vmpyw[eo]h(Rss,Rtt)[:<<1][:rnd]:sat 489def : T_PPP_pat <M2_mmacls_s1, int_hexagon_M2_mmacls_s1>; 490def : T_PPP_pat <M2_mmacls_s0, int_hexagon_M2_mmacls_s0>; 491def : T_PPP_pat <M2_mmacls_rs1, int_hexagon_M2_mmacls_rs1>; 492def : T_PPP_pat <M2_mmacls_rs0, int_hexagon_M2_mmacls_rs0>; 493def : T_PPP_pat <M2_mmachs_s1, int_hexagon_M2_mmachs_s1>; 494def : T_PPP_pat <M2_mmachs_s0, int_hexagon_M2_mmachs_s0>; 495def : T_PPP_pat <M2_mmachs_rs1, int_hexagon_M2_mmachs_rs1>; 496def : T_PPP_pat <M2_mmachs_rs0, int_hexagon_M2_mmachs_rs0>; 497 498// Vector multiply word by unsigned half with accumulation 499// Rxx+=vmpyw[eo]uh(Rss,Rtt)[:<<1][:rnd]:sat 500def : T_PPP_pat <M2_mmaculs_s1, int_hexagon_M2_mmaculs_s1>; 501def : T_PPP_pat <M2_mmaculs_s0, int_hexagon_M2_mmaculs_s0>; 502def : T_PPP_pat <M2_mmaculs_rs1, int_hexagon_M2_mmaculs_rs1>; 503def : T_PPP_pat <M2_mmaculs_rs0, int_hexagon_M2_mmaculs_rs0>; 504def : T_PPP_pat <M2_mmacuhs_s1, int_hexagon_M2_mmacuhs_s1>; 505def : T_PPP_pat <M2_mmacuhs_s0, int_hexagon_M2_mmacuhs_s0>; 506def : T_PPP_pat <M2_mmacuhs_rs1, int_hexagon_M2_mmacuhs_rs1>; 507def : T_PPP_pat <M2_mmacuhs_rs0, int_hexagon_M2_mmacuhs_rs0>; 508 509// Vector multiply even halfwords with accumulation 510// Rxx+=vmpyeh(Rss,Rtt)[:<<1][:sat] 511def : T_PPP_pat <M2_vmac2es, int_hexagon_M2_vmac2es>; 512def : T_PPP_pat <M2_vmac2es_s1, int_hexagon_M2_vmac2es_s1>; 513def : T_PPP_pat <M2_vmac2es_s0, int_hexagon_M2_vmac2es_s0>; 514 515// Vector dual multiply with accumulation 516// Rxx+=vdmpy(Rss,Rtt)[:sat] 517def : T_PPP_pat <M2_vdmacs_s1, int_hexagon_M2_vdmacs_s1>; 518def : T_PPP_pat <M2_vdmacs_s0, int_hexagon_M2_vdmacs_s0>; 519 520// Vector complex multiply real or imaginary with accumulation 521// Rxx+=vcmpy[ir](Rss,Rtt):sat 522def : T_PPP_pat <M2_vcmac_s0_sat_r, int_hexagon_M2_vcmac_s0_sat_r>; 523def : T_PPP_pat <M2_vcmac_s0_sat_i, int_hexagon_M2_vcmac_s0_sat_i>; 524 525//===----------------------------------------------------------------------===// 526// Add/Subtract halfword 527// Rd=add(Rt.L,Rs.[HL])[:sat] 528// Rd=sub(Rt.L,Rs.[HL])[:sat] 529// Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16] 530// Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16] 531//===----------------------------------------------------------------------===// 532 533//Rd=add(Rt.L,Rs.[LH]) 534def : T_RR_pat <A2_addh_l16_ll, int_hexagon_A2_addh_l16_ll>; 535def : T_RR_pat <A2_addh_l16_hl, int_hexagon_A2_addh_l16_hl>; 536 537//Rd=add(Rt.L,Rs.[LH]):sat 538def : T_RR_pat <A2_addh_l16_sat_ll, int_hexagon_A2_addh_l16_sat_ll>; 539def : T_RR_pat <A2_addh_l16_sat_hl, int_hexagon_A2_addh_l16_sat_hl>; 540 541//Rd=sub(Rt.L,Rs.[LH]) 542def : T_RR_pat <A2_subh_l16_ll, int_hexagon_A2_subh_l16_ll>; 543def : T_RR_pat <A2_subh_l16_hl, int_hexagon_A2_subh_l16_hl>; 544 545//Rd=sub(Rt.L,Rs.[LH]):sat 546def : T_RR_pat <A2_subh_l16_sat_ll, int_hexagon_A2_subh_l16_sat_ll>; 547def : T_RR_pat <A2_subh_l16_sat_hl, int_hexagon_A2_subh_l16_sat_hl>; 548 549//Rd=add(Rt.[LH],Rs.[LH]):<<16 550def : T_RR_pat <A2_addh_h16_ll, int_hexagon_A2_addh_h16_ll>; 551def : T_RR_pat <A2_addh_h16_lh, int_hexagon_A2_addh_h16_lh>; 552def : T_RR_pat <A2_addh_h16_hl, int_hexagon_A2_addh_h16_hl>; 553def : T_RR_pat <A2_addh_h16_hh, int_hexagon_A2_addh_h16_hh>; 554 555//Rd=sub(Rt.[LH],Rs.[LH]):<<16 556def : T_RR_pat <A2_subh_h16_ll, int_hexagon_A2_subh_h16_ll>; 557def : T_RR_pat <A2_subh_h16_lh, int_hexagon_A2_subh_h16_lh>; 558def : T_RR_pat <A2_subh_h16_hl, int_hexagon_A2_subh_h16_hl>; 559def : T_RR_pat <A2_subh_h16_hh, int_hexagon_A2_subh_h16_hh>; 560 561//Rd=add(Rt.[LH],Rs.[LH]):sat:<<16 562def : T_RR_pat <A2_addh_h16_sat_ll, int_hexagon_A2_addh_h16_sat_ll>; 563def : T_RR_pat <A2_addh_h16_sat_lh, int_hexagon_A2_addh_h16_sat_lh>; 564def : T_RR_pat <A2_addh_h16_sat_hl, int_hexagon_A2_addh_h16_sat_hl>; 565def : T_RR_pat <A2_addh_h16_sat_hh, int_hexagon_A2_addh_h16_sat_hh>; 566 567//Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16 568def : T_RR_pat <A2_subh_h16_sat_ll, int_hexagon_A2_subh_h16_sat_ll>; 569def : T_RR_pat <A2_subh_h16_sat_lh, int_hexagon_A2_subh_h16_sat_lh>; 570def : T_RR_pat <A2_subh_h16_sat_hl, int_hexagon_A2_subh_h16_sat_hl>; 571def : T_RR_pat <A2_subh_h16_sat_hh, int_hexagon_A2_subh_h16_sat_hh>; 572 573// ALU64 / ALU / min max 574def : T_RR_pat<A2_max, int_hexagon_A2_max>; 575def : T_RR_pat<A2_min, int_hexagon_A2_min>; 576def : T_RR_pat<A2_maxu, int_hexagon_A2_maxu>; 577def : T_RR_pat<A2_minu, int_hexagon_A2_minu>; 578 579// Shift and accumulate 580def : T_RRI_pat <S2_asr_i_r_nac, int_hexagon_S2_asr_i_r_nac>; 581def : T_RRI_pat <S2_lsr_i_r_nac, int_hexagon_S2_lsr_i_r_nac>; 582def : T_RRI_pat <S2_asl_i_r_nac, int_hexagon_S2_asl_i_r_nac>; 583def : T_RRI_pat <S2_asr_i_r_acc, int_hexagon_S2_asr_i_r_acc>; 584def : T_RRI_pat <S2_lsr_i_r_acc, int_hexagon_S2_lsr_i_r_acc>; 585def : T_RRI_pat <S2_asl_i_r_acc, int_hexagon_S2_asl_i_r_acc>; 586 587def : T_RRI_pat <S2_asr_i_r_and, int_hexagon_S2_asr_i_r_and>; 588def : T_RRI_pat <S2_lsr_i_r_and, int_hexagon_S2_lsr_i_r_and>; 589def : T_RRI_pat <S2_asl_i_r_and, int_hexagon_S2_asl_i_r_and>; 590def : T_RRI_pat <S2_asr_i_r_or, int_hexagon_S2_asr_i_r_or>; 591def : T_RRI_pat <S2_lsr_i_r_or, int_hexagon_S2_lsr_i_r_or>; 592def : T_RRI_pat <S2_asl_i_r_or, int_hexagon_S2_asl_i_r_or>; 593def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>; 594def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>; 595 596def : T_PPI_pat <S2_asr_i_p_nac, int_hexagon_S2_asr_i_p_nac>; 597def : T_PPI_pat <S2_lsr_i_p_nac, int_hexagon_S2_lsr_i_p_nac>; 598def : T_PPI_pat <S2_asl_i_p_nac, int_hexagon_S2_asl_i_p_nac>; 599def : T_PPI_pat <S2_asr_i_p_acc, int_hexagon_S2_asr_i_p_acc>; 600def : T_PPI_pat <S2_lsr_i_p_acc, int_hexagon_S2_lsr_i_p_acc>; 601def : T_PPI_pat <S2_asl_i_p_acc, int_hexagon_S2_asl_i_p_acc>; 602 603def : T_PPI_pat <S2_asr_i_p_and, int_hexagon_S2_asr_i_p_and>; 604def : T_PPI_pat <S2_lsr_i_p_and, int_hexagon_S2_lsr_i_p_and>; 605def : T_PPI_pat <S2_asl_i_p_and, int_hexagon_S2_asl_i_p_and>; 606def : T_PPI_pat <S2_asr_i_p_or, int_hexagon_S2_asr_i_p_or>; 607def : T_PPI_pat <S2_lsr_i_p_or, int_hexagon_S2_lsr_i_p_or>; 608def : T_PPI_pat <S2_asl_i_p_or, int_hexagon_S2_asl_i_p_or>; 609def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>; 610def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>; 611 612def : T_RRR_pat <S2_asr_r_r_nac, int_hexagon_S2_asr_r_r_nac>; 613def : T_RRR_pat <S2_lsr_r_r_nac, int_hexagon_S2_lsr_r_r_nac>; 614def : T_RRR_pat <S2_asl_r_r_nac, int_hexagon_S2_asl_r_r_nac>; 615def : T_RRR_pat <S2_lsl_r_r_nac, int_hexagon_S2_lsl_r_r_nac>; 616def : T_RRR_pat <S2_asr_r_r_acc, int_hexagon_S2_asr_r_r_acc>; 617def : T_RRR_pat <S2_lsr_r_r_acc, int_hexagon_S2_lsr_r_r_acc>; 618def : T_RRR_pat <S2_asl_r_r_acc, int_hexagon_S2_asl_r_r_acc>; 619def : T_RRR_pat <S2_lsl_r_r_acc, int_hexagon_S2_lsl_r_r_acc>; 620 621def : T_RRR_pat <S2_asr_r_r_and, int_hexagon_S2_asr_r_r_and>; 622def : T_RRR_pat <S2_lsr_r_r_and, int_hexagon_S2_lsr_r_r_and>; 623def : T_RRR_pat <S2_asl_r_r_and, int_hexagon_S2_asl_r_r_and>; 624def : T_RRR_pat <S2_lsl_r_r_and, int_hexagon_S2_lsl_r_r_and>; 625def : T_RRR_pat <S2_asr_r_r_or, int_hexagon_S2_asr_r_r_or>; 626def : T_RRR_pat <S2_lsr_r_r_or, int_hexagon_S2_lsr_r_r_or>; 627def : T_RRR_pat <S2_asl_r_r_or, int_hexagon_S2_asl_r_r_or>; 628def : T_RRR_pat <S2_lsl_r_r_or, int_hexagon_S2_lsl_r_r_or>; 629 630def : T_PPR_pat <S2_asr_r_p_nac, int_hexagon_S2_asr_r_p_nac>; 631def : T_PPR_pat <S2_lsr_r_p_nac, int_hexagon_S2_lsr_r_p_nac>; 632def : T_PPR_pat <S2_asl_r_p_nac, int_hexagon_S2_asl_r_p_nac>; 633def : T_PPR_pat <S2_lsl_r_p_nac, int_hexagon_S2_lsl_r_p_nac>; 634def : T_PPR_pat <S2_asr_r_p_acc, int_hexagon_S2_asr_r_p_acc>; 635def : T_PPR_pat <S2_lsr_r_p_acc, int_hexagon_S2_lsr_r_p_acc>; 636def : T_PPR_pat <S2_asl_r_p_acc, int_hexagon_S2_asl_r_p_acc>; 637def : T_PPR_pat <S2_lsl_r_p_acc, int_hexagon_S2_lsl_r_p_acc>; 638 639def : T_PPR_pat <S2_asr_r_p_and, int_hexagon_S2_asr_r_p_and>; 640def : T_PPR_pat <S2_lsr_r_p_and, int_hexagon_S2_lsr_r_p_and>; 641def : T_PPR_pat <S2_asl_r_p_and, int_hexagon_S2_asl_r_p_and>; 642def : T_PPR_pat <S2_lsl_r_p_and, int_hexagon_S2_lsl_r_p_and>; 643def : T_PPR_pat <S2_asr_r_p_or, int_hexagon_S2_asr_r_p_or>; 644def : T_PPR_pat <S2_lsr_r_p_or, int_hexagon_S2_lsr_r_p_or>; 645def : T_PPR_pat <S2_asl_r_p_or, int_hexagon_S2_asl_r_p_or>; 646def : T_PPR_pat <S2_lsl_r_p_or, int_hexagon_S2_lsl_r_p_or>; 647 648def : T_RRI_pat <S2_asr_i_r_nac, int_hexagon_S2_asr_i_r_nac>; 649def : T_RRI_pat <S2_lsr_i_r_nac, int_hexagon_S2_lsr_i_r_nac>; 650def : T_RRI_pat <S2_asl_i_r_nac, int_hexagon_S2_asl_i_r_nac>; 651def : T_RRI_pat <S2_asr_i_r_acc, int_hexagon_S2_asr_i_r_acc>; 652def : T_RRI_pat <S2_lsr_i_r_acc, int_hexagon_S2_lsr_i_r_acc>; 653def : T_RRI_pat <S2_asl_i_r_acc, int_hexagon_S2_asl_i_r_acc>; 654 655def : T_RRI_pat <S2_asr_i_r_and, int_hexagon_S2_asr_i_r_and>; 656def : T_RRI_pat <S2_lsr_i_r_and, int_hexagon_S2_lsr_i_r_and>; 657def : T_RRI_pat <S2_asl_i_r_and, int_hexagon_S2_asl_i_r_and>; 658def : T_RRI_pat <S2_asr_i_r_or, int_hexagon_S2_asr_i_r_or>; 659def : T_RRI_pat <S2_lsr_i_r_or, int_hexagon_S2_lsr_i_r_or>; 660def : T_RRI_pat <S2_asl_i_r_or, int_hexagon_S2_asl_i_r_or>; 661def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>; 662def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>; 663 664def : T_PPI_pat <S2_asr_i_p_nac, int_hexagon_S2_asr_i_p_nac>; 665def : T_PPI_pat <S2_lsr_i_p_nac, int_hexagon_S2_lsr_i_p_nac>; 666def : T_PPI_pat <S2_asl_i_p_nac, int_hexagon_S2_asl_i_p_nac>; 667def : T_PPI_pat <S2_asr_i_p_acc, int_hexagon_S2_asr_i_p_acc>; 668def : T_PPI_pat <S2_lsr_i_p_acc, int_hexagon_S2_lsr_i_p_acc>; 669def : T_PPI_pat <S2_asl_i_p_acc, int_hexagon_S2_asl_i_p_acc>; 670 671def : T_PPI_pat <S2_asr_i_p_and, int_hexagon_S2_asr_i_p_and>; 672def : T_PPI_pat <S2_lsr_i_p_and, int_hexagon_S2_lsr_i_p_and>; 673def : T_PPI_pat <S2_asl_i_p_and, int_hexagon_S2_asl_i_p_and>; 674def : T_PPI_pat <S2_asr_i_p_or, int_hexagon_S2_asr_i_p_or>; 675def : T_PPI_pat <S2_lsr_i_p_or, int_hexagon_S2_lsr_i_p_or>; 676def : T_PPI_pat <S2_asl_i_p_or, int_hexagon_S2_asl_i_p_or>; 677def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>; 678def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>; 679 680def : T_RRR_pat <S2_asr_r_r_nac, int_hexagon_S2_asr_r_r_nac>; 681def : T_RRR_pat <S2_lsr_r_r_nac, int_hexagon_S2_lsr_r_r_nac>; 682def : T_RRR_pat <S2_asl_r_r_nac, int_hexagon_S2_asl_r_r_nac>; 683def : T_RRR_pat <S2_lsl_r_r_nac, int_hexagon_S2_lsl_r_r_nac>; 684def : T_RRR_pat <S2_asr_r_r_acc, int_hexagon_S2_asr_r_r_acc>; 685def : T_RRR_pat <S2_lsr_r_r_acc, int_hexagon_S2_lsr_r_r_acc>; 686def : T_RRR_pat <S2_asl_r_r_acc, int_hexagon_S2_asl_r_r_acc>; 687def : T_RRR_pat <S2_lsl_r_r_acc, int_hexagon_S2_lsl_r_r_acc>; 688 689def : T_RRR_pat <S2_asr_r_r_and, int_hexagon_S2_asr_r_r_and>; 690def : T_RRR_pat <S2_lsr_r_r_and, int_hexagon_S2_lsr_r_r_and>; 691def : T_RRR_pat <S2_asl_r_r_and, int_hexagon_S2_asl_r_r_and>; 692def : T_RRR_pat <S2_lsl_r_r_and, int_hexagon_S2_lsl_r_r_and>; 693def : T_RRR_pat <S2_asr_r_r_or, int_hexagon_S2_asr_r_r_or>; 694def : T_RRR_pat <S2_lsr_r_r_or, int_hexagon_S2_lsr_r_r_or>; 695def : T_RRR_pat <S2_asl_r_r_or, int_hexagon_S2_asl_r_r_or>; 696def : T_RRR_pat <S2_lsl_r_r_or, int_hexagon_S2_lsl_r_r_or>; 697 698def : T_PPR_pat <S2_asr_r_p_nac, int_hexagon_S2_asr_r_p_nac>; 699def : T_PPR_pat <S2_lsr_r_p_nac, int_hexagon_S2_lsr_r_p_nac>; 700def : T_PPR_pat <S2_asl_r_p_nac, int_hexagon_S2_asl_r_p_nac>; 701def : T_PPR_pat <S2_lsl_r_p_nac, int_hexagon_S2_lsl_r_p_nac>; 702def : T_PPR_pat <S2_asr_r_p_acc, int_hexagon_S2_asr_r_p_acc>; 703def : T_PPR_pat <S2_lsr_r_p_acc, int_hexagon_S2_lsr_r_p_acc>; 704def : T_PPR_pat <S2_asl_r_p_acc, int_hexagon_S2_asl_r_p_acc>; 705def : T_PPR_pat <S2_lsl_r_p_acc, int_hexagon_S2_lsl_r_p_acc>; 706 707def : T_PPR_pat <S2_asr_r_p_and, int_hexagon_S2_asr_r_p_and>; 708def : T_PPR_pat <S2_lsr_r_p_and, int_hexagon_S2_lsr_r_p_and>; 709def : T_PPR_pat <S2_asl_r_p_and, int_hexagon_S2_asl_r_p_and>; 710def : T_PPR_pat <S2_lsl_r_p_and, int_hexagon_S2_lsl_r_p_and>; 711def : T_PPR_pat <S2_asr_r_p_or, int_hexagon_S2_asr_r_p_or>; 712def : T_PPR_pat <S2_lsr_r_p_or, int_hexagon_S2_lsr_r_p_or>; 713def : T_PPR_pat <S2_asl_r_p_or, int_hexagon_S2_asl_r_p_or>; 714def : T_PPR_pat <S2_lsl_r_p_or, int_hexagon_S2_lsl_r_p_or>; 715 716//******************************************************************* 717// ALU32/ALU 718//******************************************************************* 719def : T_RR_pat<A2_add, int_hexagon_A2_add>; 720def : T_RI_pat<A2_addi, int_hexagon_A2_addi>; 721def : T_RR_pat<A2_sub, int_hexagon_A2_sub>; 722def : T_IR_pat<A2_subri, int_hexagon_A2_subri>; 723def : T_RR_pat<A2_and, int_hexagon_A2_and>; 724def : T_RI_pat<A2_andir, int_hexagon_A2_andir>; 725def : T_RR_pat<A2_or, int_hexagon_A2_or>; 726def : T_RI_pat<A2_orir, int_hexagon_A2_orir>; 727def : T_RR_pat<A2_xor, int_hexagon_A2_xor>; 728def : T_RR_pat<A2_combinew, int_hexagon_A2_combinew>; 729 730// Assembler mapped from Rd32=not(Rs32) to Rd32=sub(#-1,Rs32) 731def : Pat <(int_hexagon_A2_not I32:$Rs), 732 (A2_subri -1, I32:$Rs)>; 733 734// Assembler mapped from Rd32=neg(Rs32) to Rd32=sub(#0,Rs32) 735def : Pat <(int_hexagon_A2_neg I32:$Rs), 736 (A2_subri 0, I32:$Rs)>; 737 738// Make sure the patterns with zero immediate value has higher complexity 739// otherwise, we need to updated the predicates for immediates to exclude zero 740let AddedComplexity = 200 in { 741def : Pat <(int_hexagon_S2_asr_i_r_rnd_goodsyntax I32:$Rs, (i32 0)), 742 (A2_tfr I32:$Rs)>; 743def : Pat <(int_hexagon_S2_asr_i_p_rnd_goodsyntax I64:$Rs, (i32 0)), 744 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>; 745def : Pat <(int_hexagon_S5_vasrhrnd_goodsyntax I64:$Rs, (i32 0)), 746 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>; 747def : Pat <(int_hexagon_S5_asrhub_rnd_sat_goodsyntax I64:$Rs, (i32 0)), 748 (S2_vsathub I64:$Rs)>; 749} 750 751def : Pat <(int_hexagon_S2_asr_i_r_rnd_goodsyntax I32:$Rs, u5_0ImmPred:$imm), 752 (S2_asr_i_r_rnd I32:$Rs, (UDEC1 u5_0ImmPred:$imm))>; 753def : Pat <(int_hexagon_S2_asr_i_p_rnd_goodsyntax I64:$Rs, u6_0ImmPred:$imm), 754 (S2_asr_i_p_rnd I64:$Rs, (UDEC1 u6_0ImmPred:$imm))>; 755def : Pat <(int_hexagon_S5_vasrhrnd_goodsyntax I64:$Rs, u4_0ImmPred:$imm), 756 (S5_vasrhrnd I64:$Rs, (UDEC1 u4_0ImmPred:$imm))>; 757def : Pat <(int_hexagon_S5_asrhub_rnd_sat_goodsyntax I64:$Rs, u4_0ImmPred:$imm), 758 (S5_asrhub_rnd_sat I64:$Rs, (UDEC1 u4_0ImmPred:$imm))>; 759 760// Transfer immediate 761def : Pat <(int_hexagon_A2_tfril I32:$Rs, u16_0ImmPred:$Is), 762 (A2_tfril I32:$Rs, u16_0ImmPred:$Is)>; 763def : Pat <(int_hexagon_A2_tfrih I32:$Rs, u16_0ImmPred:$Is), 764 (A2_tfrih I32:$Rs, u16_0ImmPred:$Is)>; 765 766// Transfer Register/immediate. 767def : T_R_pat <A2_tfr, int_hexagon_A2_tfr>; 768def : T_I_pat <A2_tfrsi, int_hexagon_A2_tfrsi>; 769 770def ImmExt64: SDNodeXForm<imm, [{ 771 int64_t V = N->getSExtValue(); 772 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i64); 773}]>; 774 775// A2_tfrpi has an operand of type i64. This is necessary, since it is 776// generated from "(set I64:$Rd, imm)". That pattern would not appear 777// in the DAG, if the immediate was not a 64-bit value. 778// The builtin for A2_tfrpi, on the other hand, takes a 32-bit value, 779// which makes it impossible to simply replace it with the instruction. 780// To connect the builtin with the instruction, the builtin's operand 781// needs to be extended to the right type. 782 783def : Pat<(int_hexagon_A2_tfrpi imm:$Is), 784 (A2_tfrpi (ImmExt64 $Is))>; 785 786// Assembler mapped from Rdd32=Rss32 to Rdd32=combine(Rss.H32,Rss.L32) 787def : Pat<(int_hexagon_A2_tfrp I64:$src), 788 (A2_combinew (HiReg I64:$src), (LoReg I64:$src))>; 789 790//******************************************************************* 791// ALU32/PERM 792//******************************************************************* 793// Combine 794def: T_RR_pat<A2_combine_hh, int_hexagon_A2_combine_hh>; 795def: T_RR_pat<A2_combine_hl, int_hexagon_A2_combine_hl>; 796def: T_RR_pat<A2_combine_lh, int_hexagon_A2_combine_lh>; 797def: T_RR_pat<A2_combine_ll, int_hexagon_A2_combine_ll>; 798 799def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s32_0ImmPred, s8_0ImmPred>; 800 801// Mux 802def : T_QRR_pat<C2_mux, int_hexagon_C2_mux>; 803def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s32_0ImmPred>; 804def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s32_0ImmPred>; 805def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s32_0ImmPred, s8_0ImmPred>; 806 807// Shift halfword 808def : T_R_pat<A2_aslh, int_hexagon_A2_aslh>; 809def : T_R_pat<A2_asrh, int_hexagon_A2_asrh>; 810 811// Sign/zero extend 812def : T_R_pat<A2_sxth, int_hexagon_A2_sxth>; 813def : T_R_pat<A2_sxtb, int_hexagon_A2_sxtb>; 814def : T_R_pat<A2_zxth, int_hexagon_A2_zxth>; 815def : T_R_pat<A2_zxtb, int_hexagon_A2_zxtb>; 816 817//******************************************************************* 818// ALU32/PRED 819//******************************************************************* 820// Compare 821def : T_Q_RR_pat<C2_cmpeq, int_hexagon_C2_cmpeq>; 822def : T_Q_RR_pat<C2_cmpgt, int_hexagon_C2_cmpgt>; 823def : T_Q_RR_pat<C2_cmpgtu, int_hexagon_C2_cmpgtu>; 824 825def : T_Q_RI_pat<C2_cmpeqi, int_hexagon_C2_cmpeqi, s32_0ImmPred>; 826def : T_Q_RI_pat<C2_cmpgti, int_hexagon_C2_cmpgti, s32_0ImmPred>; 827def : T_Q_RI_pat<C2_cmpgtui, int_hexagon_C2_cmpgtui, u32_0ImmPred>; 828 829def : Pat <(int_hexagon_C2_cmpgei I32:$src1, s32_0ImmPred:$src2), 830 (C2_tfrpr (C2_cmpgti I32:$src1, (SDEC1 s32_0ImmPred:$src2)))>; 831 832def : Pat <(int_hexagon_C2_cmpgeui I32:$src1, u32_0ImmPred:$src2), 833 (C2_tfrpr (C2_cmpgtui I32:$src1, (UDEC1 u32_0ImmPred:$src2)))>; 834 835def : Pat <(int_hexagon_C2_cmpgeui I32:$src, 0), 836 (C2_tfrpr (C2_cmpeq I32:$src, I32:$src))>; 837def : Pat <(int_hexagon_C2_cmplt I32:$src1, I32:$src2), 838 (C2_tfrpr (C2_cmpgt I32:$src2, I32:$src1))>; 839def : Pat <(int_hexagon_C2_cmpltu I32:$src1, I32:$src2), 840 (C2_tfrpr (C2_cmpgtu I32:$src2, I32:$src1))>; 841 842//******************************************************************* 843// ALU32/VH 844//******************************************************************* 845// Vector add, subtract, average halfwords 846def: T_RR_pat<A2_svaddh, int_hexagon_A2_svaddh>; 847def: T_RR_pat<A2_svaddhs, int_hexagon_A2_svaddhs>; 848def: T_RR_pat<A2_svadduhs, int_hexagon_A2_svadduhs>; 849 850def: T_RR_pat<A2_svsubh, int_hexagon_A2_svsubh>; 851def: T_RR_pat<A2_svsubhs, int_hexagon_A2_svsubhs>; 852def: T_RR_pat<A2_svsubuhs, int_hexagon_A2_svsubuhs>; 853 854def: T_RR_pat<A2_svavgh, int_hexagon_A2_svavgh>; 855def: T_RR_pat<A2_svavghs, int_hexagon_A2_svavghs>; 856def: T_RR_pat<A2_svnavgh, int_hexagon_A2_svnavgh>; 857 858//******************************************************************* 859// ALU64/ALU 860//******************************************************************* 861def: T_RR_pat<A2_addsat, int_hexagon_A2_addsat>; 862def: T_RR_pat<A2_subsat, int_hexagon_A2_subsat>; 863def: T_PP_pat<A2_addp, int_hexagon_A2_addp>; 864def: T_PP_pat<A2_subp, int_hexagon_A2_subp>; 865 866def: T_PP_pat<A2_andp, int_hexagon_A2_andp>; 867def: T_PP_pat<A2_orp, int_hexagon_A2_orp>; 868def: T_PP_pat<A2_xorp, int_hexagon_A2_xorp>; 869 870def: T_Q_PP_pat<C2_cmpeqp, int_hexagon_C2_cmpeqp>; 871def: T_Q_PP_pat<C2_cmpgtp, int_hexagon_C2_cmpgtp>; 872def: T_Q_PP_pat<C2_cmpgtup, int_hexagon_C2_cmpgtup>; 873 874def: T_PP_pat<S2_parityp, int_hexagon_S2_parityp>; 875def: T_RR_pat<S2_packhl, int_hexagon_S2_packhl>; 876 877//******************************************************************* 878// ALU64/VB 879//******************************************************************* 880// ALU64 - Vector add 881def : T_PP_pat <A2_vaddub, int_hexagon_A2_vaddub>; 882def : T_PP_pat <A2_vaddubs, int_hexagon_A2_vaddubs>; 883def : T_PP_pat <A2_vaddh, int_hexagon_A2_vaddh>; 884def : T_PP_pat <A2_vaddhs, int_hexagon_A2_vaddhs>; 885def : T_PP_pat <A2_vadduhs, int_hexagon_A2_vadduhs>; 886def : T_PP_pat <A2_vaddw, int_hexagon_A2_vaddw>; 887def : T_PP_pat <A2_vaddws, int_hexagon_A2_vaddws>; 888 889// ALU64 - Vector average 890def : T_PP_pat <A2_vavgub, int_hexagon_A2_vavgub>; 891def : T_PP_pat <A2_vavgubr, int_hexagon_A2_vavgubr>; 892def : T_PP_pat <A2_vavgh, int_hexagon_A2_vavgh>; 893def : T_PP_pat <A2_vavghr, int_hexagon_A2_vavghr>; 894def : T_PP_pat <A2_vavghcr, int_hexagon_A2_vavghcr>; 895def : T_PP_pat <A2_vavguh, int_hexagon_A2_vavguh>; 896def : T_PP_pat <A2_vavguhr, int_hexagon_A2_vavguhr>; 897 898def : T_PP_pat <A2_vavgw, int_hexagon_A2_vavgw>; 899def : T_PP_pat <A2_vavgwr, int_hexagon_A2_vavgwr>; 900def : T_PP_pat <A2_vavgwcr, int_hexagon_A2_vavgwcr>; 901def : T_PP_pat <A2_vavguw, int_hexagon_A2_vavguw>; 902def : T_PP_pat <A2_vavguwr, int_hexagon_A2_vavguwr>; 903 904// ALU64 - Vector negative average 905def : T_PP_pat <A2_vnavgh, int_hexagon_A2_vnavgh>; 906def : T_PP_pat <A2_vnavghr, int_hexagon_A2_vnavghr>; 907def : T_PP_pat <A2_vnavghcr, int_hexagon_A2_vnavghcr>; 908def : T_PP_pat <A2_vnavgw, int_hexagon_A2_vnavgw>; 909def : T_PP_pat <A2_vnavgwr, int_hexagon_A2_vnavgwr>; 910def : T_PP_pat <A2_vnavgwcr, int_hexagon_A2_vnavgwcr>; 911 912// ALU64 - Vector max 913def : T_PP_pat <A2_vmaxh, int_hexagon_A2_vmaxh>; 914def : T_PP_pat <A2_vmaxw, int_hexagon_A2_vmaxw>; 915def : T_PP_pat <A2_vmaxub, int_hexagon_A2_vmaxub>; 916def : T_PP_pat <A2_vmaxuh, int_hexagon_A2_vmaxuh>; 917def : T_PP_pat <A2_vmaxuw, int_hexagon_A2_vmaxuw>; 918 919// ALU64 - Vector min 920def : T_PP_pat <A2_vminh, int_hexagon_A2_vminh>; 921def : T_PP_pat <A2_vminw, int_hexagon_A2_vminw>; 922def : T_PP_pat <A2_vminub, int_hexagon_A2_vminub>; 923def : T_PP_pat <A2_vminuh, int_hexagon_A2_vminuh>; 924def : T_PP_pat <A2_vminuw, int_hexagon_A2_vminuw>; 925 926// ALU64 - Vector sub 927def : T_PP_pat <A2_vsubub, int_hexagon_A2_vsubub>; 928def : T_PP_pat <A2_vsububs, int_hexagon_A2_vsububs>; 929def : T_PP_pat <A2_vsubh, int_hexagon_A2_vsubh>; 930def : T_PP_pat <A2_vsubhs, int_hexagon_A2_vsubhs>; 931def : T_PP_pat <A2_vsubuhs, int_hexagon_A2_vsubuhs>; 932def : T_PP_pat <A2_vsubw, int_hexagon_A2_vsubw>; 933def : T_PP_pat <A2_vsubws, int_hexagon_A2_vsubws>; 934 935// ALU64 - Vector compare bytes 936def : T_Q_PP_pat <A2_vcmpbeq, int_hexagon_A2_vcmpbeq>; 937def : T_Q_PP_pat <A4_vcmpbgt, int_hexagon_A4_vcmpbgt>; 938def : T_Q_PP_pat <A2_vcmpbgtu, int_hexagon_A2_vcmpbgtu>; 939 940// ALU64 - Vector compare halfwords 941def : T_Q_PP_pat <A2_vcmpheq, int_hexagon_A2_vcmpheq>; 942def : T_Q_PP_pat <A2_vcmphgt, int_hexagon_A2_vcmphgt>; 943def : T_Q_PP_pat <A2_vcmphgtu, int_hexagon_A2_vcmphgtu>; 944 945// ALU64 - Vector compare words 946def : T_Q_PP_pat <A2_vcmpweq, int_hexagon_A2_vcmpweq>; 947def : T_Q_PP_pat <A2_vcmpwgt, int_hexagon_A2_vcmpwgt>; 948def : T_Q_PP_pat <A2_vcmpwgtu, int_hexagon_A2_vcmpwgtu>; 949 950// ALU64 / VB / Vector mux. 951def : T_QPP_pat <C2_vmux, int_hexagon_C2_vmux>; 952 953// MPY - Multiply and use full result 954// Rdd = mpy[u](Rs, Rt) 955def : T_RR_pat <M2_dpmpyss_s0, int_hexagon_M2_dpmpyss_s0>; 956def : T_RR_pat <M2_dpmpyuu_s0, int_hexagon_M2_dpmpyuu_s0>; 957 958// Complex multiply real or imaginary 959def : T_RR_pat <M2_cmpyi_s0, int_hexagon_M2_cmpyi_s0>; 960def : T_RR_pat <M2_cmpyr_s0, int_hexagon_M2_cmpyr_s0>; 961 962// Complex multiply 963def : T_RR_pat <M2_cmpys_s0, int_hexagon_M2_cmpys_s0>; 964def : T_RR_pat <M2_cmpysc_s0, int_hexagon_M2_cmpysc_s0>; 965def : T_RR_pat <M2_cmpys_s1, int_hexagon_M2_cmpys_s1>; 966def : T_RR_pat <M2_cmpysc_s1, int_hexagon_M2_cmpysc_s1>; 967 968// Vector multiply halfwords 969// Rdd=vmpyh(Rs,Rt)[:<<1]:sat 970def : T_RR_pat <M2_vmpy2s_s0, int_hexagon_M2_vmpy2s_s0>; 971def : T_RR_pat <M2_vmpy2s_s1, int_hexagon_M2_vmpy2s_s1>; 972 973// Rxx[+-]= mpy[u](Rs,Rt) 974def : T_PRR_pat <M2_dpmpyss_acc_s0, int_hexagon_M2_dpmpyss_acc_s0>; 975def : T_PRR_pat <M2_dpmpyss_nac_s0, int_hexagon_M2_dpmpyss_nac_s0>; 976def : T_PRR_pat <M2_dpmpyuu_acc_s0, int_hexagon_M2_dpmpyuu_acc_s0>; 977def : T_PRR_pat <M2_dpmpyuu_nac_s0, int_hexagon_M2_dpmpyuu_nac_s0>; 978 979// Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat 980def : T_PRR_pat <M2_cmacs_s0, int_hexagon_M2_cmacs_s0>; 981def : T_PRR_pat <M2_cnacs_s0, int_hexagon_M2_cnacs_s0>; 982def : T_PRR_pat <M2_cmacs_s1, int_hexagon_M2_cmacs_s1>; 983def : T_PRR_pat <M2_cnacs_s1, int_hexagon_M2_cnacs_s1>; 984 985// Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat 986def : T_PRR_pat <M2_cmacsc_s0, int_hexagon_M2_cmacsc_s0>; 987def : T_PRR_pat <M2_cnacsc_s0, int_hexagon_M2_cnacsc_s0>; 988def : T_PRR_pat <M2_cmacsc_s1, int_hexagon_M2_cmacsc_s1>; 989def : T_PRR_pat <M2_cnacsc_s1, int_hexagon_M2_cnacsc_s1>; 990 991// Rxx+=cmpy[ir](Rs,Rt) 992def : T_PRR_pat <M2_cmaci_s0, int_hexagon_M2_cmaci_s0>; 993def : T_PRR_pat <M2_cmacr_s0, int_hexagon_M2_cmacr_s0>; 994 995// Rxx+=vmpyh(Rs,Rt)[:<<1][:sat] 996def : T_PRR_pat <M2_vmac2, int_hexagon_M2_vmac2>; 997def : T_PRR_pat <M2_vmac2s_s0, int_hexagon_M2_vmac2s_s0>; 998def : T_PRR_pat <M2_vmac2s_s1, int_hexagon_M2_vmac2s_s1>; 999 1000//******************************************************************* 1001// CR 1002//******************************************************************* 1003def: T_Q_Q_pat<C2_not, int_hexagon_C2_not>; 1004def: T_Q_Q_pat<C2_all8, int_hexagon_C2_all8>; 1005def: T_Q_Q_pat<C2_any8, int_hexagon_C2_any8>; 1006def: T_Q_Q_pat<C2_pxfer_map, int_hexagon_C2_pxfer_map>; 1007 1008def: T_Q_QQ_pat<C2_and, int_hexagon_C2_and>; 1009def: T_Q_QQ_pat<C2_andn, int_hexagon_C2_andn>; 1010def: T_Q_QQ_pat<C2_or, int_hexagon_C2_or>; 1011def: T_Q_QQ_pat<C2_orn, int_hexagon_C2_orn>; 1012def: T_Q_QQ_pat<C2_xor, int_hexagon_C2_xor>; 1013 1014// Multiply 32x32 and use lower result 1015def : T_RRI_pat <M2_macsip, int_hexagon_M2_macsip>; 1016def : T_RRI_pat <M2_macsin, int_hexagon_M2_macsin>; 1017def : T_RRR_pat <M2_maci, int_hexagon_M2_maci>; 1018 1019// Subtract and accumulate 1020def : T_RRR_pat <M2_subacc, int_hexagon_M2_subacc>; 1021 1022// Add and accumulate 1023def : T_RRR_pat <M2_acci, int_hexagon_M2_acci>; 1024def : T_RRR_pat <M2_nacci, int_hexagon_M2_nacci>; 1025def : T_RRI_pat <M2_accii, int_hexagon_M2_accii>; 1026def : T_RRI_pat <M2_naccii, int_hexagon_M2_naccii>; 1027 1028// XOR and XOR with destination 1029def : T_RRR_pat <M2_xor_xacc, int_hexagon_M2_xor_xacc>; 1030 1031// Vector dual multiply with round and pack 1032def : T_PP_pat <M2_vdmpyrs_s0, int_hexagon_M2_vdmpyrs_s0>; 1033def : T_PP_pat <M2_vdmpyrs_s1, int_hexagon_M2_vdmpyrs_s1>; 1034 1035// Vector multiply halfwords with round and pack 1036def : T_RR_pat <M2_vmpy2s_s0pack, int_hexagon_M2_vmpy2s_s0pack>; 1037def : T_RR_pat <M2_vmpy2s_s1pack, int_hexagon_M2_vmpy2s_s1pack>; 1038 1039// Multiply and use lower result 1040def : T_RR_pat <M2_mpyi, int_hexagon_M2_mpyi>; 1041def : T_RI_pat <M2_mpysmi, int_hexagon_M2_mpysmi>; 1042 1043// Assembler mapped from Rd32=mpyui(Rs32,Rt32) to Rd32=mpyi(Rs32,Rt32) 1044def : T_RR_pat <M2_mpyi, int_hexagon_M2_mpyui>; 1045 1046// Multiply and use upper result 1047def : T_RR_pat <M2_mpy_up, int_hexagon_M2_mpy_up>; 1048def : T_RR_pat <M2_mpyu_up, int_hexagon_M2_mpyu_up>; 1049def : T_RR_pat <M2_hmmpyh_rs1, int_hexagon_M2_hmmpyh_rs1>; 1050def : T_RR_pat <M2_hmmpyl_rs1, int_hexagon_M2_hmmpyl_rs1>; 1051def : T_RR_pat <M2_dpmpyss_rnd_s0, int_hexagon_M2_dpmpyss_rnd_s0>; 1052 1053// Complex multiply with round and pack 1054// Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat 1055def : T_RR_pat <M2_cmpyrs_s0, int_hexagon_M2_cmpyrs_s0>; 1056def : T_RR_pat <M2_cmpyrs_s1, int_hexagon_M2_cmpyrs_s1>; 1057def : T_RR_pat <M2_cmpyrsc_s0, int_hexagon_M2_cmpyrsc_s0>; 1058def : T_RR_pat <M2_cmpyrsc_s1, int_hexagon_M2_cmpyrsc_s1>; 1059 1060//******************************************************************* 1061// STYPE/ALU 1062//******************************************************************* 1063def : T_P_pat <A2_absp, int_hexagon_A2_absp>; 1064def : T_P_pat <A2_negp, int_hexagon_A2_negp>; 1065def : T_P_pat <A2_notp, int_hexagon_A2_notp>; 1066 1067//******************************************************************* 1068// STYPE/BIT 1069//******************************************************************* 1070 1071// Count leading/trailing 1072def: T_R_pat<S2_cl0, int_hexagon_S2_cl0>; 1073def: T_P_pat<S2_cl0p, int_hexagon_S2_cl0p>; 1074def: T_R_pat<S2_cl1, int_hexagon_S2_cl1>; 1075def: T_P_pat<S2_cl1p, int_hexagon_S2_cl1p>; 1076def: T_R_pat<S2_clb, int_hexagon_S2_clb>; 1077def: T_P_pat<S2_clbp, int_hexagon_S2_clbp>; 1078def: T_R_pat<S2_clbnorm, int_hexagon_S2_clbnorm>; 1079def: T_R_pat<S2_ct0, int_hexagon_S2_ct0>; 1080def: T_R_pat<S2_ct1, int_hexagon_S2_ct1>; 1081 1082// Compare bit mask 1083def: T_RR_pat<C2_bitsclr, int_hexagon_C2_bitsclr>; 1084def: T_RI_pat<C2_bitsclri, int_hexagon_C2_bitsclri>; 1085def: T_RR_pat<C2_bitsset, int_hexagon_C2_bitsset>; 1086 1087// Vector shuffle 1088def : T_PP_pat <S2_shuffeb, int_hexagon_S2_shuffeb>; 1089def : T_PP_pat <S2_shuffob, int_hexagon_S2_shuffob>; 1090def : T_PP_pat <S2_shuffeh, int_hexagon_S2_shuffeh>; 1091def : T_PP_pat <S2_shuffoh, int_hexagon_S2_shuffoh>; 1092 1093// Vector truncate 1094def : T_PP_pat <S2_vtrunewh, int_hexagon_S2_vtrunewh>; 1095def : T_PP_pat <S2_vtrunowh, int_hexagon_S2_vtrunowh>; 1096 1097// Linear feedback-shift Iteration. 1098def : T_PP_pat <S2_lfsp, int_hexagon_S2_lfsp>; 1099 1100// Vector align 1101// Need custom lowering 1102def : T_PPQ_pat <S2_valignrb, int_hexagon_S2_valignrb>; 1103def : T_PPI_pat <S2_valignib, int_hexagon_S2_valignib>; 1104 1105// Vector splice 1106def : T_PPQ_pat <S2_vsplicerb, int_hexagon_S2_vsplicerb>; 1107def : T_PPI_pat <S2_vspliceib, int_hexagon_S2_vspliceib>; 1108 1109// Shift by immediate and add 1110def : T_RRI_pat<S2_addasl_rrri, int_hexagon_S2_addasl_rrri>; 1111 1112// Extract bitfield 1113def : T_PII_pat<S2_extractup, int_hexagon_S2_extractup>; 1114def : T_RII_pat<S2_extractu, int_hexagon_S2_extractu>; 1115def : T_RP_pat <S2_extractu_rp, int_hexagon_S2_extractu_rp>; 1116def : T_PP_pat <S2_extractup_rp, int_hexagon_S2_extractup_rp>; 1117 1118// Insert bitfield 1119def : Pat <(int_hexagon_S2_insert_rp I32:$src1, I32:$src2, I64:$src3), 1120 (S2_insert_rp I32:$src1, I32:$src2, I64:$src3)>; 1121 1122def : Pat<(i64 (int_hexagon_S2_insertp_rp I64:$src1, I64:$src2, I64:$src3)), 1123 (i64 (S2_insertp_rp I64:$src1, I64:$src2, I64:$src3))>; 1124 1125def : Pat<(int_hexagon_S2_insert I32:$src1, I32:$src2, 1126 u5_0ImmPred:$src3, u5_0ImmPred:$src4), 1127 (S2_insert I32:$src1, I32:$src2, 1128 u5_0ImmPred:$src3, u5_0ImmPred:$src4)>; 1129 1130def : Pat<(i64 (int_hexagon_S2_insertp I64:$src1, I64:$src2, 1131 u6_0ImmPred:$src3, u6_0ImmPred:$src4)), 1132 (i64 (S2_insertp I64:$src1, I64:$src2, 1133 u6_0ImmPred:$src3, u6_0ImmPred:$src4))>; 1134 1135// Innterleave/deinterleave 1136def : T_P_pat <S2_interleave, int_hexagon_S2_interleave>; 1137def : T_P_pat <S2_deinterleave, int_hexagon_S2_deinterleave>; 1138 1139// Set/Clear/Toggle Bit 1140def: T_RI_pat<S2_setbit_i, int_hexagon_S2_setbit_i>; 1141def: T_RI_pat<S2_clrbit_i, int_hexagon_S2_clrbit_i>; 1142def: T_RI_pat<S2_togglebit_i, int_hexagon_S2_togglebit_i>; 1143 1144def: T_RR_pat<S2_setbit_r, int_hexagon_S2_setbit_r>; 1145def: T_RR_pat<S2_clrbit_r, int_hexagon_S2_clrbit_r>; 1146def: T_RR_pat<S2_togglebit_r, int_hexagon_S2_togglebit_r>; 1147 1148// Test Bit 1149def: T_Q_RI_pat<S2_tstbit_i, int_hexagon_S2_tstbit_i>; 1150def: T_Q_RR_pat<S2_tstbit_r, int_hexagon_S2_tstbit_r>; 1151 1152//******************************************************************* 1153// STYPE/COMPLEX 1154//******************************************************************* 1155// Vector Complex conjugate 1156def : T_P_pat <A2_vconj, int_hexagon_A2_vconj>; 1157 1158// Vector Complex rotate 1159def : T_PR_pat <S2_vcrotate, int_hexagon_S2_vcrotate>; 1160 1161//******************************************************************* 1162// STYPE/PERM 1163//******************************************************************* 1164 1165// Vector saturate without pack 1166def : T_P_pat <S2_vsathb_nopack, int_hexagon_S2_vsathb_nopack>; 1167def : T_P_pat <S2_vsathub_nopack, int_hexagon_S2_vsathub_nopack>; 1168def : T_P_pat <S2_vsatwh_nopack, int_hexagon_S2_vsatwh_nopack>; 1169def : T_P_pat <S2_vsatwuh_nopack, int_hexagon_S2_vsatwuh_nopack>; 1170 1171//******************************************************************* 1172// STYPE/PRED 1173//******************************************************************* 1174 1175// Predicate transfer 1176def: Pat<(i32 (int_hexagon_C2_tfrpr I32:$Rs)), 1177 (i32 (C2_tfrpr (C2_tfrrp I32:$Rs)))>; 1178def: Pat<(i32 (int_hexagon_C2_tfrrp I32:$Rs)), 1179 (i32 (C2_tfrpr (C2_tfrrp I32:$Rs)))>; 1180 1181// Mask generate from predicate 1182def: Pat<(i64 (int_hexagon_C2_mask I32:$Rs)), 1183 (i64 (C2_mask (C2_tfrrp I32:$Rs)))>; 1184 1185// Viterbi pack even and odd predicate bits 1186def: T_QQ_pat<C2_vitpack, int_hexagon_C2_vitpack>; 1187 1188//******************************************************************* 1189// STYPE/SHIFT 1190//******************************************************************* 1191 1192def : T_PI_pat <S2_asr_i_p, int_hexagon_S2_asr_i_p>; 1193def : T_PI_pat <S2_lsr_i_p, int_hexagon_S2_lsr_i_p>; 1194def : T_PI_pat <S2_asl_i_p, int_hexagon_S2_asl_i_p>; 1195 1196def : T_PR_pat <S2_asr_r_p, int_hexagon_S2_asr_r_p>; 1197def : T_PR_pat <S2_lsr_r_p, int_hexagon_S2_lsr_r_p>; 1198def : T_PR_pat <S2_asl_r_p, int_hexagon_S2_asl_r_p>; 1199def : T_PR_pat <S2_lsl_r_p, int_hexagon_S2_lsl_r_p>; 1200 1201def : T_RR_pat <S2_asr_r_r, int_hexagon_S2_asr_r_r>; 1202def : T_RR_pat <S2_lsr_r_r, int_hexagon_S2_lsr_r_r>; 1203def : T_RR_pat <S2_asl_r_r, int_hexagon_S2_asl_r_r>; 1204def : T_RR_pat <S2_lsl_r_r, int_hexagon_S2_lsl_r_r>; 1205 1206def : T_RR_pat <S2_asr_r_r_sat, int_hexagon_S2_asr_r_r_sat>; 1207def : T_RR_pat <S2_asl_r_r_sat, int_hexagon_S2_asl_r_r_sat>; 1208 1209def : T_R_pat <S2_vsxtbh, int_hexagon_S2_vsxtbh>; 1210def : T_R_pat <S2_vzxtbh, int_hexagon_S2_vzxtbh>; 1211def : T_R_pat <S2_vsxthw, int_hexagon_S2_vsxthw>; 1212def : T_R_pat <S2_vzxthw, int_hexagon_S2_vzxthw>; 1213def : T_R_pat <S2_vsplatrh, int_hexagon_S2_vsplatrh>; 1214def : T_R_pat <A2_sxtw, int_hexagon_A2_sxtw>; 1215 1216// Vector saturate and pack 1217def : T_R_pat <S2_svsathb, int_hexagon_S2_svsathb>; 1218def : T_R_pat <S2_svsathub, int_hexagon_S2_svsathub>; 1219def : T_P_pat <S2_vsathub, int_hexagon_S2_vsathub>; 1220def : T_P_pat <S2_vsatwh, int_hexagon_S2_vsatwh>; 1221def : T_P_pat <S2_vsatwuh, int_hexagon_S2_vsatwuh>; 1222def : T_P_pat <S2_vsathb, int_hexagon_S2_vsathb>; 1223 1224def : T_P_pat <S2_vtrunohb, int_hexagon_S2_vtrunohb>; 1225def : T_P_pat <S2_vtrunehb, int_hexagon_S2_vtrunehb>; 1226def : T_P_pat <S2_vrndpackwh, int_hexagon_S2_vrndpackwh>; 1227def : T_P_pat <S2_vrndpackwhs, int_hexagon_S2_vrndpackwhs>; 1228def : T_R_pat <S2_brev, int_hexagon_S2_brev>; 1229def : T_R_pat <S2_vsplatrb, int_hexagon_S2_vsplatrb>; 1230 1231def : T_R_pat <A2_abs, int_hexagon_A2_abs>; 1232def : T_R_pat <A2_abssat, int_hexagon_A2_abssat>; 1233def : T_R_pat <A2_negsat, int_hexagon_A2_negsat>; 1234 1235def : T_R_pat <A2_swiz, int_hexagon_A2_swiz>; 1236 1237def : T_P_pat <A2_sat, int_hexagon_A2_sat>; 1238def : T_R_pat <A2_sath, int_hexagon_A2_sath>; 1239def : T_R_pat <A2_satuh, int_hexagon_A2_satuh>; 1240def : T_R_pat <A2_satub, int_hexagon_A2_satub>; 1241def : T_R_pat <A2_satb, int_hexagon_A2_satb>; 1242 1243// Vector arithmetic shift right by immediate with truncate and pack. 1244def : T_PI_pat<S2_asr_i_svw_trun, int_hexagon_S2_asr_i_svw_trun>; 1245 1246def : T_RI_pat <S2_asr_i_r, int_hexagon_S2_asr_i_r>; 1247def : T_RI_pat <S2_lsr_i_r, int_hexagon_S2_lsr_i_r>; 1248def : T_RI_pat <S2_asl_i_r, int_hexagon_S2_asl_i_r>; 1249def : T_RI_pat <S2_asr_i_r_rnd, int_hexagon_S2_asr_i_r_rnd>; 1250def : T_RI_pat <S2_asr_i_r_rnd_goodsyntax, 1251 int_hexagon_S2_asr_i_r_rnd_goodsyntax>; 1252 1253// Shift left by immediate with saturation. 1254def : T_RI_pat <S2_asl_i_r_sat, int_hexagon_S2_asl_i_r_sat>; 1255 1256//===----------------------------------------------------------------------===// 1257// Template 'def pat' to map tableidx[bhwd] intrinsics to :raw instructions. 1258//===----------------------------------------------------------------------===// 1259class S2op_tableidx_pat <Intrinsic IntID, InstHexagon OutputInst, 1260 SDNodeXForm XformImm> 1261 : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred:$src3, u5_0ImmPred:$src4), 1262 (OutputInst I32:$src1, I32:$src2, u4_0ImmPred:$src3, 1263 (XformImm u5_0ImmPred:$src4))>; 1264 1265def SDEC2 : SDNodeXForm<imm, [{ 1266 int32_t V = N->getSExtValue(); 1267 return CurDAG->getTargetConstant(V-2, SDLoc(N), MVT::i32); 1268}]>; 1269 1270def SDEC3 : SDNodeXForm<imm, [{ 1271 int32_t V = N->getSExtValue(); 1272 return CurDAG->getTargetConstant(V-3, SDLoc(N), MVT::i32); 1273}]>; 1274 1275// Table Index : Extract and insert bits. 1276// Map to the real hardware instructions after subtracting appropriate 1277// values from the 4th input operand. Please note that subtraction is not 1278// needed for int_hexagon_S2_tableidxb_goodsyntax. 1279 1280def : Pat <(int_hexagon_S2_tableidxb_goodsyntax I32:$src1, I32:$src2, 1281 u4_0ImmPred:$src3, u5_0ImmPred:$src4), 1282 (S2_tableidxb I32:$src1, I32:$src2, 1283 u4_0ImmPred:$src3, u5_0ImmPred:$src4)>; 1284 1285def : S2op_tableidx_pat <int_hexagon_S2_tableidxh_goodsyntax, S2_tableidxh, 1286 SDEC1>; 1287def : S2op_tableidx_pat <int_hexagon_S2_tableidxw_goodsyntax, S2_tableidxw, 1288 SDEC2>; 1289def : S2op_tableidx_pat <int_hexagon_S2_tableidxd_goodsyntax, S2_tableidxd, 1290 SDEC3>; 1291 1292//******************************************************************* 1293// STYPE/VH 1294//******************************************************************* 1295 1296// Vector absolute value halfwords with and without saturation 1297// Rdd64=vabsh(Rss64)[:sat] 1298def : T_P_pat <A2_vabsh, int_hexagon_A2_vabsh>; 1299def : T_P_pat <A2_vabshsat, int_hexagon_A2_vabshsat>; 1300 1301// Vector shift halfwords by immediate 1302// Rdd64=[vaslh/vasrh/vlsrh](Rss64,u4) 1303def : T_PI_pat <S2_asr_i_vh, int_hexagon_S2_asr_i_vh>; 1304def : T_PI_pat <S2_lsr_i_vh, int_hexagon_S2_lsr_i_vh>; 1305def : T_PI_pat <S2_asl_i_vh, int_hexagon_S2_asl_i_vh>; 1306 1307// Vector shift halfwords by register 1308// Rdd64=[vaslw/vasrw/vlslw/vlsrw](Rss64,Rt32) 1309def : T_PR_pat <S2_asr_r_vh, int_hexagon_S2_asr_r_vh>; 1310def : T_PR_pat <S2_lsr_r_vh, int_hexagon_S2_lsr_r_vh>; 1311def : T_PR_pat <S2_asl_r_vh, int_hexagon_S2_asl_r_vh>; 1312def : T_PR_pat <S2_lsl_r_vh, int_hexagon_S2_lsl_r_vh>; 1313 1314//******************************************************************* 1315// STYPE/VW 1316//******************************************************************* 1317 1318// Vector absolute value words with and without saturation 1319def : T_P_pat <A2_vabsw, int_hexagon_A2_vabsw>; 1320def : T_P_pat <A2_vabswsat, int_hexagon_A2_vabswsat>; 1321 1322// Vector shift words by immediate. 1323// Rdd64=[vasrw/vlsrw|vaslw](Rss64,u5) 1324def : T_PI_pat <S2_asr_i_vw, int_hexagon_S2_asr_i_vw>; 1325def : T_PI_pat <S2_lsr_i_vw, int_hexagon_S2_lsr_i_vw>; 1326def : T_PI_pat <S2_asl_i_vw, int_hexagon_S2_asl_i_vw>; 1327 1328// Vector shift words by register. 1329// Rdd64=[vasrw/vlsrw|vaslw|vlslw](Rss64,Rt32) 1330def : T_PR_pat <S2_asr_r_vw, int_hexagon_S2_asr_r_vw>; 1331def : T_PR_pat <S2_lsr_r_vw, int_hexagon_S2_lsr_r_vw>; 1332def : T_PR_pat <S2_asl_r_vw, int_hexagon_S2_asl_r_vw>; 1333def : T_PR_pat <S2_lsl_r_vw, int_hexagon_S2_lsl_r_vw>; 1334 1335// Vector shift words with truncate and pack 1336def : T_PR_pat <S2_asr_r_svw_trun, int_hexagon_S2_asr_r_svw_trun>; 1337 1338// Load/store locked. 1339def : T_R_pat<L2_loadw_locked, int_hexagon_L2_loadw_locked>; 1340def : T_R_pat<L4_loadd_locked, int_hexagon_L4_loadd_locked>; 1341 1342def : Pat<(int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 1343 (C2_tfrpr (S2_storew_locked I32:$Rs, I32:$Rt))>; 1344def : Pat<(int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 1345 (C2_tfrpr (S4_stored_locked I32:$Rs, I64:$Rt))>; 1346 1347//******************************************************************* 1348// ST 1349//******************************************************************* 1350 1351class T_stb_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Val> 1352 : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru), 1353 (MI I32:$Rs, I32:$Ru, Val:$Rt)>; 1354 1355def : T_stb_pat <S2_storerh_pbr, int_hexagon_S2_storerh_pbr, I32>; 1356def : T_stb_pat <S2_storerb_pbr, int_hexagon_S2_storerb_pbr, I32>; 1357def : T_stb_pat <S2_storeri_pbr, int_hexagon_S2_storeri_pbr, I32>; 1358def : T_stb_pat <S2_storerf_pbr, int_hexagon_S2_storerf_pbr, I32>; 1359def : T_stb_pat <S2_storerd_pbr, int_hexagon_S2_storerd_pbr, I64>; 1360 1361class T_stc_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Imm, PatLeaf Val> 1362 : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru, Imm:$s), 1363 (MI I32:$Rs, Imm:$s, I32:$Ru, Val:$Rt)>; 1364 1365def: T_stc_pat<S2_storerb_pci, int_hexagon_circ_stb, s4_0ImmPred, I32>; 1366def: T_stc_pat<S2_storerh_pci, int_hexagon_circ_sth, s4_1ImmPred, I32>; 1367def: T_stc_pat<S2_storeri_pci, int_hexagon_circ_stw, s4_2ImmPred, I32>; 1368def: T_stc_pat<S2_storerd_pci, int_hexagon_circ_std, s4_3ImmPred, I64>; 1369def: T_stc_pat<S2_storerf_pci, int_hexagon_circ_sthhi, s4_1ImmPred, I32>; 1370 1371multiclass MaskedStore <InstHexagon MI, Intrinsic IntID> { 1372 def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), 1373 (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>; 1374 def : Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2, 1375 HvxVR:$src3), 1376 (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>; 1377} 1378 1379defm : MaskedStore <V6_vS32b_qpred_ai, int_hexagon_V6_vmaskedstoreq>; 1380defm : MaskedStore <V6_vS32b_nqpred_ai, int_hexagon_V6_vmaskedstorenq>; 1381defm : MaskedStore <V6_vS32b_nt_qpred_ai, int_hexagon_V6_vmaskedstorentq>; 1382defm : MaskedStore <V6_vS32b_nt_nqpred_ai, int_hexagon_V6_vmaskedstorentnq>; 1383 1384defm : MaskedStore <V6_vS32b_qpred_ai, int_hexagon_V6_vS32b_qpred_ai>; 1385defm : MaskedStore <V6_vS32b_nqpred_ai, int_hexagon_V6_vS32b_nqpred_ai>; 1386defm : MaskedStore <V6_vS32b_nt_qpred_ai, int_hexagon_V6_vS32b_nt_qpred_ai>; 1387defm : MaskedStore <V6_vS32b_nt_nqpred_ai, int_hexagon_V6_vS32b_nt_nqpred_ai>; 1388 1389//******************************************************************* 1390// SYSTEM 1391//******************************************************************* 1392 1393def: T_R_pat<Y2_dccleana, int_hexagon_Y2_dccleana>; 1394def: T_R_pat<Y2_dccleaninva, int_hexagon_Y2_dccleaninva>; 1395def: T_R_pat<Y2_dcinva, int_hexagon_Y2_dcinva>; 1396def: T_R_pat<Y2_dczeroa, int_hexagon_Y2_dczeroa>; 1397 1398def: T_RR_pat<Y4_l2fetch, int_hexagon_Y4_l2fetch>; 1399def: T_RP_pat<Y5_l2fetch, int_hexagon_Y5_l2fetch>; 1400 1401include "HexagonIntrinsicsV3.td" 1402include "HexagonIntrinsicsV4.td" 1403include "HexagonIntrinsicsV5.td" 1404include "HexagonIntrinsicsV60.td" 1405