1//===- HexagonIntrinsicsV4.td - V4 Instruction intrinsics --*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This is populated based on the following specs:
10// Hexagon V4 Architecture Extensions
11// Application-Level Specification
12// 80-V9418-12 Rev. A
13// June 15, 2010
14
15// Vector reduce multiply word by signed half (32x16)
16//Rdd=vrmpyweh(Rss,Rtt)[:<<1]
17def : T_PP_pat <M4_vrmpyeh_s0, int_hexagon_M4_vrmpyeh_s0>;
18def : T_PP_pat <M4_vrmpyeh_s1, int_hexagon_M4_vrmpyeh_s1>;
19
20//Rdd=vrmpywoh(Rss,Rtt)[:<<1]
21def : T_PP_pat <M4_vrmpyoh_s0, int_hexagon_M4_vrmpyoh_s0>;
22def : T_PP_pat <M4_vrmpyoh_s1, int_hexagon_M4_vrmpyoh_s1>;
23
24//Rdd+=vrmpyweh(Rss,Rtt)[:<<1]
25def : T_PPP_pat <M4_vrmpyeh_acc_s0, int_hexagon_M4_vrmpyeh_acc_s0>;
26def : T_PPP_pat <M4_vrmpyeh_acc_s1, int_hexagon_M4_vrmpyeh_acc_s1>;
27
28//Rdd=vrmpywoh(Rss,Rtt)[:<<1]
29def : T_PPP_pat <M4_vrmpyoh_acc_s0, int_hexagon_M4_vrmpyoh_acc_s0>;
30def : T_PPP_pat <M4_vrmpyoh_acc_s1, int_hexagon_M4_vrmpyoh_acc_s1>;
31
32// Vector multiply halfwords, signed by unsigned
33// Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat
34def : T_RR_pat <M2_vmpy2su_s0, int_hexagon_M2_vmpy2su_s0>;
35def : T_RR_pat <M2_vmpy2su_s1, int_hexagon_M2_vmpy2su_s1>;
36
37// Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
38def : T_PRR_pat <M2_vmac2su_s0, int_hexagon_M2_vmac2su_s0>;
39def : T_PRR_pat <M2_vmac2su_s1, int_hexagon_M2_vmac2su_s1>;
40
41// Vector polynomial multiply halfwords
42// Rdd=vpmpyh(Rs,Rt)
43def : T_RR_pat <M4_vpmpyh, int_hexagon_M4_vpmpyh>;
44// Rxx[^]=vpmpyh(Rs,Rt)
45def : T_PRR_pat <M4_vpmpyh_acc, int_hexagon_M4_vpmpyh_acc>;
46
47// Polynomial multiply words
48// Rdd=pmpyw(Rs,Rt)
49def : T_RR_pat <M4_pmpyw, int_hexagon_M4_pmpyw>;
50// Rxx^=pmpyw(Rs,Rt)
51def : T_PRR_pat <M4_pmpyw_acc, int_hexagon_M4_pmpyw_acc>;
52
53//Rxx^=asr(Rss,Rt)
54def : T_PPR_pat <S2_asr_r_p_xor, int_hexagon_S2_asr_r_p_xor>;
55//Rxx^=asl(Rss,Rt)
56def : T_PPR_pat <S2_asl_r_p_xor, int_hexagon_S2_asl_r_p_xor>;
57//Rxx^=lsr(Rss,Rt)
58def : T_PPR_pat <S2_lsr_r_p_xor, int_hexagon_S2_lsr_r_p_xor>;
59//Rxx^=lsl(Rss,Rt)
60def : T_PPR_pat <S2_lsl_r_p_xor, int_hexagon_S2_lsl_r_p_xor>;
61
62// Multiply and use upper result
63def : T_RR_pat <M2_mpysu_up, int_hexagon_M2_mpysu_up>;
64def : T_RR_pat <M2_mpy_up_s1, int_hexagon_M2_mpy_up_s1>;
65def : T_RR_pat <M2_hmmpyh_s1, int_hexagon_M2_hmmpyh_s1>;
66def : T_RR_pat <M2_hmmpyl_s1, int_hexagon_M2_hmmpyl_s1>;
67def : T_RR_pat <M2_mpy_up_s1_sat, int_hexagon_M2_mpy_up_s1_sat>;
68
69def : T_PP_pat <A2_vaddub, int_hexagon_A2_vaddb_map>;
70def : T_PP_pat <A2_vsubub, int_hexagon_A2_vsubb_map>;
71
72// Vector reduce add unsigned halfwords
73def : T_PP_pat <M2_vraddh, int_hexagon_M2_vraddh>;
74
75def: T_P_pat<S2_brevp, int_hexagon_S2_brevp>;
76def: T_P_pat<S2_ct0p,  int_hexagon_S2_ct0p>;
77def: T_P_pat<S2_ct1p,  int_hexagon_S2_ct1p>;
78
79def: T_Q_RR_pat<C4_nbitsset,  int_hexagon_C4_nbitsset>;
80def: T_Q_RR_pat<C4_nbitsclr,  int_hexagon_C4_nbitsclr>;
81def: T_Q_RI_pat<C4_nbitsclri, int_hexagon_C4_nbitsclri>;
82
83def : T_Q_PI_pat<A4_vcmpbeqi,     int_hexagon_A4_vcmpbeqi>;
84def : T_Q_PI_pat<A4_vcmpbgti,     int_hexagon_A4_vcmpbgti>;
85def : T_Q_PI_pat<A4_vcmpbgtui,    int_hexagon_A4_vcmpbgtui>;
86def : T_Q_PI_pat<A4_vcmpheqi,     int_hexagon_A4_vcmpheqi>;
87def : T_Q_PI_pat<A4_vcmphgti,     int_hexagon_A4_vcmphgti>;
88def : T_Q_PI_pat<A4_vcmphgtui,    int_hexagon_A4_vcmphgtui>;
89def : T_Q_PI_pat<A4_vcmpweqi,     int_hexagon_A4_vcmpweqi>;
90def : T_Q_PI_pat<A4_vcmpwgti,     int_hexagon_A4_vcmpwgti>;
91def : T_Q_PI_pat<A4_vcmpwgtui,    int_hexagon_A4_vcmpwgtui>;
92def : T_Q_PP_pat<A4_vcmpbeq_any,  int_hexagon_A4_vcmpbeq_any>;
93
94def : T_Q_RR_pat<A4_cmpbeq,   int_hexagon_A4_cmpbeq>;
95def : T_Q_RR_pat<A4_cmpbgt,   int_hexagon_A4_cmpbgt>;
96def : T_Q_RR_pat<A4_cmpbgtu,  int_hexagon_A4_cmpbgtu>;
97def : T_Q_RR_pat<A4_cmpheq,   int_hexagon_A4_cmpheq>;
98def : T_Q_RR_pat<A4_cmphgt,   int_hexagon_A4_cmphgt>;
99def : T_Q_RR_pat<A4_cmphgtu,  int_hexagon_A4_cmphgtu>;
100
101def : T_Q_RI_pat<A4_cmpbeqi,  int_hexagon_A4_cmpbeqi>;
102def : T_Q_RI_pat<A4_cmpbgti,  int_hexagon_A4_cmpbgti>;
103def : T_Q_RI_pat<A4_cmpbgtui, int_hexagon_A4_cmpbgtui>;
104
105def : T_Q_RI_pat<A4_cmpheqi,  int_hexagon_A4_cmpheqi>;
106def : T_Q_RI_pat<A4_cmphgti,  int_hexagon_A4_cmphgti>;
107def : T_Q_RI_pat<A4_cmphgtui, int_hexagon_A4_cmphgtui>;
108
109def : T_Q_RP_pat<A4_boundscheck, int_hexagon_A4_boundscheck>;
110def : T_Q_PR_pat<A4_tlbmatch,    int_hexagon_A4_tlbmatch>;
111
112def : T_RRR_pat <M4_mpyrr_addr,    int_hexagon_M4_mpyrr_addr>;
113def : T_IRR_pat <M4_mpyrr_addi,    int_hexagon_M4_mpyrr_addi>;
114def : T_IRI_pat <M4_mpyri_addi,    int_hexagon_M4_mpyri_addi>;
115def : T_RIR_pat <M4_mpyri_addr_u2, int_hexagon_M4_mpyri_addr_u2>;
116def : T_RRI_pat <M4_mpyri_addr,    int_hexagon_M4_mpyri_addr>;
117def : T_RRR_pat <M4_mac_up_s1_sat, int_hexagon_M4_mac_up_s1_sat>;
118def : T_RRR_pat <M4_nac_up_s1_sat, int_hexagon_M4_nac_up_s1_sat>;
119
120// Complex multiply 32x16
121def : T_PR_pat <M4_cmpyi_wh, int_hexagon_M4_cmpyi_wh>;
122def : T_PR_pat <M4_cmpyr_wh, int_hexagon_M4_cmpyr_wh>;
123
124def : T_PR_pat <M4_cmpyi_whc, int_hexagon_M4_cmpyi_whc>;
125def : T_PR_pat <M4_cmpyr_whc, int_hexagon_M4_cmpyr_whc>;
126
127def : T_PP_pat<A4_andnp, int_hexagon_A4_andnp>;
128def : T_PP_pat<A4_ornp,  int_hexagon_A4_ornp>;
129
130// Complex add/sub halfwords/words
131def : T_PP_pat <S4_vxaddsubw, int_hexagon_S4_vxaddsubw>;
132def : T_PP_pat <S4_vxsubaddw, int_hexagon_S4_vxsubaddw>;
133def : T_PP_pat <S4_vxaddsubh, int_hexagon_S4_vxaddsubh>;
134def : T_PP_pat <S4_vxsubaddh, int_hexagon_S4_vxsubaddh>;
135
136def : T_PP_pat <S4_vxaddsubhr, int_hexagon_S4_vxaddsubhr>;
137def : T_PP_pat <S4_vxsubaddhr, int_hexagon_S4_vxsubaddhr>;
138
139// Extract bitfield
140def : T_PP_pat  <S4_extractp_rp, int_hexagon_S4_extractp_rp>;
141def : T_RP_pat  <S4_extract_rp, int_hexagon_S4_extract_rp>;
142def : T_PII_pat <S4_extractp, int_hexagon_S4_extractp>;
143def : T_RII_pat <S4_extract, int_hexagon_S4_extract>;
144
145// Vector conditional negate
146// Rdd=vcnegh(Rss,Rt)
147def : T_PR_pat <S2_vcnegh, int_hexagon_S2_vcnegh>;
148
149// Shift an immediate left by register amount
150def : T_IR_pat<S4_lsli, int_hexagon_S4_lsli>;
151
152// Vector reduce maximum halfwords
153def : T_PPR_pat <A4_vrmaxh, int_hexagon_A4_vrmaxh>;
154def : T_PPR_pat <A4_vrmaxuh, int_hexagon_A4_vrmaxuh>;
155
156// Vector reduce maximum words
157def : T_PPR_pat <A4_vrmaxw, int_hexagon_A4_vrmaxw>;
158def : T_PPR_pat <A4_vrmaxuw, int_hexagon_A4_vrmaxuw>;
159
160// Vector reduce minimum halfwords
161def : T_PPR_pat <A4_vrminh, int_hexagon_A4_vrminh>;
162def : T_PPR_pat <A4_vrminuh, int_hexagon_A4_vrminuh>;
163
164// Vector reduce minimum words
165def : T_PPR_pat <A4_vrminw, int_hexagon_A4_vrminw>;
166def : T_PPR_pat <A4_vrminuw, int_hexagon_A4_vrminuw>;
167
168// Rotate and reduce bytes
169def : Pat <(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2,
170                                     u2_0ImmPred:$src3),
171           (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred:$src3)>;
172
173// Rotate and reduce bytes with accumulation
174// Rxx+=vrcrotate(Rss,Rt,#u2)
175def : Pat <(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2,
176                                         IntRegs:$src3, u2_0ImmPred:$src4),
177           (S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2,
178                             IntRegs:$src3, u2_0ImmPred:$src4)>;
179
180// Vector conditional negate
181def : T_PPR_pat<S2_vrcnegh, int_hexagon_S2_vrcnegh>;
182
183// Logical xor with xor accumulation
184def : T_PPP_pat<M4_xor_xacc, int_hexagon_M4_xor_xacc>;
185
186// ALU64 - Vector min/max byte
187def : T_PP_pat <A2_vminb, int_hexagon_A2_vminb>;
188def : T_PP_pat <A2_vmaxb, int_hexagon_A2_vmaxb>;
189
190// Shift and add/sub/and/or
191def : T_IRI_pat <S4_andi_asl_ri, int_hexagon_S4_andi_asl_ri>;
192def : T_IRI_pat <S4_ori_asl_ri,  int_hexagon_S4_ori_asl_ri>;
193def : T_IRI_pat <S4_addi_asl_ri, int_hexagon_S4_addi_asl_ri>;
194def : T_IRI_pat <S4_subi_asl_ri, int_hexagon_S4_subi_asl_ri>;
195def : T_IRI_pat <S4_andi_lsr_ri, int_hexagon_S4_andi_lsr_ri>;
196def : T_IRI_pat <S4_ori_lsr_ri,  int_hexagon_S4_ori_lsr_ri>;
197def : T_IRI_pat <S4_addi_lsr_ri, int_hexagon_S4_addi_lsr_ri>;
198def : T_IRI_pat <S4_subi_lsr_ri, int_hexagon_S4_subi_lsr_ri>;
199
200// Split bitfield
201def : T_RI_pat <A4_bitspliti, int_hexagon_A4_bitspliti>;
202def : T_RR_pat <A4_bitsplit,  int_hexagon_A4_bitsplit>;
203
204def: T_RR_pat<S4_parity,      int_hexagon_S4_parity>;
205
206def: T_Q_RI_pat<S4_ntstbit_i, int_hexagon_S4_ntstbit_i>;
207def: T_Q_RR_pat<S4_ntstbit_r, int_hexagon_S4_ntstbit_r>;
208
209def: T_RI_pat<S4_clbaddi,     int_hexagon_S4_clbaddi>;
210def: T_PI_pat<S4_clbpaddi,    int_hexagon_S4_clbpaddi>;
211def: T_P_pat <S4_clbpnorm,    int_hexagon_S4_clbpnorm>;
212
213//*******************************************************************
214//            ALU32/ALU
215//*******************************************************************
216
217// ALU32 / ALU / Logical Operations.
218def: T_RR_pat<A4_andn, int_hexagon_A4_andn>;
219def: T_RR_pat<A4_orn,  int_hexagon_A4_orn>;
220
221//*******************************************************************
222//            ALU32/PERM
223//*******************************************************************
224
225// Combine Words Into Doublewords.
226def: T_RI_pat<A4_combineri, int_hexagon_A4_combineri, s32_0ImmPred>;
227def: T_IR_pat<A4_combineir, int_hexagon_A4_combineir, s32_0ImmPred>;
228
229//*******************************************************************
230//           ALU32/PRED
231//*******************************************************************
232
233// Compare
234def : T_Q_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi, s32_0ImmPred>;
235def : T_Q_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei, s32_0ImmPred>;
236def : T_Q_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui, u32_0ImmPred>;
237
238// Compare To General Register.
239def: T_Q_RR_pat<C4_cmpneq,  int_hexagon_C4_cmpneq>;
240def: T_Q_RR_pat<C4_cmplte,  int_hexagon_C4_cmplte>;
241def: T_Q_RR_pat<C4_cmplteu, int_hexagon_C4_cmplteu>;
242
243def: T_RR_pat<A4_rcmpeq,  int_hexagon_A4_rcmpeq>;
244def: T_RR_pat<A4_rcmpneq, int_hexagon_A4_rcmpneq>;
245
246def: T_RI_pat<A4_rcmpeqi,  int_hexagon_A4_rcmpeqi>;
247def: T_RI_pat<A4_rcmpneqi, int_hexagon_A4_rcmpneqi>;
248
249//*******************************************************************
250//           CR
251//*******************************************************************
252
253// CR / Logical Operations On Predicates.
254def: T_Q_QQQ_pat<C4_and_and,  int_hexagon_C4_and_and>;
255def: T_Q_QQQ_pat<C4_and_andn, int_hexagon_C4_and_andn>;
256def: T_Q_QQQ_pat<C4_and_or,   int_hexagon_C4_and_or>;
257def: T_Q_QQQ_pat<C4_and_orn,  int_hexagon_C4_and_orn>;
258def: T_Q_QQQ_pat<C4_or_and,   int_hexagon_C4_or_and>;
259def: T_Q_QQQ_pat<C4_or_andn,  int_hexagon_C4_or_andn>;
260def: T_Q_QQQ_pat<C4_or_or,    int_hexagon_C4_or_or>;
261def: T_Q_QQQ_pat<C4_or_orn,   int_hexagon_C4_or_orn>;
262
263//*******************************************************************
264//           XTYPE/ALU
265//*******************************************************************
266
267// Add And Accumulate.
268
269def : T_RRI_pat <S4_addaddi, int_hexagon_S4_addaddi>;
270def : T_RIR_pat <S4_subaddi, int_hexagon_S4_subaddi>;
271
272
273// XTYPE / ALU / Logical-logical Words.
274def : T_RRR_pat <M4_or_xor,   int_hexagon_M4_or_xor>;
275def : T_RRR_pat <M4_and_xor,  int_hexagon_M4_and_xor>;
276def : T_RRR_pat <M4_or_and,   int_hexagon_M4_or_and>;
277def : T_RRR_pat <M4_and_and,  int_hexagon_M4_and_and>;
278def : T_RRR_pat <M4_xor_and,  int_hexagon_M4_xor_and>;
279def : T_RRR_pat <M4_or_or,    int_hexagon_M4_or_or>;
280def : T_RRR_pat <M4_and_or,   int_hexagon_M4_and_or>;
281def : T_RRR_pat <M4_xor_or,   int_hexagon_M4_xor_or>;
282def : T_RRR_pat <M4_or_andn,  int_hexagon_M4_or_andn>;
283def : T_RRR_pat <M4_and_andn, int_hexagon_M4_and_andn>;
284def : T_RRR_pat <M4_xor_andn, int_hexagon_M4_xor_andn>;
285
286def : T_RRI_pat <S4_or_andi, int_hexagon_S4_or_andi>;
287def : T_RRI_pat <S4_or_andix,  int_hexagon_S4_or_andix>;
288def : T_RRI_pat <S4_or_ori, int_hexagon_S4_or_ori>;
289
290// Modulo wrap.
291def : T_RR_pat <A4_modwrapu, int_hexagon_A4_modwrapu>;
292
293// Arithmetic/Convergent round
294// Rd=[cround|round](Rs,Rt)[:sat]
295// Rd=[cround|round](Rs,#u5)[:sat]
296def : T_RI_pat <A4_cround_ri, int_hexagon_A4_cround_ri>;
297def : T_RR_pat <A4_cround_rr, int_hexagon_A4_cround_rr>;
298
299def : T_RI_pat <A4_round_ri, int_hexagon_A4_round_ri>;
300def : T_RR_pat <A4_round_rr, int_hexagon_A4_round_rr>;
301
302def : T_RI_pat <A4_round_ri_sat, int_hexagon_A4_round_ri_sat>;
303def : T_RR_pat <A4_round_rr_sat, int_hexagon_A4_round_rr_sat>;
304
305def : T_P_pat <A2_roundsat, int_hexagon_A2_roundsat>;
306