1 //===- HexagonPacketizer.h - VLIW packetizer --------------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
11 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
12 
13 #include "llvm/CodeGen/DFAPacketizer.h"
14 #include "llvm/CodeGen/MachineBasicBlock.h"
15 #include "llvm/CodeGen/ScheduleDAG.h"
16 #include <vector>
17 
18 namespace llvm {
19 
20 class HexagonInstrInfo;
21 class HexagonRegisterInfo;
22 class MachineBranchProbabilityInfo;
23 class MachineFunction;
24 class MachineInstr;
25 class MachineLoopInfo;
26 class TargetRegisterClass;
27 
28 class HexagonPacketizerList : public VLIWPacketizerList {
29   // Vector of instructions assigned to the packet that has just been created.
30   std::vector<MachineInstr *> OldPacketMIs;
31 
32   // Has the instruction been promoted to a dot-new instruction.
33   bool PromotedToDotNew;
34 
35   // Has the instruction been glued to allocframe.
36   bool GlueAllocframeStore;
37 
38   // Has the feeder instruction been glued to new value jump.
39   bool GlueToNewValueJump;
40 
41   // This holds the offset value, when pruning the dependences.
42   int64_t ChangedOffset;
43 
44   // Check if there is a dependence between some instruction already in this
45   // packet and this instruction.
46   bool Dependence;
47 
48   // Only check for dependence if there are resources available to
49   // schedule this instruction.
50   bool FoundSequentialDependence;
51 
52   bool MemShufDisabled = false;
53 
54   // Track MIs with ignored dependence.
55   std::vector<MachineInstr*> IgnoreDepMIs;
56 
57   // Set to true if the packet contains an instruction that stalls with an
58   // instruction from the previous packet.
59   bool PacketStalls = false;
60 
61 protected:
62   /// A handle to the branch probability pass.
63   const MachineBranchProbabilityInfo *MBPI;
64   const MachineLoopInfo *MLI;
65 
66 private:
67   const HexagonInstrInfo *HII;
68   const HexagonRegisterInfo *HRI;
69 
70 public:
71   HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
72                         AliasAnalysis *AA,
73                         const MachineBranchProbabilityInfo *MBPI);
74 
75   // initPacketizerState - initialize some internal flags.
76   void initPacketizerState() override;
77 
78   // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
79   bool ignorePseudoInstruction(const MachineInstr &MI,
80                                const MachineBasicBlock *MBB) override;
81 
82   // isSoloInstruction - return true if instruction MI can not be packetized
83   // with any other instruction, which means that MI itself is a packet.
84   bool isSoloInstruction(const MachineInstr &MI) override;
85 
86   // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
87   // together.
88   bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;
89 
90   // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
91   // and SUJ.
92   bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
93 
94   bool foundLSInPacket();
95   MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override;
96   void endPacket(MachineBasicBlock *MBB,
97                  MachineBasicBlock::iterator MI) override;
98   bool shouldAddToPacket(const MachineInstr &MI) override;
99 
100   void unpacketizeSoloInstrs(MachineFunction &MF);
101 
102 protected:
getmemShufDisabled()103   bool getmemShufDisabled() {
104     return MemShufDisabled;
105   };
setmemShufDisabled(bool val)106   void setmemShufDisabled(bool val) {
107     MemShufDisabled = val;
108   };
109   bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
110                        unsigned DepReg);
111   bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
112                        MachineBasicBlock::iterator &MII,
113                        const TargetRegisterClass *RC);
114   bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU,
115                           unsigned DepReg, MachineBasicBlock::iterator &MII,
116                           const TargetRegisterClass *RC);
117   void cleanUpDotCur();
118 
119   bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType,
120                        MachineBasicBlock::iterator &MII,
121                        const TargetRegisterClass *RC);
122   bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU,
123                           unsigned DepReg, MachineBasicBlock::iterator &MII,
124                           const TargetRegisterClass *RC);
125   bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU,
126                             unsigned DepReg, MachineBasicBlock::iterator &MII);
127   bool canPromoteToNewValueStore(const MachineInstr &MI,
128                                  const MachineInstr &PacketMI, unsigned DepReg);
129   bool demoteToDotOld(MachineInstr &MI);
130   bool useCallersSP(MachineInstr &MI);
131   void useCalleesSP(MachineInstr &MI);
132   bool updateOffset(SUnit *SUI, SUnit *SUJ);
133   void undoChangedOffset(MachineInstr &MI);
134   bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
135   bool restrictingDepExistInPacket(MachineInstr&, unsigned);
136   bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
137   bool isCurifiable(MachineInstr &MI);
138   bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ);
139 
isPromotedToDotNew()140   bool isPromotedToDotNew() const {
141     return PromotedToDotNew;
142   }
143 
144   bool tryAllocateResourcesForConstExt(bool Reserve);
145   bool canReserveResourcesForConstExt();
146   void reserveResourcesForConstExt();
147   bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J);
148   bool hasControlDependence(const MachineInstr &I, const MachineInstr &J);
149   bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J);
150   bool hasV4SpecificDependence(const MachineInstr &I, const MachineInstr &J);
151   bool producesStall(const MachineInstr &MI);
152 };
153 
154 } // end namespace llvm
155 
156 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
157