1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides Mips specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "MipsMCTargetDesc.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsAsmBackend.h"
17 #include "MipsELFStreamer.h"
18 #include "MipsMCAsmInfo.h"
19 #include "MipsMCNaCl.h"
20 #include "MipsTargetStreamer.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCELFStreamer.h"
24 #include "llvm/MC/MCInstrAnalysis.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCObjectWriter.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/MC/MachineLocation.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/FormattedStream.h"
33 #include "llvm/Support/TargetRegistry.h"
34
35 using namespace llvm;
36
37 #define GET_INSTRINFO_MC_DESC
38 #include "MipsGenInstrInfo.inc"
39
40 #define GET_SUBTARGETINFO_MC_DESC
41 #include "MipsGenSubtargetInfo.inc"
42
43 #define GET_REGINFO_MC_DESC
44 #include "MipsGenRegisterInfo.inc"
45
46 /// Select the Mips CPU for the given triple and cpu name.
47 /// FIXME: Merge with the copy in MipsSubtarget.cpp
selectMipsCPU(const Triple & TT,StringRef CPU)48 StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
49 if (CPU.empty() || CPU == "generic") {
50 if (TT.isMIPS32())
51 CPU = "mips32";
52 else
53 CPU = "mips64";
54 }
55 return CPU;
56 }
57
createMipsMCInstrInfo()58 static MCInstrInfo *createMipsMCInstrInfo() {
59 MCInstrInfo *X = new MCInstrInfo();
60 InitMipsMCInstrInfo(X);
61 return X;
62 }
63
createMipsMCRegisterInfo(const Triple & TT)64 static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
65 MCRegisterInfo *X = new MCRegisterInfo();
66 InitMipsMCRegisterInfo(X, Mips::RA);
67 return X;
68 }
69
createMipsMCSubtargetInfo(const Triple & TT,StringRef CPU,StringRef FS)70 static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
71 StringRef CPU, StringRef FS) {
72 CPU = MIPS_MC::selectMipsCPU(TT, CPU);
73 return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
74 }
75
createMipsMCAsmInfo(const MCRegisterInfo & MRI,const Triple & TT)76 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
77 const Triple &TT) {
78 MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
79
80 unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
81 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
82 MAI->addInitialFrameState(Inst);
83
84 return MAI;
85 }
86
createMipsMCInstPrinter(const Triple & T,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)87 static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
88 unsigned SyntaxVariant,
89 const MCAsmInfo &MAI,
90 const MCInstrInfo &MII,
91 const MCRegisterInfo &MRI) {
92 return new MipsInstPrinter(MAI, MII, MRI);
93 }
94
createMCStreamer(const Triple & T,MCContext & Context,std::unique_ptr<MCAsmBackend> && MAB,std::unique_ptr<MCObjectWriter> && OW,std::unique_ptr<MCCodeEmitter> && Emitter,bool RelaxAll)95 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
96 std::unique_ptr<MCAsmBackend> &&MAB,
97 std::unique_ptr<MCObjectWriter> &&OW,
98 std::unique_ptr<MCCodeEmitter> &&Emitter,
99 bool RelaxAll) {
100 MCStreamer *S;
101 if (!T.isOSNaCl())
102 S = createMipsELFStreamer(Context, std::move(MAB), std::move(OW),
103 std::move(Emitter), RelaxAll);
104 else
105 S = createMipsNaClELFStreamer(Context, std::move(MAB), std::move(OW),
106 std::move(Emitter), RelaxAll);
107 return S;
108 }
109
createMipsAsmTargetStreamer(MCStreamer & S,formatted_raw_ostream & OS,MCInstPrinter * InstPrint,bool isVerboseAsm)110 static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S,
111 formatted_raw_ostream &OS,
112 MCInstPrinter *InstPrint,
113 bool isVerboseAsm) {
114 return new MipsTargetAsmStreamer(S, OS);
115 }
116
createMipsNullTargetStreamer(MCStreamer & S)117 static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) {
118 return new MipsTargetStreamer(S);
119 }
120
121 static MCTargetStreamer *
createMipsObjectTargetStreamer(MCStreamer & S,const MCSubtargetInfo & STI)122 createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
123 return new MipsTargetELFStreamer(S, STI);
124 }
125
126 namespace {
127
128 class MipsMCInstrAnalysis : public MCInstrAnalysis {
129 public:
MipsMCInstrAnalysis(const MCInstrInfo * Info)130 MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
131
evaluateBranch(const MCInst & Inst,uint64_t Addr,uint64_t Size,uint64_t & Target) const132 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
133 uint64_t &Target) const override {
134 unsigned NumOps = Inst.getNumOperands();
135 if (NumOps == 0)
136 return false;
137 switch (Info->get(Inst.getOpcode()).OpInfo[NumOps - 1].OperandType) {
138 case MCOI::OPERAND_UNKNOWN:
139 case MCOI::OPERAND_IMMEDIATE:
140 // jal, bal ...
141 Target = Inst.getOperand(NumOps - 1).getImm();
142 return true;
143 case MCOI::OPERAND_PCREL:
144 // b, j, beq ...
145 Target = Addr + Inst.getOperand(NumOps - 1).getImm();
146 return true;
147 default:
148 return false;
149 }
150 }
151 };
152 }
153
createMipsMCInstrAnalysis(const MCInstrInfo * Info)154 static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) {
155 return new MipsMCInstrAnalysis(Info);
156 }
157
LLVMInitializeMipsTargetMC()158 extern "C" void LLVMInitializeMipsTargetMC() {
159 for (Target *T : {&getTheMipsTarget(), &getTheMipselTarget(),
160 &getTheMips64Target(), &getTheMips64elTarget()}) {
161 // Register the MC asm info.
162 RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
163
164 // Register the MC instruction info.
165 TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo);
166
167 // Register the MC register info.
168 TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo);
169
170 // Register the elf streamer.
171 TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
172
173 // Register the asm target streamer.
174 TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer);
175
176 TargetRegistry::RegisterNullTargetStreamer(*T,
177 createMipsNullTargetStreamer);
178
179 // Register the MC subtarget info.
180 TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo);
181
182 // Register the MC instruction analyzer.
183 TargetRegistry::RegisterMCInstrAnalysis(*T, createMipsMCInstrAnalysis);
184
185 // Register the MCInstPrinter.
186 TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter);
187
188 TargetRegistry::RegisterObjectTargetStreamer(
189 *T, createMipsObjectTargetStreamer);
190
191 // Register the asm backend.
192 TargetRegistry::RegisterMCAsmBackend(*T, createMipsAsmBackend);
193 }
194
195 // Register the MC Code Emitter
196 for (Target *T : {&getTheMipsTarget(), &getTheMips64Target()})
197 TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB);
198
199 for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()})
200 TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL);
201 }
202