1//===-- PPCScheduleE500.td - e500 Scheduling Defs ------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the Freescale e500 32-bit
11// Power processor.
12//
13// All information is derived from the "e500 Core Reference Manual",
14// Freescale Document Number E500MCRM, Rev. 1, 03/2012.
15//
16//===----------------------------------------------------------------------===//
17// Relevant functional units in the Freescale e500 core:
18//
19//  * Decode & Dispatch
20//    Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
21//    queues (GIQx) or Branch issue queue (BIQ).
22def E500_DIS0 : FuncUnit; // Dispatch stage - insn 1
23def E500_DIS1 : FuncUnit; // Dispatch stage - insn 2
24
25//  * Execute
26//    6 pipelined execution units: SU0, SU1, BU, LSU, MU.
27//    Some instructions can only execute in SU0 but not SU1.
28def E500_SU0  : FuncUnit; // Simple unit 0
29def E500_SU1  : FuncUnit; // Simple unit 1
30def E500_BU    : FuncUnit; // Branch unit
31def E500_MU    : FuncUnit; // MU pipeline
32def E500_LSU_0 : FuncUnit; // LSU pipeline
33
34def E500_GPR_Bypass : Bypass;
35def E500_CR_Bypass  : Bypass;
36def E500_DivBypass  : Bypass;
37
38def PPCE500Itineraries : ProcessorItineraries<
39  [E500_DIS0, E500_DIS1, E500_SU0, E500_SU1, E500_BU,
40   E500_MU, E500_LSU_0],
41  [E500_CR_Bypass, E500_GPR_Bypass, E500_DivBypass], [
42  InstrItinData<IIC_IntSimple,   [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
43                                  InstrStage<1, [E500_SU0, E500_SU1]>],
44                                 [4, 1, 1], // Latency = 1
45                                 [E500_GPR_Bypass,
46                                  E500_GPR_Bypass, E500_GPR_Bypass]>,
47  InstrItinData<IIC_IntGeneral,  [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
48                                  InstrStage<1, [E500_SU0, E500_SU1]>],
49                                 [4, 1, 1], // Latency = 1
50                                 [E500_GPR_Bypass,
51                                  E500_GPR_Bypass, E500_GPR_Bypass]>,
52  InstrItinData<IIC_IntISEL,     [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
53                                  InstrStage<1, [E500_SU0, E500_SU1]>],
54                                 [4, 1, 1, 1], // Latency = 1
55                                 [E500_GPR_Bypass,
56                                  E500_GPR_Bypass, E500_GPR_Bypass,
57                                  E500_CR_Bypass]>,
58  InstrItinData<IIC_IntCompare,  [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
59                                  InstrStage<1, [E500_SU0, E500_SU1]>],
60                                 [5, 1, 1], // Latency = 1 or 2
61                                 [E500_CR_Bypass,
62                                  E500_GPR_Bypass, E500_GPR_Bypass]>,
63  InstrItinData<IIC_IntDivW,     [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
64                                  InstrStage<1, [E500_MU], 0>,
65                                  InstrStage<14, [E500_MU]>],
66                                 [17, 1, 1], // Latency=4..35, Repeat= 4..35
67                                 [E500_GPR_Bypass,
68                                  E500_GPR_Bypass, E500_GPR_Bypass]>,
69  InstrItinData<IIC_IntMulHW,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
70                                  InstrStage<4, [E500_MU]>],
71                                 [7, 1, 1], // Latency = 4, Repeat rate = 1
72                                 [E500_GPR_Bypass,
73                                  E500_GPR_Bypass, E500_GPR_Bypass]>,
74  InstrItinData<IIC_IntMulHWU,   [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
75                                  InstrStage<4, [E500_MU]>],
76                                 [7, 1, 1], // Latency = 4, Repeat rate = 1
77                                 [E500_GPR_Bypass,
78                                  E500_GPR_Bypass, E500_GPR_Bypass]>,
79  InstrItinData<IIC_IntMulLI,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
80                                  InstrStage<4, [E500_MU]>],
81                                 [7, 1, 1], // Latency = 4, Repeat rate = 1
82                                 [E500_GPR_Bypass,
83                                  E500_GPR_Bypass, E500_GPR_Bypass]>,
84  InstrItinData<IIC_IntRotate,   [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
85                                  InstrStage<1, [E500_SU0, E500_SU1]>],
86                                 [4, 1, 1], // Latency = 1
87                                 [E500_GPR_Bypass,
88                                  E500_GPR_Bypass, E500_GPR_Bypass]>,
89  InstrItinData<IIC_IntShift,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
90                                  InstrStage<1, [E500_SU0, E500_SU1]>],
91                                 [4, 1, 1], // Latency = 1
92                                 [E500_GPR_Bypass,
93                                  E500_GPR_Bypass, E500_GPR_Bypass]>,
94  InstrItinData<IIC_IntTrapW,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
95                                  InstrStage<2, [E500_SU0]>],
96                                 [5, 1], // Latency = 2, Repeat rate = 2
97                                 [E500_GPR_Bypass, E500_GPR_Bypass]>,
98  InstrItinData<IIC_BrB,         [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
99                                  InstrStage<1, [E500_BU]>],
100                                 [4, 1], // Latency = 1
101                                 [NoBypass, E500_GPR_Bypass]>,
102  InstrItinData<IIC_BrCR,        [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
103                                  InstrStage<1, [E500_BU]>],
104                                 [4, 1, 1], // Latency = 1
105                                 [E500_CR_Bypass,
106                                  E500_CR_Bypass, E500_CR_Bypass]>,
107  InstrItinData<IIC_BrMCR,       [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
108                                  InstrStage<1, [E500_BU]>],
109                                 [4, 1], // Latency = 1
110                                 [E500_CR_Bypass, E500_CR_Bypass]>,
111  InstrItinData<IIC_BrMCRX,      [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
112                                  InstrStage<1, [E500_SU0, E500_SU1]>],
113                                 [4, 1, 1], // Latency = 1
114                                 [E500_CR_Bypass, E500_GPR_Bypass]>,
115  InstrItinData<IIC_LdStDCBA,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
116                                  InstrStage<1, [E500_LSU_0]>],
117                                 [6, 1], // Latency = 3, Repeat rate = 1
118                                 [E500_GPR_Bypass, E500_GPR_Bypass]>,
119  InstrItinData<IIC_LdStDCBF,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
120                                  InstrStage<1, [E500_LSU_0]>],
121                                 [6, 1], // Latency = 3
122                                 [E500_GPR_Bypass, E500_GPR_Bypass]>,
123  InstrItinData<IIC_LdStDCBI,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
124                                  InstrStage<1, [E500_LSU_0]>],
125                                 [6, 1], // Latency = 3
126                                 [E500_GPR_Bypass, E500_GPR_Bypass]>,
127  InstrItinData<IIC_LdStLoad,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
128                                  InstrStage<1, [E500_LSU_0]>],
129                                 [6, 1], // Latency = 3
130                                 [E500_GPR_Bypass, E500_GPR_Bypass]>,
131  InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
132                                  InstrStage<1, [E500_SU0, E500_SU1], 0>,
133                                  InstrStage<1, [E500_LSU_0]>],
134                                 [6, 1], // Latency = 3
135                                 [E500_GPR_Bypass, E500_GPR_Bypass],
136                                 2>, // 2 micro-ops
137  InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
138                                  InstrStage<1, [E500_SU0, E500_SU1], 0>,
139                                  InstrStage<1, [E500_LSU_0]>],
140                                 [6, 1], // Latency = 3
141                                 [E500_GPR_Bypass, E500_GPR_Bypass],
142                                 2>, // 2 micro-ops
143  InstrItinData<IIC_LdStStore,   [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
144                                  InstrStage<1, [E500_LSU_0]>],
145                                 [6, 1], // Latency = 3
146                                 [NoBypass, E500_GPR_Bypass]>,
147  InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
148                                  InstrStage<1, [E500_SU0, E500_SU1], 0>,
149                                  InstrStage<1, [E500_LSU_0]>],
150                                 [6, 1], // Latency = 3
151                                 [NoBypass, E500_GPR_Bypass],
152                                 2>, // 2 micro-ops
153  InstrItinData<IIC_LdStICBI,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
154                                  InstrStage<1, [E500_LSU_0]>],
155                                 [6, 1], // Latency = 3
156                                 [NoBypass, E500_GPR_Bypass]>,
157  InstrItinData<IIC_LdStLHA,     [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
158                                  InstrStage<1, [E500_LSU_0]>],
159                                 [6, 1], // Latency = 3
160                                 [E500_GPR_Bypass, E500_GPR_Bypass]>,
161  InstrItinData<IIC_LdStLHAU,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
162                                  InstrStage<1, [E500_SU0, E500_SU1], 0>,
163                                  InstrStage<1, [E500_LSU_0]>],
164                                 [6, 1], // Latency = 3
165                                 [E500_GPR_Bypass, E500_GPR_Bypass]>,
166  InstrItinData<IIC_LdStLHAUX,   [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
167                                  InstrStage<1, [E500_SU0, E500_SU1], 0>,
168                                  InstrStage<1, [E500_LSU_0]>],
169                                 [6, 1], // Latency = 3
170                                 [E500_GPR_Bypass, E500_GPR_Bypass]>,
171  InstrItinData<IIC_LdStLMW,     [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
172                                  InstrStage<1, [E500_LSU_0]>],
173                                 [7, 1], // Latency = r+3
174                                 [NoBypass, E500_GPR_Bypass]>,
175  InstrItinData<IIC_LdStLWARX,   [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
176                                  InstrStage<3, [E500_LSU_0]>],
177                                 [6, 1, 1], // Latency = 3, Repeat rate = 3
178                                 [E500_GPR_Bypass,
179                                  E500_GPR_Bypass, E500_GPR_Bypass]>,
180  InstrItinData<IIC_LdStSTWCX,   [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
181                                  InstrStage<1, [E500_LSU_0]>],
182                                 [6, 1], // Latency = 3
183                                 [NoBypass, E500_GPR_Bypass]>,
184  InstrItinData<IIC_LdStSync,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
185                                  InstrStage<1, [E500_LSU_0]>]>,
186  InstrItinData<IIC_SprMFSR,     [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
187                                  InstrStage<4, [E500_SU0]>],
188                                 [7, 1],
189                                 [E500_GPR_Bypass, E500_GPR_Bypass]>,
190  InstrItinData<IIC_SprMTMSR,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
191                                  InstrStage<2, [E500_SU0, E500_SU1]>],
192                                 [5, 1], // Latency = 2, Repeat rate = 4
193                                 [E500_GPR_Bypass, E500_GPR_Bypass]>,
194  InstrItinData<IIC_SprMTSR,     [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
195                                  InstrStage<1, [E500_SU0]>],
196                                 [5, 1],
197                                 [NoBypass, E500_GPR_Bypass]>,
198  InstrItinData<IIC_SprTLBSYNC,  [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
199                                  InstrStage<1, [E500_LSU_0], 0>]>,
200  InstrItinData<IIC_SprMFCR,     [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
201                                  InstrStage<5, [E500_SU0]>],
202                                 [8, 1],
203                                 [E500_GPR_Bypass, E500_CR_Bypass]>,
204  InstrItinData<IIC_SprMFCRF,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
205                                  InstrStage<5, [E500_SU0]>],
206                                 [8, 1],
207                                 [E500_GPR_Bypass, E500_CR_Bypass]>,
208  InstrItinData<IIC_SprMFPMR,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
209                                  InstrStage<4, [E500_SU0]>],
210                                 [7, 1], // Latency = 4, Repeat rate = 4
211                                 [E500_GPR_Bypass, E500_GPR_Bypass]>,
212  InstrItinData<IIC_SprMFMSR,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
213                                  InstrStage<4, [E500_SU0]>],
214                                 [7, 1], // Latency = 4, Repeat rate = 4
215                                 [E500_GPR_Bypass, E500_GPR_Bypass]>,
216  InstrItinData<IIC_SprMFSPR,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
217                                  InstrStage<1, [E500_SU0, E500_SU1]>],
218                                 [4, 1], // Latency = 1, Repeat rate = 1
219                                 [E500_GPR_Bypass, E500_CR_Bypass]>,
220  InstrItinData<IIC_SprMTPMR,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
221                                  InstrStage<1, [E500_SU0]>],
222                                 [4, 1], // Latency = 1, Repeat rate = 1
223                                 [E500_CR_Bypass, E500_GPR_Bypass]>,
224  InstrItinData<IIC_SprMFTB,     [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
225                                  InstrStage<4, [E500_SU0]>],
226                                 [7, 1], // Latency = 4, Repeat rate = 4
227                                 [NoBypass, E500_GPR_Bypass]>,
228  InstrItinData<IIC_SprMTSPR,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
229                                  InstrStage<1, [E500_SU0, E500_SU1]>],
230                                 [4, 1], // Latency = 1, Repeat rate = 1
231                                 [E500_CR_Bypass, E500_GPR_Bypass]>,
232  InstrItinData<IIC_SprMTSRIN,   [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
233                                  InstrStage<1, [E500_SU0]>],
234                                 [4, 1],
235                                 [NoBypass, E500_GPR_Bypass]>,
236  InstrItinData<IIC_FPDGeneral,  [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
237                                  InstrStage<6, [E500_MU]>],
238                                 [9, 1, 1],  // Latency = 6, Repeat rate = 1
239                                 [NoBypass]>,
240  InstrItinData<IIC_FPSGeneral,  [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
241                                  InstrStage<4, [E500_MU]>],
242                                 [7, 1, 1],  // Latency = 4, Repeat rate = 1
243                                 [NoBypass]>,
244  InstrItinData<IIC_FPDivD,      [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
245                                  InstrStage<32, [E500_MU]>],
246                                 [35, 1, 1], // Latency = 32, Repeat rate = 32
247                                 [E500_DivBypass]>,
248  InstrItinData<IIC_FPDivS,      [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
249                                  InstrStage<29, [E500_MU]>],
250                                 [32, 1, 1], // Latency = 29, Repeat rate = 29
251                                 [E500_DivBypass]>,
252  InstrItinData<IIC_VecGeneral,  [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
253                                  InstrStage<1, [E500_SU0]>],
254                                 [4, 1, 1], // Latency = 1, Repeat rate = 1
255                                 [NoBypass]>,
256  InstrItinData<IIC_VecComplex,  [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
257                                  InstrStage<4, [E500_MU]>],
258                                 [7, 1, 1], // Latency = 4, Repeat rate = 1
259                                 [NoBypass]>
260]>;
261
262// ===---------------------------------------------------------------------===//
263// e500 machine model for scheduling and other instruction cost heuristics.
264
265def PPCE500Model : SchedMachineModel {
266  let IssueWidth = 2;  // 2 micro-ops are dispatched per cycle.
267  let LoadLatency = 5; // Optimistic load latency assuming bypass.
268                       // This is overriden by OperandCycles if the
269                       // Itineraries are queried instead.
270
271  let CompleteModel = 0;
272
273  let Itineraries = PPCE500Itineraries;
274}
275