1//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10include "llvm/Target/Target.td"
11
12//===----------------------------------------------------------------------===//
13// RISC-V subtarget features and instruction predicates.
14//===----------------------------------------------------------------------===//
15
16def FeatureStdExtM
17    : SubtargetFeature<"m", "HasStdExtM", "true",
18                       "'M' (Integer Multiplication and Division)">;
19def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
20                           AssemblerPredicate<"FeatureStdExtM">;
21
22def FeatureStdExtA
23    : SubtargetFeature<"a", "HasStdExtA", "true",
24                       "'A' (Atomic Instructions)">;
25def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
26                           AssemblerPredicate<"FeatureStdExtA">;
27
28def FeatureStdExtF
29    : SubtargetFeature<"f", "HasStdExtF", "true",
30                       "'F' (Single-Precision Floating-Point)">;
31def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
32                           AssemblerPredicate<"FeatureStdExtF">;
33
34def FeatureStdExtD
35    : SubtargetFeature<"d", "HasStdExtD", "true",
36                       "'D' (Double-Precision Floating-Point)",
37                       [FeatureStdExtF]>;
38def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
39                           AssemblerPredicate<"FeatureStdExtD">;
40
41def FeatureStdExtC
42    : SubtargetFeature<"c", "HasStdExtC", "true",
43                       "'C' (Compressed Instructions)">;
44def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
45                           AssemblerPredicate<"FeatureStdExtC">;
46
47
48def Feature64Bit
49    : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
50def IsRV64 : Predicate<"Subtarget->is64Bit()">,
51                       AssemblerPredicate<"Feature64Bit">;
52def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
53                       AssemblerPredicate<"!Feature64Bit">;
54
55def RV64           : HwMode<"+64bit">;
56def RV32           : HwMode<"-64bit">;
57
58def FeatureRelax
59    : SubtargetFeature<"relax", "EnableLinkerRelax", "true",
60                       "Enable Linker relaxation.">;
61
62//===----------------------------------------------------------------------===//
63// Registers, calling conventions, instruction descriptions.
64//===----------------------------------------------------------------------===//
65
66include "RISCVRegisterInfo.td"
67include "RISCVCallingConv.td"
68include "RISCVInstrInfo.td"
69
70//===----------------------------------------------------------------------===//
71// RISC-V processors supported.
72//===----------------------------------------------------------------------===//
73
74def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
75
76def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
77
78//===----------------------------------------------------------------------===//
79// Define the RISC-V target.
80//===----------------------------------------------------------------------===//
81
82def RISCVInstrInfo : InstrInfo {
83  let guessInstructionProperties = 0;
84}
85
86def RISCVAsmParser : AsmParser {
87  let ShouldEmitMatchRegisterAltName = 1;
88  let AllowDuplicateRegisterNames = 1;
89}
90
91def RISCVAsmWriter : AsmWriter {
92  int PassSubtarget = 1;
93}
94
95def RISCV : Target {
96  let InstructionSet = RISCVInstrInfo;
97  let AssemblyParsers = [RISCVAsmParser];
98  let AssemblyWriters = [RISCVAsmWriter];
99  let AllowRegisterRenaming = 1;
100}
101